2 * (C) Copyright 2000-2004
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 * Klaus Heydeck, Kieback & Peter GmbH & Co KG, heydeck@kieback-peter.de
6 * See file CREDITS for list of people who contributed to this
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 * board/config.h - configuration options, board specific
27 * Derived from ../tqm8xx/tqm8xx.c
34 * High Level Configuration Options
38 #define CONFIG_MPC855 1 /* This is a MPC855 CPU */
39 #define CONFIG_KUP4K 1 /* ...on a KUP4K module */
41 #define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
42 #undef CONFIG_8xx_CONS_SMC2
43 #undef CONFIG_8xx_CONS_NONE
44 #define CONFIG_BAUDRATE 115200 /* console baudrate */
46 #define CONFIG_BOOTDELAY -1 /* autoboot disabled */
48 #define CONFIG_BOOTDELAY 1 /* autoboot after 1 second */
51 #define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */
53 #define CONFIG_BOARD_TYPES 1 /* support board types */
56 #undef CONFIG_BOOTARGS
59 #define CONFIG_EXTRA_ENV_SETTINGS \
60 "slot_a_boot=setenv bootargs root=/dev/hda2 ip=off;" \
61 "run addhw; diskboot 200000 0:1; bootm 200000\0" \
62 "slot_b_boot=setenv bootargs root=/dev/hda2 ip=off;" \
63 "run addhw; diskboot 200000 2:1; bootm 200000\0" \
64 "nfs_boot=dhcp; run nfsargs addip addhw; bootm 200000\0" \
65 "panic_boot=echo No Bootdevice !!! reset\0" \
66 "nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath)\0" \
67 "ramargs=setenv bootargs root=/dev/ram rw\0" \
68 "addip=setenv bootargs $(bootargs) ip=$(ipaddr):$(serverip):$(gatewayip)" \
69 ":$(netmask):$(hostname):$(netdev):off\0" \
70 "addhw=setenv bootargs $(bootargs) hw=$(hw) key1=$(key1) panic=1\0" \
74 "load=tftp 200000 bootloader-4k.bitmap;tftp 100000 bootloader-4k.bin\0" \
75 "update=protect off 1:0-5;era 1:0-5;cp.b 100000 40000000 $(filesize);" \
76 "cp.b 200000 40040000 14000\0"
78 #define CONFIG_BOOTCOMMAND \
79 "run slot_a_boot;run slot_b_boot;run nfs_boot;run panic_boot"
82 #define CONFIG_MISC_INIT_R 1
83 #define CONFIG_MISC_INIT_F 1
85 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
86 #undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */
88 #undef CONFIG_WATCHDOG /* watchdog disabled */
90 #define CONFIG_STATUS_LED 1 /* Status LED enabled */
92 #undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */
94 #define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
96 #define CONFIG_MAC_PARTITION
97 #define CONFIG_DOS_PARTITION
99 #define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
101 #define CONFIG_HARD_I2C
102 #define CFG_I2C_SPEED 40000
103 #define CFG_I2C_SLAVE 0x7F
105 #define CONFIG_ETHADDR 00:0B:64:00:00:00 /* our OUI from IEEE */
106 #define CONFIG_KUP4K_LOGO 0x40040000 /* Address of logo bitmap */
108 /* Define to allow the user to overwrite serial and ethaddr */
109 #define CONFIG_ENV_OVERWRITE
111 #define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
117 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
118 #include <cmd_confdefs.h>
121 * Miscellaneous configurable options
123 #define CFG_LONGHELP /* undef to save memory */
124 #define CFG_PROMPT "=> " /* Monitor Command Prompt */
125 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
126 #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
128 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
130 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
131 #define CFG_MAXARGS 16 /* max number of command args */
132 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
134 #define CFG_MEMTEST_START 0x000400000 /* memtest works on */
135 #define CFG_MEMTEST_END 0x002C00000 /* 4 ... 44 MB in DRAM */
137 #define CFG_LOAD_ADDR 0x200000 /* default load address */
139 #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
141 #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 115200 }
143 #define CFG_CONSOLE_INFO_QUIET 1
146 * Low Level Configuration Settings
147 * (address mappings, register initial values, etc.)
148 * You should know what you are doing if you make changes here.
150 /*-----------------------------------------------------------------------
151 * Internal Memory Mapped Register
153 #define CFG_IMMR 0xFFF00000
155 /*-----------------------------------------------------------------------
156 * Definitions for initial stack pointer and data area (in DPRAM)
158 #define CFG_INIT_RAM_ADDR CFG_IMMR
159 #define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
160 #define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
161 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
162 #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
164 /*-----------------------------------------------------------------------
165 * Start addresses for the final memory configuration
166 * (Set up by the startup code)
167 * Please note that CFG_SDRAM_BASE _must_ start at 0
169 #define CFG_SDRAM_BASE 0x00000000
170 #define CFG_FLASH_BASE 0x40000000
171 #define CFG_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
172 #define CFG_MONITOR_BASE CFG_FLASH_BASE
173 #define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
176 * For booting Linux, the board info and command line data
177 * have to be in the first 8 MB of memory, since this is
178 * the maximum mapped by the Linux kernel during initialization.
180 #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
182 /*-----------------------------------------------------------------------
185 #define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
186 #define CFG_MAX_FLASH_SECT 19 /* max number of sectors on one chip */
188 #define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
189 #define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
191 #define CFG_ENV_IS_IN_FLASH 1
192 #define CFG_ENV_OFFSET 0x30000 /* Offset of Environment Sector */
193 #define CFG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */
194 #define CFG_ENV_SECT_SIZE 0x10000
196 /* Address and size of Redundant Environment Sector */
198 #define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SIZE)
199 #define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
201 /*-----------------------------------------------------------------------
202 * Hardware Information Block
205 #define CFG_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */
206 #define CFG_HWINFO_SIZE 0x00000040 /* size of HW Info block */
207 #define CFG_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */
209 /*-----------------------------------------------------------------------
210 * Cache Configuration
212 #define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
213 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
214 #define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
217 /*-----------------------------------------------------------------------
218 * SYPCR - System Protection Control 11-9
219 * SYPCR can only be written once after reset!
220 *-----------------------------------------------------------------------
221 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
223 #if defined(CONFIG_WATCHDOG)
224 #define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
225 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
227 #define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
230 /*-----------------------------------------------------------------------
231 * SIUMCR - SIU Module Configuration 11-6
232 *-----------------------------------------------------------------------
233 * PCMCIA config., multi-function pin tri-state
235 #define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC00)
237 /*-----------------------------------------------------------------------
238 * TBSCR - Time Base Status and Control 11-26
239 *-----------------------------------------------------------------------
240 * Clear Reference Interrupt Status, Timebase freezing enabled
242 #define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
244 /*-----------------------------------------------------------------------
245 * RTCSC - Real-Time Clock Status and Control Register 11-27
246 *-----------------------------------------------------------------------
248 #define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
250 /*-----------------------------------------------------------------------
251 * PISCR - Periodic Interrupt Status and Control 11-31
252 *-----------------------------------------------------------------------
253 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
255 #define CFG_PISCR (PISCR_PS | PISCR_PITF)
257 /*-----------------------------------------------------------------------
258 * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
259 *-----------------------------------------------------------------------
260 * Reset PLL lock status sticky bit, timer expired status bit and timer
261 * interrupt status bit
263 * If this is a 80 MHz CPU, set PLL multiplication factor to 5 (5*16=80)!
265 #define CFG_PLPRCR ( (5-1)<<PLPRCR_MF_SHIFT | PLPRCR_TEXPS | PLPRCR_TMIST )
267 /*-----------------------------------------------------------------------
268 * SCCR - System Clock and reset Control Register 15-27
269 *-----------------------------------------------------------------------
270 * Set clock output, timebase and RTC source and divider,
271 * power management and some other internal clocks
273 #define SCCR_MASK SCCR_EBDF00
274 #define CFG_SCCR (SCCR_TBS | SCCR_EBDF01 | \
275 SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
276 SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
279 /*-----------------------------------------------------------------------
281 *-----------------------------------------------------------------------
285 /* KUP4K use both slots, SLOT_A as "primary". */
286 #define CONFIG_PCMCIA_SLOT_A 1
288 #define CFG_PCMCIA_MEM_ADDR (0xE0000000)
289 #define CFG_PCMCIA_MEM_SIZE ( 64 << 20 )
290 #define CFG_PCMCIA_DMA_ADDR (0xE4000000)
291 #define CFG_PCMCIA_DMA_SIZE ( 64 << 20 )
292 #define CFG_PCMCIA_ATTRB_ADDR (0xE8000000)
293 #define CFG_PCMCIA_ATTRB_SIZE ( 64 << 20 )
294 #define CFG_PCMCIA_IO_ADDR (0xEC000000)
295 #define CFG_PCMCIA_IO_SIZE ( 64 << 20 )
297 #define PCMCIA_SOCKETS_NO 2
298 #define PCMCIA_MEM_WIN_NO 8
299 /*-----------------------------------------------------------------------
300 * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
301 *-----------------------------------------------------------------------
304 #define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
306 #undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
307 #define CONFIG_IDE_LED 1 /* LED for ide supported */
308 #undef CONFIG_IDE_RESET /* reset for ide not supported */
310 #define CFG_IDE_MAXBUS 2
311 #define CFG_IDE_MAXDEVICE 4
313 #define CFG_ATA_IDE0_OFFSET 0x0000
315 #define CFG_ATA_IDE1_OFFSET (4 * CFG_PCMCIA_MEM_SIZE)
317 #define CFG_ATA_BASE_ADDR CFG_PCMCIA_MEM_ADDR
319 /* Offset for data I/O */
320 #define CFG_ATA_DATA_OFFSET (CFG_PCMCIA_MEM_SIZE + 0x320)
322 /* Offset for normal register accesses */
323 #define CFG_ATA_REG_OFFSET (2 * CFG_PCMCIA_MEM_SIZE + 0x320)
325 /* Offset for alternate registers */
326 #define CFG_ATA_ALT_OFFSET 0x0100
329 /*-----------------------------------------------------------------------
331 *-----------------------------------------------------------------------
337 * Init Memory Controller:
339 * BR0/1 and OR0/1 (FLASH)
341 #define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */
343 /* used to re-map FLASH both when starting from SRAM or FLASH:
344 * restrict access enough to keep SRAM working (if any)
345 * but not too much to meddle with FLASH accesses
347 #define CFG_REMAP_OR_AM 0x80000000 /* OR addr mask */
348 #define CFG_PRELIM_OR_AM 0xE0000000 /* OR addr mask */
353 #define CFG_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \
354 OR_SCY_2_CLK | OR_EHTR | OR_BI)
356 #define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH)
357 #define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
358 #define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V )
361 /* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
362 #define CFG_OR_TIMING_SDRAM 0x00000A00
366 * Memory Periodic Timer Prescaler
368 * The Divider for PTA (refresh timer) configuration is based on an
369 * example SDRAM configuration (64 MBit, one bank). The adjustment to
370 * the number of chip selects (NCS) and the actually needed refresh
371 * rate is done by setting MPTPR.
373 * PTA is calculated from
374 * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS)
376 * gclk CPU clock (not bus clock!)
377 * Trefresh Refresh cycle * 4 (four word bursts used)
379 * 4096 Rows from SDRAM example configuration
380 * 1000 factor s -> ms
381 * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration
382 * 4 Number of refresh cycles per period
383 * 64 Refresh cycle in ms per number of rows
384 * --------------------------------------------
385 * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000
387 * 50 MHz => 50.000.000 / Divider = 98
388 * 66 Mhz => 66.000.000 / Divider = 129
389 * 80 Mhz => 80.000.000 / Divider = 156
391 #if defined(CONFIG_80MHz)
392 #define CFG_MAMR_PTA 156
393 #elif defined(CONFIG_66MHz)
394 #define CFG_MAMR_PTA 129
396 #define CFG_MAMR_PTA 98
397 #endif /*CONFIG_??MHz */
400 * For 16 MBit, refresh rates could be 31.3 us
401 * (= 64 ms / 2K = 125 / quad bursts).
402 * For a simpler initialization, 15.6 us is used instead.
404 * #define CFG_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks
405 * #define CFG_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank
407 #define CFG_MPTPR 0x400
410 * MAMR settings for SDRAM
412 #define CFG_MAMR 0x80802114
415 * Internal Definitions
419 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
420 #define BOOTFLAG_WARM 0x02 /* Software reboot */
423 #define CONFIG_AUTOBOOT_KEYED /* use key strings to stop autoboot */
425 #define CONFIG_AUTOBOOT_PROMPT "Boote in %d Sekunden - stop mit \"2\"\n"
427 #define CONFIG_AUTOBOOT_STOP_STR "." /* easy to stop for now */
428 #define CONFIG_SILENT_CONSOLE 1
430 #endif /* __CONFIG_H */