2 * (C) Copyright 2004 Sandburst Corporation
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 /************************************************************************
24 * KAMINOREFDES.h - configuration for the Sandburst Kamino Reference
26 ***********************************************************************/
29 * $Id: KAREF.h,v 1.6 2005/06/03 15:05:25 tsawyer Exp $
36 /*-----------------------------------------------------------------------
37 * High Level Configuration Options
38 *----------------------------------------------------------------------*/
39 #define CONFIG_KAREF 1 /* Board is Kamino Ref Variant */
40 #define CONFIG_440GX 1 /* Specifc GX support */
41 #define CONFIG_440 1 /* ... PPC440 family */
42 #define CONFIG_4xx 1 /* ... PPC4xx family */
43 #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
44 #define CONFIG_MISC_INIT_F 1 /* Call board misc_init_f */
45 #define CONFIG_MISC_INIT_R 1 /* Call board misc_init_r */
47 #define CONFIG_SYS_TEXT_BASE 0xFFF80000
49 #undef CONFIG_SYS_DRAM_TEST /* Disable-takes long time!*/
50 #define CONFIG_SYS_CLK_FREQ 66666666 /* external freq to pll */
52 #define CONFIG_VERY_BIG_RAM 1
53 #define CONFIG_VERSION_VARIABLE
55 #define CONFIG_IDENT_STRING " Sandburst Kamino Reference Design"
57 /*-----------------------------------------------------------------------
58 * Base addresses -- Note these are effective addresses where the
59 * actual resources get mapped (not physical addresses)
60 *----------------------------------------------------------------------*/
61 #define CONFIG_SYS_SDRAM_BASE 0x00000000 /* _must_ be 0 */
62 #define CONFIG_SYS_FLASH_BASE 0xfff80000 /* start of FLASH */
63 #define CONFIG_SYS_MONITOR_BASE 0xfff80000 /* start of monitor */
64 #define CONFIG_SYS_PCI_MEMBASE 0x80000000 /* mapped pci memory */
65 #define CONFIG_SYS_ISRAM_BASE 0xc0000000 /* internal SRAM */
66 #define CONFIG_SYS_PCI_BASE 0xd0000000 /* internal PCI regs */
68 #define CONFIG_SYS_NVRAM_BASE_ADDR (CONFIG_SYS_PERIPHERAL_BASE + 0x08000000)
69 #define CONFIG_SYS_KAREF_FPGA_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x08200000)
70 #define CONFIG_SYS_OFEM_FPGA_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x08400000)
71 #define CONFIG_SYS_BME32_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x08500000)
72 #define CONFIG_SYS_GPIO_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x00000700)
74 /* Here for completeness */
75 #define CONFIG_SYS_OFEMAC_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x08600000)
77 /*-----------------------------------------------------------------------
78 * Initial RAM & stack pointer (placed in internal SRAM)
79 *----------------------------------------------------------------------*/
80 #define CONFIG_SYS_TEMP_STACK_OCM 1
81 #define CONFIG_SYS_OCM_DATA_ADDR CONFIG_SYS_ISRAM_BASE
82 #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_ISRAM_BASE /* Initial RAM address */
83 #define CONFIG_SYS_INIT_RAM_SIZE 0x2000 /* Size of used area in RAM */
84 #define CONFIG_SYS_GBL_DATA_SIZE 128 /* num bytes initial data */
86 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - CONFIG_SYS_GBL_DATA_SIZE)
87 #define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_GBL_DATA_OFFSET - 0x4)
89 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Rsrv 256kB for Mon */
90 #define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Rsrv 128kB for malloc */
92 /*-----------------------------------------------------------------------
94 *----------------------------------------------------------------------*/
95 #define CONFIG_CONS_INDEX 1 /* Use UART0 */
96 #define CONFIG_SYS_NS16550
97 #define CONFIG_SYS_NS16550_SERIAL
98 #define CONFIG_SYS_NS16550_REG_SIZE 1
99 #define CONFIG_SYS_NS16550_CLK get_serial_clock()
100 #define CONFIG_SERIAL_MULTI 1
101 #define CONFIG_BAUDRATE 9600
103 #define CONFIG_SYS_BAUDRATE_TABLE \
104 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
106 /*-----------------------------------------------------------------------
109 * NOTE: Upper 8 bytes of NVRAM is where the RTC registers are located.
110 * The DS1743 code assumes this condition (i.e. -- it assumes the base
111 * address for the RTC registers is:
113 * CONFIG_SYS_NVRAM_BASE_ADDR + CONFIG_SYS_NVRAM_SIZE
115 *----------------------------------------------------------------------*/
116 #define CONFIG_SYS_NVRAM_SIZE (0x2000 - 8) /* NVRAM size(8k)- RTC regs*/
117 #define CONFIG_RTC_DS174x 1 /* DS1743 RTC */
119 /*-----------------------------------------------------------------------
121 *----------------------------------------------------------------------*/
122 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
123 #define CONFIG_SYS_MAX_FLASH_SECT 8 /* sectors per device */
125 #undef CONFIG_SYS_FLASH_CHECKSUM
126 #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Flash Erase TO (in ms) */
127 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write TO(in ms) */
129 /*-----------------------------------------------------------------------
131 *----------------------------------------------------------------------*/
132 #define CONFIG_SPD_EEPROM 1 /* Use SPD EEPROM for setup*/
133 #define SPD_EEPROM_ADDRESS {0x53} /* SPD i2c spd addresses */
135 /*-----------------------------------------------------------------------
137 *----------------------------------------------------------------------*/
138 #define CONFIG_HARD_I2C 1 /* I2C hardware support */
139 #undef CONFIG_SOFT_I2C /* I2C !bit-banged */
140 #define CONFIG_PPC4XX_I2C /* use PPC4xx driver */
141 #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed 400kHz */
142 #define CONFIG_SYS_I2C_SLAVE 0x7F /* I2C slave address */
143 #define CONFIG_SYS_I2C_NOPROBES {0x69} /* Don't probe these addrs */
144 #define CONFIG_I2C_BUS1 1 /* Include i2c bus 1 supp */
147 /*-----------------------------------------------------------------------
149 *----------------------------------------------------------------------*/
150 #define CONFIG_ENV_IS_IN_NVRAM 1 /* Environment uses NVRAM */
151 #undef CONFIG_ENV_IS_IN_FLASH /* ... not in flash */
152 #undef CONFIG_ENV_IS_IN_EEPROM /* ... not in EEPROM */
153 #define CONFIG_ENV_OVERWRITE 1 /* allow env overwrite */
155 #define CONFIG_ENV_SIZE 0x1000 /* Size of Env vars */
156 #define CONFIG_ENV_ADDR (CONFIG_SYS_NVRAM_BASE_ADDR)
158 #define CONFIG_BOOTDELAY 5 /* 5 second autoboot */
160 #define CONFIG_LOADS_ECHO 1 /* echo on for serial dnld */
161 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
163 /*-----------------------------------------------------------------------
165 *----------------------------------------------------------------------*/
166 #define CONFIG_PPC4xx_EMAC
167 #define CONFIG_MII 1 /* MII PHY management */
168 #define CONFIG_NET_MULTI 1
169 #define CONFIG_PHY_ADDR 0xff /* no phy on EMAC0 */
170 #define CONFIG_PHY1_ADDR 0xff /* no phy on EMAC1 */
171 #define CONFIG_PHY2_ADDR 0x08 /* PHY addr, MGMT, EMAC2 */
172 #define CONFIG_PHY3_ADDR 0x18 /* PHY addr, LCL, EMAC3 */
173 #define CONFIG_HAS_ETH0
174 #define CONFIG_HAS_ETH1
175 #define CONFIG_HAS_ETH2
176 #define CONFIG_HAS_ETH3
177 #define CONFIG_PHY_RESET 1 /* reset phy upon startup */
178 #define CONFIG_CIS8201_PHY 1 /* RGMII mode for Cicada */
179 #define CONFIG_CIS8201_SHORT_ETCH 1 /* Use short etch mode */
180 #define CONFIG_PHY_GIGE 1 /* GbE speed/duplex detect */
181 #define CONFIG_PHY_RESET_DELAY 1000
182 #define CONFIG_NETMASK 255.255.0.0
183 #define CONFIG_ETHADDR 00:00:00:00:00:00 /* No EMAC 0 support */
184 #define CONFIG_ETH1ADDR 00:00:00:00:00:00 /* No EMAC 1 support */
185 #define CONFIG_SYS_RX_ETH_BUFFER 32 /* #eth rx buff & descrs */
191 #define CONFIG_BOOTP_BOOTFILESIZE
192 #define CONFIG_BOOTP_BOOTPATH
193 #define CONFIG_BOOTP_GATEWAY
194 #define CONFIG_BOOTP_HOSTNAME
198 * Command line configuration.
200 #include <config_cmd_default.h>
202 #define CONFIG_CMD_PCI
203 #define CONFIG_CMD_IRQ
204 #define CONFIG_CMD_I2C
205 #define CONFIG_CMD_DHCP
206 #define CONFIG_CMD_DATE
207 #define CONFIG_CMD_BEDBUG
208 #define CONFIG_CMD_PING
209 #define CONFIG_CMD_DIAG
210 #define CONFIG_CMD_MII
211 #define CONFIG_CMD_NET
212 #define CONFIG_CMD_ELF
213 #define CONFIG_CMD_IDE
214 #define CONFIG_CMD_FAT
217 /* Include NetConsole support */
218 #define CONFIG_NETCONSOLE
220 /* Include auto complete with tabs */
221 #define CONFIG_AUTO_COMPLETE 1
222 #define CONFIG_SYS_ALT_MEMTEST 1 /* use real memory test */
224 #define CONFIG_SYS_LONGHELP /* undef to save memory */
225 #define CONFIG_SYS_PROMPT "KaRefDes=> " /* Monitor Command Prompt */
227 #define CONFIG_SYS_HUSH_PARSER 1 /* HUSH for ext'd cli */
228 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
231 /*-----------------------------------------------------------------------
233 *----------------------------------------------------------------------*/
234 #if defined(CONFIG_CMD_KGDB)
235 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
237 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
239 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
240 /* Print Buffer Size */
241 #define CONFIG_SYS_MAXARGS 16 /* max number of cmd args */
242 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Arg Buffer Size */
244 /*-----------------------------------------------------------------------
246 *----------------------------------------------------------------------*/
247 #define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
248 #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
250 /*-----------------------------------------------------------------------
251 * Compact Flash (in true IDE mode)
252 *----------------------------------------------------------------------*/
253 #undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */
254 #undef CONFIG_IDE_LED /* no led for ide supported */
256 #define CONFIG_IDE_RESET /* reset for ide supported */
257 #define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE busses */
258 #define CONFIG_SYS_IDE_MAXDEVICE (CONFIG_SYS_IDE_MAXBUS*1) /* max. 1 drives per IDE bus */
260 #define CONFIG_SYS_ATA_BASE_ADDR 0xF0000000
261 #define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
262 #define CONFIG_SYS_ATA_DATA_OFFSET 0x0000 /* Offset for data I/O */
263 #define CONFIG_SYS_ATA_REG_OFFSET 0x0000 /* Offset for normal register accesses*/
264 #define CONFIG_SYS_ATA_ALT_OFFSET 0x100000 /* Offset for alternate registers */
266 #define CONFIG_SYS_ATA_STRIDE 2 /* Directly connected CF, needs a stride
267 to get to the correct offset */
268 #define CONFIG_DOS_PARTITION 1 /* Include dos partition */
270 /*-----------------------------------------------------------------------
272 *----------------------------------------------------------------------*/
274 #define CONFIG_PCI /* include pci support */
275 #define CONFIG_PCI_PNP /* do pci plug-and-play */
276 #define CONFIG_PCI_SCAN_SHOW /* show pci devices */
277 #define CONFIG_SYS_PCI_TARGBASE (CONFIG_SYS_PCI_MEMBASE)
279 /* Board-specific PCI */
280 #define CONFIG_SYS_PCI_TARGET_INIT /* let board init pci target*/
282 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x17BA /* Sandburst */
283 #define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0xcafe /* Whatever */
286 * For booting Linux, the board info and command line data
287 * have to be in the first 8 MB of memory, since this is
288 * the maximum mapped by the Linux kernel during initialization.
290 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
292 #if defined(CONFIG_CMD_KGDB)
293 #define CONFIG_KGDB_BAUDRATE 230400 /* kgdb serial port baud */
294 #define CONFIG_KGDB_SER_INDEX 2 /* kgdb serial port */
297 /*-----------------------------------------------------------------------
298 * Miscellaneous configurable options
299 *----------------------------------------------------------------------*/
300 #undef CONFIG_WATCHDOG /* watchdog disabled */
301 #define CONFIG_SYS_LOAD_ADDR 0x8000000 /* default load address */
302 #define CONFIG_SYS_EXTBDINFO 1 /* use extended board_info */
304 #define CONFIG_SYS_HZ 100 /* decr freq: 1 ms ticks */
307 #endif /* __CONFIG_H */