3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
28 * High Level Configuration Options
32 #define CONFIG_MPC5XXX 1 /* This is an MPC5xxx CPU */
33 #define CONFIG_ICECUBE 1 /* ... on IceCube board */
35 #define CFG_MPC5XXX_CLKIN 33333333 /* ... running at 33MHz */
37 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
38 #define BOOTFLAG_WARM 0x02 /* Software reboot */
40 #define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
41 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
42 # define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
46 * Serial console configuration
48 #define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */
49 #define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
50 #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
53 #ifdef CONFIG_MPC5200 /* MPC5100 PCI is not supported yet. */
56 * 0x40000000 - 0x4fffffff - PCI Memory
57 * 0x50000000 - 0x50ffffff - PCI IO Space
60 #define CONFIG_PCI_PNP 1
61 #define CONFIG_PCI_SCAN_SHOW 1
63 #define CONFIG_PCI_MEM_BUS 0x40000000
64 #define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
65 #define CONFIG_PCI_MEM_SIZE 0x10000000
67 #define CONFIG_PCI_IO_BUS 0x50000000
68 #define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
69 #define CONFIG_PCI_IO_SIZE 0x01000000
71 #define CONFIG_NET_MULTI 1
72 #define CONFIG_EEPRO100 1
73 #define CFG_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
74 #define CONFIG_NS8382X 1
76 #define ADD_PCI_CMD CFG_CMD_PCI
80 #define ADD_PCI_CMD 0 /* no CFG_CMD_PCI */
87 #define CONFIG_COMMANDS (CONFIG_CMD_DFL | ADD_PCI_CMD | \
88 CFG_CMD_I2C | CFG_CMD_EEPROM)
90 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
91 #include <cmd_confdefs.h>
93 #if (TEXT_BASE == 0xFF000000) /* Boot low with 16 MB Flash */
94 # define CFG_LOWBOOT 1
95 # define CFG_LOWBOOT16 1
97 #if (TEXT_BASE == 0xFF800000) /* Boot low with 8 MB Flash */
98 # define CFG_LOWBOOT 1
99 # define CFG_LOWBOOT08 1
105 #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
107 #define CONFIG_PREBOOT "echo;" \
108 "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
111 #undef CONFIG_BOOTARGS
113 #define CONFIG_EXTRA_ENV_SETTINGS \
115 "nfsargs=setenv bootargs root=/dev/nfs rw " \
116 "nfsroot=$(serverip):$(rootpath)\0" \
117 "ramargs=setenv bootargs root=/dev/ram rw\0" \
118 "addip=setenv bootargs $(bootargs) " \
119 "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \
120 ":$(hostname):$(netdev):off panic=1\0" \
121 "flash_nfs=run nfsargs addip;" \
122 "bootm $(kernel_addr)\0" \
123 "flash_self=run ramargs addip;" \
124 "bootm $(kernel_addr) $(ramdisk_addr)\0" \
125 "net_nfs=tftp 200000 $(bootfile);run nfsargs addip;bootm\0" \
126 "rootpath=/opt/eldk/ppc_82xx\0" \
127 "bootfile=/tftpboot/MPC5200/uImage\0" \
130 #define CONFIG_BOOTCOMMAND "run flash_self"
132 #if defined(CONFIG_MPC5200)
134 * IPB Bus clocking configuration.
136 #undef CFG_IPBSPEED_133 /* define for 133MHz speed */
141 #define CONFIG_HARD_I2C 1 /* I2C with hardware support */
142 #define CFG_I2C_MODULE 2 /* Select I2C module #1 or #2 */
144 #define CFG_I2C_SPEED 100000 /* 100 kHz */
145 #define CFG_I2C_SLAVE 0x7F
148 * EEPROM configuration
150 #define CFG_I2C_EEPROM_ADDR 0x50 /* 1010000x */
151 #define CFG_I2C_EEPROM_ADDR_LEN 1
152 #define CFG_EEPROM_PAGE_WRITE_BITS 3
153 #define CFG_EEPROM_PAGE_WRITE_DELAY_MS 70
156 * Flash configuration
158 #define CFG_FLASH_BASE 0xff000000
159 #define CFG_FLASH_SIZE 0x01000000
160 #if !defined(CFG_LOWBOOT)
161 #define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x740000 + 0x800000)
162 #else /* CFG_LOWBOOT */
163 #if defined(CFG_LOWBOOT08)
164 #define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x30000 + 0x800000)
166 #if defined(CFG_LOWBOOT16)
167 #define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x30000)
169 #endif /* CFG_LOWBOOT */
170 #define CFG_MAX_FLASH_BANKS 2 /* max num of memory banks */
172 #define CFG_MAX_FLASH_SECT 128 /* max num of sects on one chip */
174 #define CFG_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */
175 #define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
177 #undef CONFIG_FLASH_16BIT /* Flash is 8-bit */
181 * Environment settings
183 #define CFG_ENV_IS_IN_FLASH 1
184 #define CFG_ENV_SIZE 0x10000
185 #define CFG_ENV_SECT_SIZE 0x10000
186 #define CONFIG_ENV_OVERWRITE 1
191 #define CFG_MBAR 0xf0000000
192 #define CFG_SDRAM_BASE 0x00000000
193 #define CFG_DEFAULT_MBAR 0x80000000
195 /* Use SRAM until RAM will be available */
196 #define CFG_INIT_RAM_ADDR MPC5XXX_SRAM
197 #define CFG_INIT_RAM_END MPC5XXX_SRAM_SIZE /* End of used area in DPRAM */
200 #define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
201 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
202 #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
204 #define CFG_MONITOR_BASE TEXT_BASE
205 #if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
206 # define CFG_RAMBOOT 1
209 #define CFG_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
210 #define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
211 #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
214 * Ethernet configuration
216 #define CONFIG_MPC5XXX_FEC 1
217 #define CONFIG_FEC_10MBIT 1 /* Workaround for FEC 100Mbit problem */
222 #define CFG_GPS_PORT_CONFIG 0x10000004
225 * Miscellaneous configurable options
227 #define CFG_LONGHELP /* undef to save memory */
228 #define CFG_PROMPT "=> " /* Monitor Command Prompt */
229 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
230 #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
232 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
234 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
235 #define CFG_MAXARGS 16 /* max number of command args */
236 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
238 #define CFG_MEMTEST_START 0x00100000 /* memtest works on */
239 #define CFG_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
241 #define CFG_LOAD_ADDR 0x100000 /* default load address */
243 #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
246 * Various low-level settings
248 #if defined(CONFIG_MPC5200)
249 #define CFG_HID0_INIT HID0_ICE | HID0_ICFI
250 #define CFG_HID0_FINAL HID0_ICE
252 #define CFG_HID0_INIT 0
253 #define CFG_HID0_FINAL 0
256 #define CFG_BOOTCS_START CFG_FLASH_BASE
257 #define CFG_BOOTCS_SIZE CFG_FLASH_SIZE
258 #define CFG_BOOTCS_CFG 0x00047801
259 #define CFG_CS0_START CFG_FLASH_BASE
260 #define CFG_CS0_SIZE CFG_FLASH_SIZE
262 #define CFG_CS_BURST 0x00000000
263 #define CFG_CS_DEADCYCLE 0x33333333
265 #define CFG_RESET_ADDRESS 0xff000000
267 #endif /* __CONFIG_H */