2 * (C) Copyright 2003-2005
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
28 * High Level Configuration Options
32 #define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */
33 #define CONFIG_ICECUBE 1 /* ... on IceCube board */
35 #define CFG_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */
37 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
38 #define BOOTFLAG_WARM 0x02 /* Software reboot */
40 #define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
41 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
42 # define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
46 * Serial console configuration
48 #define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */
49 #define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
50 #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
53 #ifdef CONFIG_MPC5200 /* MPC5100 PCI is not supported yet. */
56 * 0x40000000 - 0x4fffffff - PCI Memory
57 * 0x50000000 - 0x50ffffff - PCI IO Space
61 #if defined(CONFIG_PCI)
62 #define CONFIG_PCI_PNP 1
63 #define CONFIG_PCI_SCAN_SHOW 1
65 #define CONFIG_PCI_MEM_BUS 0x40000000
66 #define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
67 #define CONFIG_PCI_MEM_SIZE 0x10000000
69 #define CONFIG_PCI_IO_BUS 0x50000000
70 #define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
71 #define CONFIG_PCI_IO_SIZE 0x01000000
72 #define ADD_PCI_CMD CFG_CMD_PCI
75 #define CFG_XLB_PIPELINING 1
77 #define CONFIG_NET_MULTI 1
79 #define CONFIG_EEPRO100 1
80 #define CFG_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
81 #define CONFIG_NS8382X 1
86 #define ADD_PCI_CMD 0 /* no CFG_CMD_PCI */
91 #define CONFIG_MAC_PARTITION
92 #define CONFIG_DOS_PARTITION
93 #define CONFIG_ISO_PARTITION
97 #define CONFIG_USB_OHCI
98 #define ADD_USB_CMD CFG_CMD_USB | CFG_CMD_FAT
99 #define CONFIG_USB_STORAGE
101 #define ADD_USB_CMD 0
104 #define CONFIG_TIMESTAMP /* Print image info with timestamp */
109 #define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
119 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
120 #include <cmd_confdefs.h>
122 #if (TEXT_BASE == 0xFF000000) /* Boot low with 16 MB Flash */
123 # define CFG_LOWBOOT 1
124 # define CFG_LOWBOOT16 1
126 #if (TEXT_BASE == 0xFF800000) /* Boot low with 8 MB Flash */
127 #if defined(CONFIG_LITE5200B)
128 # error CFG_LOWBOOT08 is incompatible with the Lite5200B
130 # define CFG_LOWBOOT 1
131 # define CFG_LOWBOOT08 1
138 #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
140 #define CONFIG_PREBOOT "echo;" \
141 "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
144 #undef CONFIG_BOOTARGS
146 #define CONFIG_EXTRA_ENV_SETTINGS \
148 "nfsargs=setenv bootargs root=/dev/nfs rw " \
149 "nfsroot=${serverip}:${rootpath}\0" \
150 "ramargs=setenv bootargs root=/dev/ram rw\0" \
151 "addip=setenv bootargs ${bootargs} " \
152 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
153 ":${hostname}:${netdev}:off panic=1\0" \
154 "flash_nfs=run nfsargs addip;" \
155 "bootm ${kernel_addr}\0" \
156 "flash_self=run ramargs addip;" \
157 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
158 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
159 "rootpath=/opt/eldk/ppc_82xx\0" \
160 "bootfile=/tftpboot/MPC5200/uImage\0" \
163 #define CONFIG_BOOTCOMMAND "run flash_self"
165 #if defined(CONFIG_MPC5200)
167 * IPB Bus clocking configuration.
169 #if defined(CONFIG_LITE5200B)
170 #define CFG_IPBSPEED_133 /* define for 133MHz speed */
172 #undef CFG_IPBSPEED_133 /* define for 133MHz speed */
174 #endif /* CONFIG_MPC5200 */
178 #define CONFIG_HARD_I2C 1 /* I2C with hardware support */
179 #define CFG_I2C_MODULE 2 /* Select I2C module #1 or #2 */
181 #define CFG_I2C_SPEED 100000 /* 100 kHz */
182 #define CFG_I2C_SLAVE 0x7F
185 * EEPROM configuration
187 #define CFG_I2C_EEPROM_ADDR 0x50 /* 1010000x */
188 #define CFG_I2C_EEPROM_ADDR_LEN 1
189 #define CFG_EEPROM_PAGE_WRITE_BITS 3
190 #define CFG_EEPROM_PAGE_WRITE_DELAY_MS 70
193 * Flash configuration
195 #if defined(CONFIG_LITE5200B)
196 #define CFG_FLASH_BASE 0xFE000000
197 #define CFG_FLASH_SIZE 0x01000000
198 #if !defined(CFG_LOWBOOT)
199 #define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x01760000 + 0x00800000)
200 #else /* CFG_LOWBOOT */
201 #if defined(CFG_LOWBOOT08)
202 # error CFG_LOWBOOT08 is incompatible with the Lite5200B
204 #if defined(CFG_LOWBOOT16)
205 #define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x01060000)
207 #endif /* CFG_LOWBOOT */
208 #else /* !CONFIG_LITE5200B (IceCube)*/
209 #define CFG_FLASH_BASE 0xFF000000
210 #define CFG_FLASH_SIZE 0x01000000
211 #if !defined(CFG_LOWBOOT)
212 #define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x00740000 + 0x00800000)
213 #else /* CFG_LOWBOOT */
214 #if defined(CFG_LOWBOOT08)
215 #define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x00040000 + 0x00800000)
217 #if defined(CFG_LOWBOOT16)
218 #define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x00040000)
220 #endif /* CFG_LOWBOOT */
221 #endif /* CONFIG_LITE5200B */
222 #define CFG_MAX_FLASH_BANKS 2 /* max num of memory banks */
224 #define CFG_MAX_FLASH_SECT 128 /* max num of sects on one chip */
226 #define CFG_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */
227 #define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
229 #undef CONFIG_FLASH_16BIT /* Flash is 8-bit */
231 #if defined(CONFIG_LITE5200B)
232 #define CFG_FLASH_CFI_DRIVER
233 #define CFG_FLASH_CFI
234 #define CFG_FLASH_BANKS_LIST {CFG_CS1_START,CFG_CS0_START}
239 * Environment settings
241 #define CFG_ENV_IS_IN_FLASH 1
242 #define CFG_ENV_SIZE 0x10000
243 #if defined(CONFIG_LITE5200B)
244 #define CFG_ENV_SECT_SIZE 0x20000
246 #define CFG_ENV_SECT_SIZE 0x10000
248 #define CONFIG_ENV_OVERWRITE 1
253 #define CFG_MBAR 0xF0000000
254 #define CFG_SDRAM_BASE 0x00000000
255 #define CFG_DEFAULT_MBAR 0x80000000
257 /* Use SRAM until RAM will be available */
258 #define CFG_INIT_RAM_ADDR MPC5XXX_SRAM
259 #define CFG_INIT_RAM_END MPC5XXX_SRAM_SIZE /* End of used area in DPRAM */
262 #define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
263 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
264 #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
266 #define CFG_MONITOR_BASE TEXT_BASE
267 #if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
268 # define CFG_RAMBOOT 1
271 #define CFG_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
272 #define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
273 #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
276 * Ethernet configuration
278 #define CONFIG_MPC5xxx_FEC 1
280 * Define CONFIG_FEC_10MBIT to force FEC at 10Mb
282 /* #define CONFIG_FEC_10MBIT 1 */
283 #define CONFIG_PHY_ADDR 0x00
284 #if defined(CONFIG_LITE5200B)
285 #define CONFIG_FEC_MII100 1
291 #ifdef CONFIG_MPC5200_DDR
292 #define CFG_GPS_PORT_CONFIG 0x90000004
294 #define CFG_GPS_PORT_CONFIG 0x10000004
298 * Miscellaneous configurable options
300 #define CFG_LONGHELP /* undef to save memory */
301 #define CFG_PROMPT "=> " /* Monitor Command Prompt */
302 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
303 #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
305 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
307 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
308 #define CFG_MAXARGS 16 /* max number of command args */
309 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
311 #define CFG_MEMTEST_START 0x00100000 /* memtest works on */
312 #define CFG_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
314 #define CFG_LOAD_ADDR 0x100000 /* default load address */
316 #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
319 * Various low-level settings
321 #if defined(CONFIG_MPC5200)
322 #define CFG_HID0_INIT HID0_ICE | HID0_ICFI
323 #define CFG_HID0_FINAL HID0_ICE
325 #define CFG_HID0_INIT 0
326 #define CFG_HID0_FINAL 0
329 #if defined(CONFIG_LITE5200B)
330 #define CFG_CS1_START CFG_FLASH_BASE
331 #define CFG_CS1_SIZE CFG_FLASH_SIZE
332 #define CFG_CS1_CFG 0x00047800
333 #define CFG_CS0_START (CFG_FLASH_BASE + CFG_FLASH_SIZE)
334 #define CFG_CS0_SIZE CFG_FLASH_SIZE
335 #define CFG_BOOTCS_START CFG_CS0_START
336 #define CFG_BOOTCS_SIZE CFG_FLASH_SIZE
337 #define CFG_BOOTCS_CFG 0x00047800
338 #else /* IceCube aka Lite5200 */
339 #ifdef CONFIG_MPC5200_DDR
341 #define CFG_BOOTCS_START (CFG_CS1_START + CFG_CS1_SIZE)
342 #define CFG_BOOTCS_SIZE 0x00800000
343 #define CFG_BOOTCS_CFG 0x00047801
344 #define CFG_CS1_START CFG_FLASH_BASE
345 #define CFG_CS1_SIZE 0x00800000
346 #define CFG_CS1_CFG 0x00047800
348 #else /* !CONFIG_MPC5200_DDR */
350 #define CFG_BOOTCS_START CFG_FLASH_BASE
351 #define CFG_BOOTCS_SIZE CFG_FLASH_SIZE
352 #define CFG_BOOTCS_CFG 0x00047801
353 #define CFG_CS0_START CFG_FLASH_BASE
354 #define CFG_CS0_SIZE CFG_FLASH_SIZE
356 #endif /* CONFIG_MPC5200_DDR */
357 #endif /*CONFIG_LITE5200B */
359 #define CFG_CS_BURST 0x00000000
360 #define CFG_CS_DEADCYCLE 0x33333333
362 #define CFG_RESET_ADDRESS 0xff000000
364 /*-----------------------------------------------------------------------
366 *-----------------------------------------------------------------------
368 #define CONFIG_USB_CLOCK 0x0001BBBB
369 #define CONFIG_USB_CONFIG 0x00001000
371 /*-----------------------------------------------------------------------
372 * IDE/ATA stuff Supports IDE harddisk
373 *-----------------------------------------------------------------------
376 #undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */
378 #undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
379 #undef CONFIG_IDE_LED /* LED for ide not supported */
381 #define CONFIG_IDE_RESET /* reset for ide supported */
382 #define CONFIG_IDE_PREINIT
384 #define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */
385 #define CFG_IDE_MAXDEVICE 2 /* max. 1 drive per IDE bus */
387 #define CFG_ATA_IDE0_OFFSET 0x0000
389 #define CFG_ATA_BASE_ADDR MPC5XXX_ATA
391 /* Offset for data I/O */
392 #define CFG_ATA_DATA_OFFSET (0x0060)
394 /* Offset for normal register accesses */
395 #define CFG_ATA_REG_OFFSET (CFG_ATA_DATA_OFFSET)
397 /* Offset for alternate registers */
398 #define CFG_ATA_ALT_OFFSET (0x005C)
400 /* Interval between registers */
401 #define CFG_ATA_STRIDE 4
403 #define CONFIG_ATAPI 1
405 #endif /* __CONFIG_H */