2 * (C) Copyright 2000-2005
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 * board/config.h - configuration options, board specific
32 * High Level Configuration Options
36 #define CONFIG_MPC860 1 /* This is a MPC860 CPU */
37 #define CONFIG_IP860 1 /* ...on a IP860 board */
39 #define CONFIG_SYS_TEXT_BASE 0x10000000
41 #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
42 #define CONFIG_RESET_PHY_R 1 /* Call reset_phy() */
44 #define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
45 #define CONFIG_BAUDRATE 9600
46 #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
48 #define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo" \
49 "\0load=tftp \"/tftpboot/u-boot.bin\"\0update=protect off 1:0;era 1:0;cp.b 100000 10000000 ${filesize}\0"
51 #undef CONFIG_BOOTARGS
52 #define CONFIG_BOOTCOMMAND \
54 "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
55 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \
58 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
59 #undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */
61 #undef CONFIG_WATCHDOG /* watchdog disabled */
64 /* enable I2C and select the hardware/software driver */
65 #undef CONFIG_HARD_I2C /* I2C with hardware support */
66 #define CONFIG_SOFT_I2C 1 /* I2C bit-banged */
68 * Software (bit-bang) I2C driver configuration
70 #define PB_SCL 0x00000020 /* PB 26 */
71 #define PB_SDA 0x00000010 /* PB 27 */
73 #define I2C_INIT (immr->im_cpm.cp_pbdir |= PB_SCL)
74 #define I2C_ACTIVE (immr->im_cpm.cp_pbdir |= PB_SDA)
75 #define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA)
76 #define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0)
77 #define I2C_SDA(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SDA; \
78 else immr->im_cpm.cp_pbdat &= ~PB_SDA
79 #define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \
80 else immr->im_cpm.cp_pbdat &= ~PB_SCL
81 #define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
84 # define CONFIG_SYS_I2C_SPEED 50000
85 # define CONFIG_SYS_I2C_SLAVE 0xFE
86 # define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM X24C16 */
87 # define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* bytes of address */
88 /* mask of address bits that overflow into the "EEPROM chip address" */
89 #define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07
90 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4
91 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* takes up to 10 msec */
93 #define CONFIG_TIMESTAMP /* Print image info with timestamp */
97 * Command line configuration.
99 #include <config_cmd_default.h>
101 #define CONFIG_CMD_BEDBUG
102 #define CONFIG_CMD_I2C
103 #define CONFIG_CMD_EEPROM
104 #define CONFIG_CMD_NFS
105 #define CONFIG_CMD_SNTP
110 #define CONFIG_BOOTP_SUBNETMASK
111 #define CONFIG_BOOTP_GATEWAY
112 #define CONFIG_BOOTP_HOSTNAME
113 #define CONFIG_BOOTP_BOOTPATH
116 * Miscellaneous configurable options
118 #define CONFIG_SYS_LONGHELP /* undef to save memory */
119 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
120 #if defined(CONFIG_CMD_KGDB)
121 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
123 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
125 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
126 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
127 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
129 #define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
130 #define CONFIG_SYS_MEMTEST_END 0x00F00000 /* 1 ... 15MB in DRAM */
132 #define CONFIG_SYS_LOAD_ADDR 0x00100000 /* default load address */
134 #define CONFIG_SYS_PIO_MODE 0 /* IDE interface in PIO Mode 0 */
136 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
138 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
141 * Low Level Configuration Settings
142 * (address mappings, register initial values, etc.)
143 * You should know what you are doing if you make changes here.
145 /*-----------------------------------------------------------------------
146 * Internal Memory Mapped Register
148 #define CONFIG_SYS_IMMR 0xF1000000 /* Non-standard value!! */
150 /*-----------------------------------------------------------------------
151 * Definitions for initial stack pointer and data area (in DPRAM)
153 #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
154 #define CONFIG_SYS_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
155 #define CONFIG_SYS_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
156 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
157 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
159 /*-----------------------------------------------------------------------
160 * Start addresses for the final memory configuration
161 * (Set up by the startup code)
162 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
164 #define CONFIG_SYS_SDRAM_BASE 0x00000000
165 #define CONFIG_SYS_FLASH_BASE 0x10000000
167 #define CONFIG_SYS_MONITOR_LEN (512 << 10) /* Reserve 512 kB for Monitor */
169 #if 0 /* need more space for I2C tests */
170 #define CONFIG_SYS_MONITOR_LEN (128 << 10) /* Reserve 128 kB for Monitor */
172 #define CONFIG_SYS_MONITOR_LEN (256 << 10)
175 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
176 #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
179 * For booting Linux, the board info and command line data
180 * have to be in the first 8 MB of memory, since this is
181 * the maximum mapped by the Linux kernel during initialization.
183 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
184 /*-----------------------------------------------------------------------
187 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
188 #define CONFIG_SYS_MAX_FLASH_SECT 124 /* max number of sectors on one chip */
190 #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
191 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
193 #undef CONFIG_ENV_IS_IN_FLASH
194 #undef CONFIG_ENV_IS_IN_NVRAM
195 #undef CONFIG_ENV_IS_IN_NVRAM
197 #define CONFIG_ENV_IS_IN_EEPROM
199 #ifdef CONFIG_ENV_IS_IN_NVRAM
200 #define CONFIG_ENV_ADDR 0x20000000 /* use SRAM */
201 #define CONFIG_ENV_SIZE (16<<10) /* use 16 kB */
202 #endif /* CONFIG_ENV_IS_IN_NVRAM */
204 #ifdef CONFIG_ENV_IS_IN_EEPROM
205 #define CONFIG_ENV_OFFSET 512 /* Leave 512 bytes free for other data */
206 #define CONFIG_ENV_SIZE 1536 /* Use remaining space */
207 #endif /* CONFIG_ENV_IS_IN_EEPROM */
209 /*-----------------------------------------------------------------------
210 * Cache Configuration
212 #define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
213 #if defined(CONFIG_CMD_KGDB)
214 #define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */
216 #define CONFIG_SYS_DELAYED_ICACHE 1 /* enable ICache not before
220 /*-----------------------------------------------------------------------
221 * SYPCR - System Protection Control 11-9
222 * SYPCR can only be written once after reset!
223 *-----------------------------------------------------------------------
224 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
227 #if defined(CONFIG_WATCHDOG)
228 #define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
229 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
231 #define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
234 /*-----------------------------------------------------------------------
235 * SIUMCR - SIU Module Configuration 11-6
236 *-----------------------------------------------------------------------
237 * +0x0000 => 0x80600800
239 #define CONFIG_SYS_SIUMCR (SIUMCR_EARB | SIUMCR_EARP0 | \
240 SIUMCR_DBGC11 | SIUMCR_MLRC10)
242 /*-----------------------------------------------------------------------
243 * Clock Setting - get clock frequency from Board Revision Register
244 *-----------------------------------------------------------------------
247 extern unsigned long ip860_get_clk_freq (void);
249 #define CONFIG_8xx_GCLK_FREQ ip860_get_clk_freq()
251 /*-----------------------------------------------------------------------
252 * TBSCR - Time Base Status and Control 11-26
253 *-----------------------------------------------------------------------
254 * Clear Reference Interrupt Status, Timebase freezing enabled
257 #define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
259 /*-----------------------------------------------------------------------
260 * PISCR - Periodic Interrupt Status and Control 11-31
261 *-----------------------------------------------------------------------
262 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
265 #define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF)
267 /*-----------------------------------------------------------------------
268 * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
269 *-----------------------------------------------------------------------
270 * Reset PLL lock status sticky bit, timer expired status bit and timer
271 * interrupt status bit, set PLL multiplication factor !
273 /* +0x0286 => was: 0x0000D000 */
274 #define CONFIG_SYS_PLPRCR \
275 ( PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST | \
276 /*PLPRCR_CSRC|*/ PLPRCR_LPM_NORMAL | \
277 PLPRCR_CSR | PLPRCR_LOLRE /*|PLPRCR_FIOPD*/ \
280 /*-----------------------------------------------------------------------
281 * SCCR - System Clock and reset Control Register 15-27
282 *-----------------------------------------------------------------------
283 * Set clock output, timebase and RTC source and divider,
284 * power management and some other internal clocks
286 #define SCCR_MASK SCCR_EBDF11
287 #define CONFIG_SYS_SCCR (SCCR_COM00 | SCCR_TBS | \
288 SCCR_RTDIV | SCCR_RTSEL | \
289 /*SCCR_CRQEN|*/ /*SCCR_PRQEN|*/ \
290 SCCR_EBDF00 | SCCR_DFSYNC00 | \
291 SCCR_DFBRG00 | SCCR_DFNL000 | \
294 /*-----------------------------------------------------------------------
295 * RTCSC - Real-Time Clock Status and Control Register 11-27
296 *-----------------------------------------------------------------------
298 /* +0x0220 => 0x00C3 */
299 #define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
302 /*-----------------------------------------------------------------------
303 * RCCR - RISC Controller Configuration Register 19-4
304 *-----------------------------------------------------------------------
306 /* +0x09C4 => TIMEP=1 */
307 #define CONFIG_SYS_RCCR 0x0100
309 /*-----------------------------------------------------------------------
310 * RMDS - RISC Microcode Development Support Control Register
311 *-----------------------------------------------------------------------
313 #define CONFIG_SYS_RMDS 0
315 /*-----------------------------------------------------------------------
316 * DER - Debug Event Register
317 *-----------------------------------------------------------------------
320 #define CONFIG_SYS_DER 0
323 * Init Memory Controller:
327 * MAMR settings for SDRAM - 16-14
331 /* periodic timer for refresh */
332 #define CONFIG_SYS_MAMR_PTA 0xC3
334 #define CONFIG_SYS_MAMR ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
335 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
336 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
338 * BR1 and OR1 (FLASH)
340 #define FLASH_BASE 0x10000000 /* FLASH bank #0 */
342 /* used to re-map FLASH
343 * restrict access enough to keep SRAM working (if any)
344 * but not too much to meddle with FLASH accesses
346 /* allow for max 8 MB of Flash */
347 #define CONFIG_SYS_REMAP_OR_AM 0xFF800000 /* OR addr mask */
348 #define CONFIG_SYS_PRELIM_OR_AM 0xFF800000 /* OR addr mask */
350 #define CONFIG_SYS_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_DIV2 | OR_BI | OR_SCY_6_CLK)
352 #define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
353 #define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
354 /* 16 bit, bank valid */
355 #define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE & BR_BA_MSK) | BR_PS_32 | BR_V )
357 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM
358 #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_BR0_PRELIM
363 #define SDRAM_BASE 0x00000000 /* SDRAM bank */
364 #define SDRAM_PRELIM_OR_AM 0xF8000000 /* map max. 128 MB */
365 #define SDRAM_TIMING 0x00000A00 /* SDRAM-Timing */
367 #define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB SDRAM */
369 #define CONFIG_SYS_OR2 (SDRAM_PRELIM_OR_AM | SDRAM_TIMING )
370 #define CONFIG_SYS_BR2 ((SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V )
373 * BR3/OR3 - SRAM (16 bit)
375 #define SRAM_BASE 0x20000000
376 #define CONFIG_SYS_OR3 0xFFF00130 /* BI/SCY = 5/TRLX (internal) */
377 #define CONFIG_SYS_BR3 ((SRAM_BASE & BR_BA_MSK) | BR_PS_16 | BR_V)
378 #define SRAM_SIZE (1 + (~(CONFIG_SYS_OR3 & BR_BA_MSK)))
379 #define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR3 /* Make sure to map early */
380 #define CONFIG_SYS_BR3_PRELIM CONFIG_SYS_BR3 /* in case it's used for ENV */
381 #define CONFIG_SYS_SRAM_BASE SRAM_BASE
382 #define CONFIG_SYS_SRAM_SIZE SRAM_SIZE
385 * BR4/OR4 - Board Control & Status (8 bit)
387 #define BCSR_BASE 0xFC000000
388 #define CONFIG_SYS_OR4 0xFFFF0120 /* BI (internal) */
389 #define CONFIG_SYS_BR4 ((BCSR_BASE & BR_BA_MSK) | BR_PS_8 | BR_V)
392 * BR5/OR5 - IP Slot A/B (16 bit)
394 #define IP_SLOT_BASE 0x40000000
395 #define CONFIG_SYS_OR5 0xFE00010C /* SETA/TRLX/BI/ SCY=0 (external) */
396 #define CONFIG_SYS_BR5 ((IP_SLOT_BASE & BR_BA_MSK) | BR_PS_16 | BR_V)
399 * BR6/OR6 - VME STD (16 bit)
401 #define VME_STD_BASE 0xFE000000
402 #define CONFIG_SYS_OR6 0xFF00010C /* SETA/TRLX/BI/SCY=0 (external) */
403 #define CONFIG_SYS_BR6 ((VME_STD_BASE & BR_BA_MSK) | BR_PS_16 | BR_V)
406 * BR7/OR7 - SHORT I/O + RTC + IACK (16 bit)
408 #define VME_SHORT_BASE 0xFF000000
409 #define CONFIG_SYS_OR7 0xFF00010C /* SETA/TRLX/BI/ SCY=0 (external) */
410 #define CONFIG_SYS_BR7 ((VME_SHORT_BASE & BR_BA_MSK) | BR_PS_16 | BR_V)
412 /*-----------------------------------------------------------------------
413 * Board Control and Status Region:
414 *-----------------------------------------------------------------------
417 typedef struct ip860_bcsr_s {
418 unsigned char shmem_addr; /* +00 shared memory address register */
419 unsigned char reserved0;
420 unsigned char mbox_addr; /* +02 mailbox address register */
421 unsigned char reserved1;
422 unsigned char vme_int_mask; /* +04 VME Bus interrupt mask register */
423 unsigned char reserved2;
424 unsigned char vme_int_pend; /* +06 VME interrupt pending register */
425 unsigned char reserved3;
426 unsigned char bd_int_mask; /* +08 board interrupt mask register */
427 unsigned char reserved4;
428 unsigned char bd_int_pend; /* +0A board interrupt pending register */
429 unsigned char reserved5;
430 unsigned char bd_ctrl; /* +0C board control register */
431 unsigned char reserved6;
432 unsigned char bd_status; /* +0E board status register */
433 unsigned char reserved7;
434 unsigned char vme_irq; /* +10 VME interrupt request register */
435 unsigned char reserved8;
436 unsigned char vme_ivec; /* +12 VME interrupt vector register */
437 unsigned char reserved9;
438 unsigned char cli_mbox; /* +14 clear mailbox irq */
439 unsigned char reservedA;
440 unsigned char rtc; /* +16 RTC control register */
441 unsigned char reservedB;
442 unsigned char mbox_data; /* +18 mailbox read/write register */
443 unsigned char reservedC;
444 unsigned char wd_trigger; /* +1A Watchdog trigger register */
445 unsigned char reservedD;
446 unsigned char rmw_req; /* +1C RMW request register */
447 unsigned char reservedE;
448 unsigned char bd_rev; /* +1E Board Revision register */
450 #endif /* __ASSEMBLY__ */
452 /*-----------------------------------------------------------------------
453 * Board Control Register: bd_ctrl (Offset 0x0C)
454 *-----------------------------------------------------------------------
456 #define BD_CTRL_IPLSE 0x80 /* IP Slot Long Select Enable */
457 #define BD_CTRL_WDOGE 0x40 /* Watchdog Enable */
458 #define BD_CTRL_FLWE 0x20 /* Flash Write Enable */
459 #define BD_CTRL_RWDN 0x10 /* VMEBus Requester Release When Done Enable */
461 /*-----------------------------------------------------------------------
463 *-----------------------------------------------------------------------
468 * Internal Definitions
472 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
473 #define BOOTFLAG_WARM 0x02 /* Software reboot */
475 #endif /* __CONFIG_H */