2 * (C) Copyright 2001-2005
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * SPDX-License-Identifier: GPL-2.0+
9 * board/config.h - configuration options, board specific
15 #include <mpc8xx_irq.h>
18 * High Level Configuration Options
21 #define CONFIG_MPC860 1
22 #define CONFIG_MPC860T 1
23 #define CONFIG_ICU862 1
24 #define CONFIG_MPC862 1
26 #define CONFIG_SYS_TEXT_BASE 0x40F00000
28 #define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
29 #undef CONFIG_8xx_CONS_SMC2
30 #undef CONFIG_8xx_CONS_NONE
31 #define CONFIG_BAUDRATE 9600
32 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
35 #define MPC8XX_FACT 24 /* Multiply by 24 */
36 #define MPC8XX_XIN 4165000 /* 4.165 MHz in */
37 #define CONFIG_8xx_GCLK_FREQ (MPC8XX_FACT * MPC8XX_XIN)
38 /* define if cant' use get_gclk_freq */
40 #if 1 /* for 50MHz version of processor */
41 #define MPC8XX_FACT 12 /* Multiply by 12 */
42 #define MPC8XX_XIN 4000000 /* 4 MHz in */
43 #define CONFIG_8xx_GCLK_FREQ 48000000 /* define if cant use get_gclk_freq */
44 #else /* for 80MHz version of processor */
45 #define MPC8XX_FACT 20 /* Multiply by 20 */
46 #define MPC8XX_XIN 4000000 /* 4 MHz in */
47 #define CONFIG_8xx_GCLK_FREQ 80000000 /* define if cant use get_gclk_freq */
52 #define CONFIG_BOOTDELAY -1 /* autoboot disabled */
54 #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
57 #define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo"
59 #undef CONFIG_BOOTARGS
60 #define CONFIG_BOOTCOMMAND \
62 "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
63 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \
66 #undef CONFIG_WATCHDOG /* watchdog disabled */
68 #define CONFIG_STATUS_LED 1 /* Status LED enabled */
73 #define CONFIG_BOOTP_SUBNETMASK
74 #define CONFIG_BOOTP_GATEWAY
75 #define CONFIG_BOOTP_HOSTNAME
76 #define CONFIG_BOOTP_BOOTPATH
77 #define CONFIG_BOOTP_BOOTFILESIZE
80 #undef CONFIG_SCC1_ENET /* disable SCC1 ethernet */
81 #define CONFIG_FEC_ENET 1 /* use FEC ethernet */
84 #define CONFIG_SYS_DISCOVER_PHY 1
86 #undef CONFIG_SYS_DISCOVER_PHY
89 #define CONFIG_MAC_PARTITION
90 #define CONFIG_DOS_PARTITION
92 /* enable I2C and select the hardware/software driver */
93 #undef CONFIG_HARD_I2C /* I2C with hardware support */
94 #define CONFIG_SOFT_I2C 1 /* I2C bit-banged */
95 # define CONFIG_SYS_I2C_SPEED 50000
96 # define CONFIG_SYS_I2C_SLAVE 0xFE
97 # define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
98 # define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
100 * Software (bit-bang) I2C driver configuration
102 #define PB_SCL 0x00000020 /* PB 26 */
103 #define PB_SDA 0x00000010 /* PB 27 */
105 #define I2C_INIT (immr->im_cpm.cp_pbdir |= PB_SCL)
106 #define I2C_ACTIVE (immr->im_cpm.cp_pbdir |= PB_SDA)
107 #define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA)
108 #define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0)
109 #define I2C_SDA(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SDA; \
110 else immr->im_cpm.cp_pbdat &= ~PB_SDA
111 #define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \
112 else immr->im_cpm.cp_pbdat &= ~PB_SCL
113 #define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
115 #define CONFIG_SYS_EEPROM_X40430 /* Use a Xicor X40430 EEPROM */
116 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* 16 bytes page write mode */
118 #define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
122 * Command line configuration.
124 #include <config_cmd_default.h>
126 #define CONFIG_CMD_ASKENV
127 #define CONFIG_CMD_DATE
128 #define CONFIG_CMD_DHCP
129 #define CONFIG_CMD_EEPROM
130 #define CONFIG_CMD_I2C
131 #define CONFIG_CMD_IDE
132 #define CONFIG_CMD_NFS
133 #define CONFIG_CMD_SNTP
137 * Miscellaneous configurable options
139 #define CONFIG_SYS_LONGHELP /* undef to save memory */
140 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
141 #if defined(CONFIG_CMD_KGDB)
142 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
144 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
146 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
147 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
148 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
150 #define CONFIG_SYS_MEMTEST_START 0x0100000 /* memtest works on */
151 #define CONFIG_SYS_MEMTEST_END 0x0400000 /* 1 ... 4 MB in DRAM */
153 #define CONFIG_SYS_LOAD_ADDR 0x00100000
155 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
158 * Low Level Configuration Settings
159 * (address mappings, register initial values, etc.)
160 * You should know what you are doing if you make changes here.
162 /*-----------------------------------------------------------------------
163 * Internal Memory Mapped Register
165 #define CONFIG_SYS_IMMR 0xF0000000
166 #define CONFIG_SYS_IMMR_SIZE ((uint)(64 * 1024))
168 /*-----------------------------------------------------------------------
169 * Definitions for initial stack pointer and data area (in DPRAM)
171 #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
172 #define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */
173 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
174 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
176 /*-----------------------------------------------------------------------
177 * Start addresses for the final memory configuration
178 * (Set up by the startup code)
179 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
181 #define CONFIG_SYS_SDRAM_BASE 0x00000000
182 #define CONFIG_SYS_FLASH_BASE 0x40000000
183 #define CONFIG_SYS_FLASH_SIZE ((uint)(16 * 1024 * 1024)) /* max 16Mbyte */
185 #define CONFIG_SYS_RESET_ADDRESS 0xFFF00100
189 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
191 #define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
194 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
196 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
197 #define CONFIG_SYS_MALLOC_LEN (256 << 10) /* Reserve 256 kB for malloc() */
200 * For booting Linux, the board info and command line data
201 * have to be in the first 8 MB of memory, since this is
202 * the maximum mapped by the Linux kernel during initialization.
204 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
205 /*-----------------------------------------------------------------------
208 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
209 #define CONFIG_SYS_MAX_FLASH_SECT 64 /* max number of sectors on one chip */
211 #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
212 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
215 #define CONFIG_ENV_IS_IN_FLASH 1
216 #define CONFIG_ENV_OFFSET 0x00F40000
218 #define CONFIG_ENV_SECT_SIZE 0x40000 /* Total Size of Environment sector */
219 #define CONFIG_ENV_SIZE 0x4000 /* Used Size of Environment Sector */
220 #define CONFIG_SYS_USE_PPCENV /* Environment embedded in sect .ppcenv */
222 /*-----------------------------------------------------------------------
223 * Cache Configuration
225 #define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
226 #if defined(CONFIG_CMD_KGDB)
227 #define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */
230 /*-----------------------------------------------------------------------
231 * SYPCR - System Protection Control 11-9
232 * SYPCR can only be written once after reset!
233 *-----------------------------------------------------------------------
234 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
236 #if defined(CONFIG_WATCHDOG)
237 #define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
238 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
240 #define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
243 /*-----------------------------------------------------------------------
244 * SIUMCR - SIU Module Configuration 11-6
245 *-----------------------------------------------------------------------
246 * PCMCIA config., multi-function pin tri-state
248 #define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
250 /*-----------------------------------------------------------------------
251 * TBSCR - Time Base Status and Control 11-26
252 *-----------------------------------------------------------------------
253 * Clear Reference Interrupt Status, Timebase freezing enabled
255 #define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBE)
257 /*-----------------------------------------------------------------------
258 * PISCR - Periodic Interrupt Status and Control 11-31
259 *-----------------------------------------------------------------------
260 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
262 #define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF)
264 /*-----------------------------------------------------------------------
265 * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
266 *-----------------------------------------------------------------------
267 * set the PLL, the low-power modes and the reset control (15-29)
269 #define CONFIG_SYS_PLPRCR (((MPC8XX_FACT-1) << PLPRCR_MF_SHIFT) | \
270 PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
272 /*-----------------------------------------------------------------------
273 * SCCR - System Clock and reset Control Register 15-27
274 *-----------------------------------------------------------------------
275 * Set clock output, timebase and RTC source and divider,
276 * power management and some other internal clocks
278 #ifdef CONFIG_100MHz /* for 100 MHz, external bus is half CPU clock */
280 #define CONFIG_SYS_SCCR (SCCR_TBS | SCCR_COM00 | SCCR_DFSYNC00 | \
281 SCCR_DFBRG00 | SCCR_DFNL000 | SCCR_DFNH000 | \
282 SCCR_DFLCD000 |SCCR_DFALCD00 | SCCR_EBDF01)
283 #else /* up to 50 MHz we use a 1:1 clock */
284 #define SCCR_MASK SCCR_EBDF11
285 #define CONFIG_SYS_SCCR (SCCR_TBS | SCCR_COM00 | SCCR_DFSYNC00 | \
286 SCCR_DFBRG00 | SCCR_DFNL000 | SCCR_DFNH000 | \
287 SCCR_DFLCD000 |SCCR_DFALCD00 )
288 #endif /* CONFIG_100MHz */
290 /*-----------------------------------------------------------------------
291 * RCCR - RISC Controller Configuration Register 19-4
292 *-----------------------------------------------------------------------
294 /* +0x09C4 => DRQP = 10 (IDMA requests have lowest priority) */
295 #define CONFIG_SYS_RCCR 0x0020
297 /*-----------------------------------------------------------------------
299 *-----------------------------------------------------------------------
301 #define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000)
302 #define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 )
303 #define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000)
304 #define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 )
305 #define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000)
306 #define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 )
307 #define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000)
308 #define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 )
310 /*-----------------------------------------------------------------------
311 * PCMCIA Power Switch
313 * The ICU862 uses a TPS2205 PC-Card Power-Interface Switch to
314 * control the voltages on the PCMCIA slot which is connected to Port B
315 *-----------------------------------------------------------------------
318 #define TPS2205_VCC5 0x00008000 /* PB.16: 5V Voltage Control */
319 #define TPS2205_VCC3 0x00004000 /* PB.17: 3V Voltage Control */
320 #define TPS2205_VPP_PGM 0x00002000 /* PB.18: PGM Voltage Control */
321 #define TPS2205_VPP_VCC 0x00001000 /* PB.19: VPP Voltage Control */
322 #define TPS2205_SHDN 0x00000200 /* PB.22: Shutdown */
323 #define TPS2205_OUTPUTS ( TPS2205_VCC5 | TPS2205_VCC3 | \
324 TPS2205_VPP_PGM | TPS2205_VPP_VCC | \
328 #define TPS2205_OC 0x00000100 /* PB.23: Over-Current */
329 #define TPS2205_INPUTS ( TPS2205_OC )
331 /*-----------------------------------------------------------------------
332 * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
333 *-----------------------------------------------------------------------
336 #define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */
337 #define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
339 #undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
340 #undef CONFIG_IDE_LED /* LED for ide not supported */
341 #undef CONFIG_IDE_RESET /* reset for ide not supported */
343 #define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
344 #define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
346 #define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
348 #define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR
350 /* Offset for data I/O */
351 #define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
353 /* Offset for normal register accesses */
354 #define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
356 /* Offset for alternate registers */
357 #define CONFIG_SYS_ATA_ALT_OFFSET 0x0100
360 /*-----------------------------------------------------------------------
362 *-----------------------------------------------------------------------
365 #define CONFIG_SYS_DER 0
367 /* Because of the way the 860 starts up and assigns CS0 the
368 * entire address space, we have to set the memory controller
369 * differently. Normally, you write the option register
370 * first, and then enable the chip select by writing the
371 * base register. For CS0, you must write the base register
372 * first, followed by the option register.
376 * Init Memory Controller:
378 * BR0 and OR0 (FLASH)
381 #define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */
382 #define FLASH_BASE1_PRELIM 0x0 /* FLASH bank #1 */
384 #define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */
385 #define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */
387 /* FLASH timing: ACS = 10, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 0 */
388 #define CONFIG_SYS_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_DIV4 | OR_BI | OR_SCY_3_CLK | OR_TRLX)
390 #define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
392 #define CONFIG_SYS_OR0_PRELIM 0xFF000954 /* Real values for the board */
393 #define CONFIG_SYS_BR0_PRELIM 0x40000001 /* Real values for the board */
396 * BR1 and OR1 (SDRAM)
398 #define SDRAM_BASE1_PRELIM 0x00000000 /* SDRAM bank */
399 #define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */
401 #define CONFIG_SYS_OR_TIMING_SDRAM 0x00000800 /* BIH is not set */
403 #define CONFIG_SYS_OR1_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM)
404 #define CONFIG_SYS_BR1_PRELIM ((SDRAM_BASE1_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V)
407 * Memory Periodic Timer Prescaler
410 /* periodic timer for refresh */
411 #define CONFIG_SYS_MAMR_PTA 97 /* start with divider for 100 MHz */
413 /* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit */
414 #define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */
415 #define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */
417 /* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */
418 #define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */
419 #define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */
422 * MAMR settings for SDRAM
426 #define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
427 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
428 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
430 #define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
431 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
432 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
434 #define CONFIG_SYS_MAMR 0x13a01114
436 #ifdef CONFIG_MPC860T
438 /* Interrupt level assignments.
440 #define FEC_INTERRUPT SIU_LEVEL1 /* FEC interrupt */
442 #endif /* CONFIG_MPC860T */
445 #endif /* __CONFIG_H */