2 * Copyright 2009-2010 eXMeritus, A Boeing Company
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 * HardwareWall HWW-1U-1A airborne unit configuration file
29 /* High-level system configuration options */
30 #define CONFIG_BOOKE /* Power/PowerPC Book-E */
31 #define CONFIG_E500 /* e500 (Power ISA v2.03 with SPE) */
32 #define CONFIG_MPC85xx /* MPC8540/60/55/41/48 family */
33 #define CONFIG_FSL_ELBC /* FreeScale Enhanced LocalBus Cntlr */
34 #define CONFIG_FSL_LAW /* FreeScale Local Access Window */
35 #define CONFIG_P2020 /* FreeScale P2020 */
36 #define CONFIG_HWW1U1A /* eXMeritus HardwareWall HWW-1U-1A */
37 #define CONFIG_MP /* Multiprocessing support */
38 #define CONFIG_HWCONFIG /* Use hwconfig from environment */
40 #define CONFIG_L2_CACHE /* L2 cache enabled */
41 #define CONFIG_BTB /* Branch predition enabled */
43 #define CONFIG_PANIC_HANG /* No board reset on panic */
44 #define CONFIG_BOARD_EARLY_INIT_R /* Call board_early_init_r() */
45 #define CONFIG_CMD_REGINFO /* Dump various CPU regs */
48 * Allow the use of 36-bit physical addresses. Device-trees with 64-bit
49 * addresses have known compatibility issues with some existing kernels.
51 #define CONFIG_ENABLE_36BIT_PHYS
52 #define CONFIG_PHYS_64BIT
53 #define CONFIG_ADDR_MAP
54 #define CONFIG_SYS_NUM_ADDR_MAP 16 /* Number of entries in TLB1 */
56 /* Reserve plenty of RAM for malloc (we have 2GB+) */
57 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024)
59 /* How much L2 cache do we map so we can use it as RAM */
60 #define CONFIG_SYS_INIT_RAM_LOCK
61 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
63 /* This is our temporary global data area just above the stack */
64 #define CONFIG_SYS_GBL_DATA_OFFSET \
65 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
67 /* The stack grows down from the global data area */
68 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
70 /* Enable IRQs and watchdog with a 1000Hz system decrementer */
71 #define CONFIG_CMD_IRQ
72 #define CONFIG_SYS_HZ 1000
75 /* -------------------------------------------------------------------- */
78 * Clock crystal configuration:
79 * (1) SYS: 66.666MHz +/- 50ppm (drives CPU/PCI/DDR)
80 * (2) CCB: Multiplier from SYS_CLK
81 * (3) RTC: 25.000MHz +/- 50ppm (sampled against CCB clock)
83 #define CONFIG_SYS_CLK_FREQ 66666000/*Hz*/
84 #define CONFIG_DDR_CLK_FREQ 66666000/*Hz*/
87 /* -------------------------------------------------------------------- */
92 * 0x0000_0000 0x7fff_ffff 2G DDR2 ECC SDRAM
93 * 0x8000_0000 0x9fff_ffff 512M PCI-E Bus 1
94 * 0xa000_0000 0xbfff_ffff 512M PCI-E Bus 2 (unused)
95 * 0xc000_0000 0xdfff_ffff 512M PCI-E Bus 3
96 * 0xe000_0000 0xe7ff_ffff 128M Spansion FLASH
97 * 0xe800_0000 0xefff_ffff 128M Spansion FLASH
98 * 0xffd0_0000 0xffd0_3fff 16K L1 boot stack (TLB0)
99 * 0xffe0_0000 0xffef_ffff 1M CCSR
100 * 0xffe0_5000 0xffe0_5fff 4K Enhanced LocalBus Controller
103 /* Virtual Memory Map */
104 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
105 #define CONFIG_SYS_SDRAM_BASE 0x00000000
106 #define CONFIG_SYS_PCIE3_MEM_VIRT 0x80000000
107 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
108 #define CONFIG_SYS_PCIE1_MEM_VIRT 0xc0000000
109 #define CONFIG_SYS_FLASH_BASE 0xe0000000
110 #define CONFIG_SYS_PCIE3_IO_VIRT 0xffc00000
111 #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000
112 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc20000
113 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000
114 #define CONFIG_SYS_CCSRBAR 0xffe00000 /* CCSRBAR @ runtime */
116 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */
117 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
118 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
119 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
120 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
121 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
123 /* Physical Memory Map */
124 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc00000000ull
125 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
126 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc40000000ull
127 #define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull
128 #define CONFIG_SYS_PCIE3_IO_PHYS 0xfffc00000ull
129 #define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull
130 #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc20000ull
131 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS 0xfffd00000ull
132 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf /* for ASM code */
133 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xffd00000 /* for ASM code */
134 #define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0xf /* for ASM code */
135 #define CONFIG_SYS_CCSRBAR_PHYS_LOW 0xffe00000 /* for ASM code */
138 /* -------------------------------------------------------------------- */
140 /* U-Boot image (MONITOR_BASE == TEXT_BASE) */
141 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc /* Top address in flash */
142 #define CONFIG_SYS_TEXT_BASE 0xeff80000 /* Start of U-Boot image */
143 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
144 #define CONFIG_SYS_MONITOR_LEN 0x80000 /* 512kB (4 flash sectors) */
147 * U-Boot Environment Image: The two sectors immediately below U-Boot
148 * form the U-Boot environment (regular and redundant).
150 #define CONFIG_ENV_IS_IN_FLASH /* The environment image is stored in FLASH */
151 #define CONFIG_ENV_OVERWRITE /* Allow "protected" variables to be erased */
152 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128kB (1 flash sector) */
153 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
154 #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR - CONFIG_ENV_SECT_SIZE)
156 /* Only use 8kB of each environment sector for data */
157 #define CONFIG_ENV_SIZE 0x2000 /* 8kB */
158 #define CONFIG_ENV_SIZE_REDUND 0x2000 /* 8kB */
161 /* -------------------------------------------------------------------- */
163 /* Serial Console Configuration */
164 #define CONFIG_CONS_INDEX 1
165 #define CONFIG_SYS_NS16550
166 #define CONFIG_SYS_NS16550_SERIAL
167 #define CONFIG_SYS_NS16550_REG_SIZE 1
168 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
170 #define CONFIG_BAUDRATE 115200
171 #define CONFIG_SYS_BAUDRATE_TABLE \
172 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
174 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
175 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
177 /* Echo back characters received during a serial download */
178 #define CONFIG_LOADS_ECHO
180 /* Allow a serial-download to temporarily change baud */
181 #define CONFIG_SYS_LOADS_BAUD_CHANGE
184 /* -------------------------------------------------------------------- */
186 /* PCI and PCI-Express Support */
187 #define CONFIG_PCI /* Enable PCI/PCIE */
188 #define CONFIG_PCI_PNP /* Scan PCI busses */
189 #define CONFIG_CMD_PCI /* Enable the "pci" command */
190 #define CONFIG_FSL_PCI_INIT /* Common FreeScale PCI initialization */
191 #define CONFIG_FSL_PCIE_RESET /* We have PCI-E reset errata */
192 #define CONFIG_SYS_PCI_64BIT /* PCI resources are 64-bit */
193 #define CONFIG_PCI_SCAN_SHOW /* Display PCI scan during boot */
195 /* Enable 2 of the 3 PCI-E controllers */
200 /* Display human-readable names when initializing */
201 #define CONFIG_SYS_PCIE3_NAME "Intel 82571EB"
202 #define CONFIG_SYS_PCIE2_NAME "Unused"
203 #define CONFIG_SYS_PCIE1_NAME "Silicon Image SIL3531"
207 * Memory space is mapped 1-1, but I/O space must start from 0.
209 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
210 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
211 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
212 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
213 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
214 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
217 /* -------------------------------------------------------------------- */
219 /* Generic FreeScale hardware I2C support */
220 #define CONFIG_HARD_I2C
221 #define CONFIG_FSL_I2C
222 #define CONFIG_CMD_I2C
223 #define CONFIG_I2C_MULTI_BUS
224 #define CONFIG_SYS_I2C_OFFSET 0x3000
225 #define CONFIG_SYS_I2C2_OFFSET 0x3100
227 /* I2C bus configuration */
228 #define CONFIG_SYS_I2C_SPEED 400000
229 #define CONFIG_SYS_I2C_SLAVE 0x7F
231 /* DDR2 SO-RDIMM SPD EEPROM is at I2C0-0x51 */
232 #define CONFIG_SYS_SPD_BUS_NUM 0
233 #define SPD_EEPROM_ADDRESS 0x51
235 /* DS1339 RTC is at I2C0-0x68 (I know it says "DS1337", it's a DS1339) */
236 #define CONFIG_CMD_DATE
237 #define CONFIG_RTC_DS1337
238 #define CONFIG_SYS_RTC_BUS_NUM 0
239 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
240 /* Turn off RTC square-wave output to save battery */
241 #define CONFIG_SYS_RTC_DS1337_NOOSC
243 /* PCA9554 is at I2C1-0x3f (I know it says "PCA953X", it's a PCA9554) */
244 #define CONFIG_PCA953X
245 #define CONFIG_CMD_PCA953X
246 #define CONFIG_CMD_PCA953X_INFO
247 #define CONFIG_SYS_I2C_PCA953X_ADDR 0x3f
250 /* -------------------------------------------------------------------- */
252 /* FreeScale DDR2/3 SDRAM Controller */
253 #define CONFIG_FSL_DDR2 /* Our SDRAM slot is DDR2 */
254 #define CONFIG_DDR_ECC /* Enable ECC by default */
255 #define CONFIG_DDR_SPD /* Detect DDR config from SPD EEPROM */
256 #define CONFIG_SPD_EEPROM /* ...why 2 config variables for this? */
257 #define CONFIG_VERY_BIG_RAM /* Allow 2GB+ of RAM */
258 #define CONFIG_CMD_SDRAM
260 /* Standard P2020 DDR controller parameters */
261 #define CONFIG_NUM_DDR_CONTROLLERS 1
262 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
263 #define CONFIG_CHIP_SELECTS_PER_CTRL 2
265 /* Make sure to tell the DDR controller to preinitialze all of RAM */
266 #define CONFIG_MEM_INIT_VALUE 0xDEADBEEF
267 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
270 /* -------------------------------------------------------------------- */
272 /* FLASH Memory Configuration (2x 128MB SPANSION FLASH) */
273 #define CONFIG_FLASH_CFI_DRIVER
274 #define CONFIG_SYS_FLASH_CFI
275 #define CONFIG_SYS_FLASH_EMPTY_INFO
276 #define CONFIG_SYS_FLASH_AMD_CHECK_DQ7
278 /* Flash banks (2x 128MB) */
279 #define FLASH0_PHYS (CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000ull)
280 #define FLASH1_PHYS (CONFIG_SYS_FLASH_BASE_PHYS + 0x0000000ull)
281 #define CONFIG_SYS_MAX_FLASH_BANKS 2
282 #define CONFIG_SYS_MAX_FLASH_SECT 1024
283 #define CONFIG_SYS_FLASH_BANKS_LIST { FLASH0_PHYS, FLASH1_PHYS }
286 * Flash access modes and timings (values are the defaults after a RESET).
288 * NOTE: These could probably be optimized but are more than sufficient for
289 * this particular system for the moment.
291 #define FLASH_BRx (BR_PS_16 | BR_MS_GPCM | BR_V)
292 #define FLASH_ORx (OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_XACS \
293 | OR_GPCM_SCY_15 | OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD)
295 /* Configure both flash banks */
296 #define CONFIG_SYS_BR0_PRELIM (FLASH_BRx | BR_PHYS_ADDR(FLASH0_PHYS))
297 #define CONFIG_SYS_BR1_PRELIM (FLASH_BRx | BR_PHYS_ADDR(FLASH1_PHYS))
298 #define CONFIG_SYS_OR0_PRELIM (FLASH_ORx | OR_AM_128MB)
299 #define CONFIG_SYS_OR1_PRELIM (FLASH_ORx | OR_AM_128MB)
301 /* Flash timeouts (in ms) */
302 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000UL /* Erase (60s) */
303 #define CONFIG_SYS_FLASH_WRITE_TOUT 500UL /* Write (0.5s) */
305 /* Quiet flash testing */
306 #define CONFIG_SYS_FLASH_QUIET_TEST
308 /* Make program/erase count down from 45/5 (9....8....7....) */
309 #define CONFIG_FLASH_SHOW_PROGRESS 45
312 /* -------------------------------------------------------------------- */
314 /* Ethernet Device Support */
315 #define CONFIG_MII /* Enable MII PHY code */
316 #define CONFIG_MII_DEFAULT_TSEC /* ??? Copied from P2020DS */
317 #define CONFIG_PHY_GIGE /* Support Gigabit PHYs */
318 #define CONFIG_ETHPRIME "e1000#0" /* Default to external ports */
320 /* Turn on various helpful networking commands */
321 #define CONFIG_CMD_DHCP
322 #define CONFIG_CMD_MII
323 #define CONFIG_CMD_NET
324 #define CONFIG_CMD_PING
326 /* On-chip FreeScale P2020 "tsec" Ethernet (oneway fibers and peer) */
327 #define CONFIG_TSEC_ENET
331 #define CONFIG_TSEC1_NAME "owt0"
332 #define CONFIG_TSEC2_NAME "owt1"
333 #define CONFIG_TSEC3_NAME "peer"
334 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
335 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
336 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
337 #define TSEC1_PHYIDX 0
338 #define TSEC2_PHYIDX 0
339 #define TSEC3_PHYIDX 0
340 #define TSEC1_PHY_ADDR 2
341 #define TSEC2_PHY_ADDR 3
342 #define TSEC3_PHY_ADDR 4
343 #define TSEC3_PHY_ADDR_CPUA 4
344 #define TSEC3_PHY_ADDR_CPUB 5
346 /* PCI-E dual-port E1000 (external ethernet ports) */
348 #define CONFIG_E1000_SPI
349 #define CONFIG_E1000_SPI_GENERIC
350 #define CONFIG_CMD_E1000
352 /* We need the SPI infrastructure to poke the E1000's EEPROM */
355 #define CONFIG_CMD_SPI
356 #define MAX_SPI_BYTES 32
359 /* -------------------------------------------------------------------- */
361 /* USB Thumbdrive Device Support */
362 #define CONFIG_USB_EHCI
363 #define CONFIG_USB_EHCI_FSL
364 #define CONFIG_USB_STORAGE
365 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
366 #define CONFIG_CMD_USB
368 /* Partition and Filesystem support */
369 #define CONFIG_DOS_PARTITION
370 #define CONFIG_EFI_PARTITION
371 #define CONFIG_ISO_PARTITION
372 #define CONFIG_CMD_EXT2
373 #define CONFIG_CMD_FAT
376 /* -------------------------------------------------------------------- */
378 /* Command line configuration. */
379 #define CONFIG_CMDLINE_EDITING /* Enable command editing */
380 #define CONFIG_COMMAND_HISTORY /* Enable command history */
381 #define CONFIG_AUTO_COMPLETE /* Enable command completion */
382 #define CONFIG_SYS_LONGHELP /* Enable detailed command help */
383 #define CONFIG_SYS_MAXARGS 128 /* Up to 128 command-line args */
384 #define CONFIG_SYS_PBSIZE 8192 /* Allow up to 8k printed lines */
385 #define CONFIG_SYS_CBSIZE 4096 /* Allow up to 4k command lines */
386 #define CONFIG_SYS_BARGSIZE 4096 /* Allow up to 4k boot args */
387 #define CONFIG_SYS_HUSH_PARSER /* Enable a fancier shell */
388 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " /* Command-line continuation */
390 /* A little extra magic here for the prompt */
391 #define CONFIG_SYS_PROMPT hww1u1a_get_ps1()
393 const char *hww1u1a_get_ps1(void);
396 /* Include a bunch of default commands we probably want */
397 #include <config_cmd_default.h>
399 /* Other helpful shell-like commands */
402 #define CONFIG_CMD_MD5SUM
403 #define CONFIG_CMD_SHA1
404 #define CONFIG_CMD_ASKENV
405 #define CONFIG_CMD_SETEXPR
408 /* -------------------------------------------------------------------- */
410 /* Image manipulation and booting */
412 /* We use the OpenFirmware-esque "Flattened Device Tree" */
413 #define CONFIG_OF_LIBFDT
414 #define CONFIG_OF_BOARD_SETUP
415 #define CONFIG_OF_STDOUT_VIA_ALIAS
418 * For booting Linux, the board info and command line data
419 * have to be in the first 64 MB of memory, since this is
420 * the maximum mapped by the Linux kernel during initialization.
422 #define CONFIG_CMD_ELF
423 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Maximum kernel memory map */
424 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Maximum kernel size of 64MB */
426 /* This is the default address for commands with an optional address arg */
427 #define CONFIG_LOADADDR 100000
428 #define CONFIG_SYS_LOAD_ADDR 0x100000
430 /* Test memory starting from the default load address to just below 2GB */
431 #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_LOAD_ADDR
432 #define CONFIG_SYS_MEMTEST_END 0x7f000000
434 #define CONFIG_BOOTDELAY 20
435 #define CONFIG_BOOTCOMMAND "echo Not yet flashed"
436 #define CONFIG_BOOTARGS ""
437 #define CONFIG_BOOTARGS_DYNAMIC "console=ttyS0,${baudrate}n1"
439 /* Extra environment parameters */
440 #define CONFIG_EXTRA_ENV_SETTINGS \
441 "ethprime=e1000#0\0" \
443 "setbootargs=setenv bootargs " \
444 "\"${bootargs} "CONFIG_BOOTARGS_DYNAMIC"\"\0" \
445 "perf_mode=performance\0" \
446 "hwconfig=" "fsl_ddr:ctlr_intlv=bank,bank_intlv=cs0_cs1;" \
447 "usb1:dr_mode=host,phy_type=ulpi\0" \
448 "flkernel=0xe8000000\0" \
449 "flinitramfs=0xe8800000\0" \
450 "fldevicetree=0xeff20000\0" \
451 "flbootm=bootm ${flkernel} ${flinitramfs} ${fldevicetree}\0" \
452 "flboot=run preboot; run flbootm\0"
454 #endif /* __CONFIG_H */