3 * Yusdi Santoso, Adaptec Inc., yusdi_santoso@adaptec.com
5 * (C) Copyright 2001, 2002
6 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
8 * SPDX-License-Identifier: GPL-2.0+
11 /* ------------------------------------------------------------------------- */
14 * board/config.h - configuration options, board specific
21 * High Level Configuration Options
25 #define CONFIG_MPC824X 1
26 #define CONFIG_MPC8245 1
27 #define CONFIG_HIDDEN_DRAGON 1
29 #define CONFIG_SYS_TEXT_BASE 0xFFF00000
37 #define CONFIG_CONS_INDEX 3 /* set to '3' for on-chip DUART */
38 #define CONFIG_BAUDRATE 9600
39 #define CONFIG_DRAM_SPEED 100 /* MHz */
45 #define CONFIG_BOOTP_BOOTFILESIZE
46 #define CONFIG_BOOTP_BOOTPATH
47 #define CONFIG_BOOTP_GATEWAY
48 #define CONFIG_BOOTP_HOSTNAME
52 * Command line configuration.
54 #include <config_cmd_default.h>
56 #define CONFIG_CMD_EEPROM
57 #define CONFIG_CMD_ELF
58 #define CONFIG_CMD_I2C
59 #define CONFIG_CMD_NET
60 #define CONFIG_CMD_PCI
61 #define CONFIG_CMD_PING
64 * Miscellaneous configurable options
66 #define CONFIG_SYS_LONGHELP 1 /* undef to save memory */
67 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
68 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
69 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
70 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
71 #define CONFIG_SYS_LOAD_ADDR 0x00100000 /* default load address */
73 /*-----------------------------------------------------------------------
75 *-----------------------------------------------------------------------
77 #define CONFIG_PCI /* include pci support */
78 #define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
82 #define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
84 #define PCI_ENET0_IOADDR 0x80000000
85 #define PCI_ENET0_MEMADDR 0x80000000
86 #define PCI_ENET1_IOADDR 0x81000000
87 #define PCI_ENET1_MEMADDR 0x81000000
89 #define CONFIG_RTL8139
91 /* Make sure the ethaddr can be overwritten
92 TODO: Remove this on final product
94 #define CONFIG_ENV_OVERWRITE
96 /*-----------------------------------------------------------------------
97 * Start addresses for the final memory configuration
98 * (Set up by the startup code)
99 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
101 #define CONFIG_SYS_SDRAM_BASE 0x00000000
102 #define CONFIG_SYS_MAX_RAM_SIZE 0x02000000
104 #define CONFIG_SYS_RESET_ADDRESS 0xFFF00100
106 #if defined (USE_DINK32)
107 #define CONFIG_SYS_MONITOR_LEN 0x00030000
108 #define CONFIG_SYS_MONITOR_BASE 0x00090000
109 #define CONFIG_SYS_RAMBOOT 1
110 #define CONFIG_SYS_INIT_RAM_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
111 #define CONFIG_SYS_INIT_RAM_SIZE 0x10000
112 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
113 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
115 #undef CONFIG_SYS_RAMBOOT
116 #define CONFIG_SYS_MONITOR_LEN 0x00030000
117 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
120 #define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
121 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000
122 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
126 #define CONFIG_SYS_FLASH_BASE 0xFFE00000
127 #define CONFIG_SYS_FLASH_SIZE (2 * 1024 * 1024) /* Unity has onboard 1MByte flash */
128 #define CONFIG_ENV_IS_IN_FLASH 1
129 #define CONFIG_ENV_OFFSET 0x00004000 /* Offset of Environment Sector */
130 #define CONFIG_ENV_SIZE 0x00002000 /* Total Size of Environment Sector */
132 #define CONFIG_SYS_MALLOC_LEN (512 << 10) /* Reserve 512 kB for malloc() */
134 #define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest works on */
135 #define CONFIG_SYS_MEMTEST_END 0x02000000 /* 0 ... 32 MB in DRAM */
137 #define CONFIG_SYS_EUMB_ADDR 0xFC000000
139 #define CONFIG_SYS_ISA_MEM 0xFD000000
140 #define CONFIG_SYS_ISA_IO 0xFE000000
142 #define CONFIG_SYS_FLASH_RANGE_BASE 0xFFE00000 /* flash memory address range */
143 #define CONFIG_SYS_FLASH_RANGE_SIZE 0x00200000
144 #define FLASH_BASE0_PRELIM 0xFFE00000 /* processor board flash */
147 * select i2c support configuration
149 * Supported configurations are {none, software, hardware} drivers.
150 * If the software driver is chosen, there are some additional
151 * configuration items that the driver uses to drive the port pins.
153 #define CONFIG_HARD_I2C 1 /* To enable I2C support */
154 #undef CONFIG_SYS_I2C_SOFT /* I2C bit-banged */
155 #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
156 #define CONFIG_SYS_I2C_SLAVE 0x7F
158 #ifdef CONFIG_SYS_I2C_SOFT
159 #error "Soft I2C is not configured properly. Please review!"
160 #define CONFIG_SYS_I2C
161 #define CONFIG_SYS_I2C_SOFT_SPEED 50000
162 #define CONFIG_SYS_I2C_SOFT_SLAVE 0xFE
163 #define I2C_PORT 3 /* Port A=0, B=1, C=2, D=3 */
164 #define I2C_ACTIVE (iop->pdir |= 0x00010000)
165 #define I2C_TRISTATE (iop->pdir &= ~0x00010000)
166 #define I2C_READ ((iop->pdat & 0x00010000) != 0)
167 #define I2C_SDA(bit) if(bit) iop->pdat |= 0x00010000; \
168 else iop->pdat &= ~0x00010000
169 #define I2C_SCL(bit) if(bit) iop->pdat |= 0x00020000; \
170 else iop->pdat &= ~0x00020000
171 #define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
172 #endif /* CONFIG_SYS_I2C_SOFT */
174 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 /* EEPROM IS24C02 */
175 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
176 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
177 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
179 #define CONFIG_SYS_FLASH_BANKS { FLASH_BASE0_PRELIM }
181 /*-----------------------------------------------------------------------
182 * Definitions for initial stack pointer and data area (in DPRAM)
186 /* #define CONFIG_WINBOND_83C553 1 / *has a winbond bridge */
187 #define CONFIG_SYS_USE_WINBOND_IDE 0 /*use winbond 83c553 internal IDE ctrlr */
188 #define CONFIG_SYS_WINBOND_ISA_CFG_ADDR 0x80005800 /*pci-isa bridge config addr */
189 #define CONFIG_SYS_WINBOND_IDE_CFG_ADDR 0x80005900 /*ide config addr */
191 #define CONFIG_SYS_IDE_MAXBUS 2 /* max. 2 IDE busses */
192 #define CONFIG_SYS_IDE_MAXDEVICE (CONFIG_SYS_IDE_MAXBUS*2) /* max. 2 drives per IDE bus */
194 /* TODO: Change this to VIA686A */
197 * NS87308 Configuration
199 #define CONFIG_NS87308 /* Nat Semi super-io controller on ISA bus */
201 #define CONFIG_SYS_NS87308_BADDR_10 1
203 #define CONFIG_SYS_NS87308_DEVS ( CONFIG_SYS_NS87308_UART1 | \
204 CONFIG_SYS_NS87308_UART2 | \
205 CONFIG_SYS_NS87308_POWRMAN | \
206 CONFIG_SYS_NS87308_RTC_APC )
208 #undef CONFIG_SYS_NS87308_PS2MOD
210 #define CONFIG_SYS_NS87308_CS0_BASE 0x0076
211 #define CONFIG_SYS_NS87308_CS0_CONF 0x30
212 #define CONFIG_SYS_NS87308_CS1_BASE 0x0075
213 #define CONFIG_SYS_NS87308_CS1_CONF 0x30
214 #define CONFIG_SYS_NS87308_CS2_BASE 0x0074
215 #define CONFIG_SYS_NS87308_CS2_CONF 0x30
218 * NS16550 Configuration
220 #define CONFIG_SYS_NS16550
221 #define CONFIG_SYS_NS16550_SERIAL
223 #define CONFIG_SYS_NS16550_REG_SIZE 1
225 #if (CONFIG_CONS_INDEX > 2)
226 #define CONFIG_SYS_NS16550_CLK CONFIG_DRAM_SPEED*1000000
228 #define CONFIG_SYS_NS16550_CLK 1843200
231 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_ISA_IO + CONFIG_SYS_NS87308_UART1_BASE)
232 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_ISA_IO + CONFIG_SYS_NS87308_UART2_BASE)
233 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_EUMB_ADDR + 0x4500)
234 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_EUMB_ADDR + 0x4600)
237 * Low Level Configuration Settings
238 * (address mappings, register initial values, etc.)
239 * You should know what you are doing if you make changes here.
242 #define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */
244 #define CONFIG_SYS_ROMNAL 7 /*rom/flash next access time */
245 #define CONFIG_SYS_ROMFAL 11 /*rom/flash access time */
247 #define CONFIG_SYS_REFINT 430 /* no of clock cycles between CBR refresh cycles */
249 /* the following are for SDRAM only*/
250 #define CONFIG_SYS_BSTOPRE 121 /* Burst To Precharge, sets open page interval */
251 #define CONFIG_SYS_REFREC 8 /* Refresh to activate interval */
252 #define CONFIG_SYS_RDLAT 4 /* data latency from read command */
253 #define CONFIG_SYS_PRETOACT 3 /* Precharge to activate interval */
254 #define CONFIG_SYS_ACTTOPRE 5 /* Activate to Precharge interval */
255 #define CONFIG_SYS_ACTORW 3 /* Activate to R/W */
256 #define CONFIG_SYS_SDMODE_CAS_LAT 3 /* SDMODE CAS latency */
257 #define CONFIG_SYS_SDMODE_WRAP 0 /* SDMODE wrap type */
259 #define CONFIG_SYS_SDMODE_BURSTLEN 2 /* OBSOLETE! SDMODE Burst length 2=4, 3=8 */
262 #define CONFIG_SYS_REGISTERD_TYPE_BUFFER 1
263 #define CONFIG_SYS_EXTROM 1
264 #define CONFIG_SYS_REGDIMM 0
267 /* memory bank settings*/
269 * only bits 20-29 are actually used from these vales to set the
270 * start/end address the upper two bits will be 0, and the lower 20
271 * bits will be set to 0x00000 for a start address, or 0xfffff for an
274 #define CONFIG_SYS_BANK0_START 0x00000000
275 #define CONFIG_SYS_BANK0_END (CONFIG_SYS_MAX_RAM_SIZE - 1)
276 #define CONFIG_SYS_BANK0_ENABLE 1
277 #define CONFIG_SYS_BANK1_START 0x3ff00000
278 #define CONFIG_SYS_BANK1_END 0x3fffffff
279 #define CONFIG_SYS_BANK1_ENABLE 0
280 #define CONFIG_SYS_BANK2_START 0x3ff00000
281 #define CONFIG_SYS_BANK2_END 0x3fffffff
282 #define CONFIG_SYS_BANK2_ENABLE 0
283 #define CONFIG_SYS_BANK3_START 0x3ff00000
284 #define CONFIG_SYS_BANK3_END 0x3fffffff
285 #define CONFIG_SYS_BANK3_ENABLE 0
286 #define CONFIG_SYS_BANK4_START 0x00000000
287 #define CONFIG_SYS_BANK4_END 0x00000000
288 #define CONFIG_SYS_BANK4_ENABLE 0
289 #define CONFIG_SYS_BANK5_START 0x00000000
290 #define CONFIG_SYS_BANK5_END 0x00000000
291 #define CONFIG_SYS_BANK5_ENABLE 0
292 #define CONFIG_SYS_BANK6_START 0x00000000
293 #define CONFIG_SYS_BANK6_END 0x00000000
294 #define CONFIG_SYS_BANK6_ENABLE 0
295 #define CONFIG_SYS_BANK7_START 0x00000000
296 #define CONFIG_SYS_BANK7_END 0x00000000
297 #define CONFIG_SYS_BANK7_ENABLE 0
299 * Memory bank enable bitmask, specifying which of the banks defined above
300 are actually present. MSB is for bank #7, LSB is for bank #0.
302 #define CONFIG_SYS_BANK_ENABLE 0x01
304 #define CONFIG_SYS_ODCR 0xff /* configures line driver impedances, */
305 /* see 8240 book for bit definitions */
306 #define CONFIG_SYS_PGMAX 0x32 /* how long the 8240 retains the */
307 /* currently accessed page in memory */
308 /* see 8240 book for details */
310 /* SDRAM 0 - 256MB */
311 #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
312 #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
314 /* stack in DCACHE @ 1GB (no backing mem) */
315 #if defined(USE_DINK32)
316 #define CONFIG_SYS_IBAT1L (0x40000000 | BATL_PP_00 )
317 #define CONFIG_SYS_IBAT1U (0x40000000 | BATU_BL_128K )
319 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE)
320 #define CONFIG_SYS_IBAT1U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
324 #define CONFIG_SYS_IBAT2L (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
325 #define CONFIG_SYS_IBAT2U (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP)
327 /* Flash, config addrs, etc */
328 #define CONFIG_SYS_IBAT3L (0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
329 #define CONFIG_SYS_IBAT3U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
331 #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
332 #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
333 #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
334 #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
335 #define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
336 #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
337 #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
338 #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
341 * For booting Linux, the board info and command line data
342 * have to be in the first 8 MB of memory, since this is
343 * the maximum mapped by the Linux kernel during initialization.
345 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
346 /*-----------------------------------------------------------------------
349 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
350 #define CONFIG_SYS_MAX_FLASH_SECT 36 /* max number of sectors on one chip */
352 #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
353 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
355 /*-----------------------------------------------------------------------
356 * Cache Configuration
358 #define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8240 CPU */
359 #if defined(CONFIG_CMD_KGDB)
360 # define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
363 /* values according to the manual */
364 #define CONFIG_DRAM_50MHZ 1
365 #define CONFIG_SDRAM_50MHZ
368 #define NR_8259_INTS 1
370 #define CONFIG_DISK_SPINUP_TIME 1000000
372 #endif /* __CONFIG_H */