include/configs/GEN860T.h

   1 /*
   2  * (C) Copyright 2000
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  * Keith Outwater, keith_outwater@mvis.com
   5  *
   6  * See file CREDITS for list of people who contributed to this
   7  * project.
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License as
  11  * published by the Free Software Foundation; either version 2 of
  12  * the License, or (at your option) any later version.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  22  * MA 02111-1307 USA
  23  */
  24
  25 /*
  26  * board/config_GEN860T.h - board specific configuration options
  27  */
  28
  29 #ifndef __CONFIG_GEN860T_H
  30 #define __CONFIG_H
  31
  32 /*
  33  * High Level Configuration Options
  34  */
  35 #define CONFIG_MPC860
  36 #define CONFIG_GEN860T
  37
  38 #define CONFIG_SYS_TEXT_BASE            0x40000000
  39
  40 /*
  41  * Identify the board
  42  */
  43 #if !defined(CONFIG_SC)
  44 #define CONFIG_IDENT_STRING             " B2"
  45 #else
  46 #define CONFIG_IDENT_STRING             " SC"
  47 #endif
  48
  49 /*
  50  * Don't depend on the RTC clock to determine clock frequency -
  51  * the 860's internal rtc uses a 32.768 KHz clock which is
  52  * generated by the DS1337 - and the DS1337 clock can be turned off.
  53  */
  54 #if !defined(CONFIG_SC)
  55 #define CONFIG_8xx_GCLK_FREQ            66600000
  56 #else
  57 #define CONFIG_8xx_GCLK_FREQ            48000000
  58 #endif
  59
  60 /*
  61  * The RS-232 console port is on SMC1
  62  */
  63 #define CONFIG_8xx_CONS_SMC1
  64 #define CONFIG_BAUDRATE                 38400
  65
  66 /*
  67  * Print console information
  68  */
  69 #undef   CONFIG_SYS_CONSOLE_INFO_QUIET
  70
  71 /*
  72  * Set the autoboot delay in seconds.  A delay of -1 disables autoboot
  73  */
  74 #define CONFIG_BOOTDELAY                                5
  75
  76 /*
  77  * Pass the clock frequency to the Linux kernel in units of MHz
  78  */
  79 #define CONFIG_CLOCKS_IN_MHZ
  80
  81 #define CONFIG_PREBOOT          \
  82         "echo;echo"
  83
  84 #undef  CONFIG_BOOTARGS
  85 #define CONFIG_BOOTCOMMAND      \
  86         "bootp;" \
  87         "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
  88         "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \
  89         "bootm"
  90
  91 /*
  92  * Turn off echo for serial download by default.  Allow baud rate to be changed
  93  * for downloads
  94  */
  95 #undef  CONFIG_LOADS_ECHO
  96 #define CONFIG_SYS_LOADS_BAUD_CHANGE
  97
  98 /*
  99  * Turn off the watchdog timer
 100  */
 101 #undef  CONFIG_WATCHDOG
 102
 103 /*
 104  * Do not reboot if a panic occurs
 105  */
 106 #define CONFIG_PANIC_HANG
 107
 108 /*
 109  * Enable the status LED
 110  */
 111 #define CONFIG_STATUS_LED
 112
 113 /*
 114  * Reset address. We pick an address such that when an instruction
 115  * is executed at that address, a machine check exception occurs
 116  */
 117 #define CONFIG_SYS_RESET_ADDRESS                                ((ulong) -1)
 118
 119 /*
 120  * BOOTP options
 121  */
 122 #define CONFIG_BOOTP_SUBNETMASK
 123 #define CONFIG_BOOTP_GATEWAY
 124 #define CONFIG_BOOTP_HOSTNAME
 125 #define CONFIG_BOOTP_BOOTPATH
 126 #define CONFIG_BOOTP_BOOTFILESIZE
 127
 128
 129 /*
 130  * The GEN860T network interface uses the on-chip 10/100 FEC with
 131  * an Intel LXT971A PHY connected to the 860T's MII. The PHY's
 132  * MII address is hardwired on the board to zero.
 133  */
 134 #define CONFIG_FEC_ENET
 135 #define CONFIG_SYS_DISCOVER_PHY
 136 #define CONFIG_MII
 137 #define CONFIG_MII_INIT                 1
 138 #define CONFIG_PHY_ADDR                 0
 139
 140 /*
 141  * Set default IP stuff just to get bootstrap entries into the
 142  * environment so that we can source the full default environment.
 143  */
 144 #define CONFIG_ETHADDR                                  9a:52:63:15:85:25
 145 #define CONFIG_SERVERIP                                 10.0.4.201
 146 #define CONFIG_IPADDR                                   10.0.4.111
 147
 148 /*
 149  * This board has a 32 kibibyte EEPROM (Atmel AT24C256) connected to
 150  * the MPC860T I2C interface.
 151  */
 152 #define CONFIG_SYS_I2C_EEPROM_ADDR                              0x50
 153 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS               6               /* 64 byte pages                */
 154 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   12              /* 10 mS w/ 20% margin  */
 155 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN                  2               /* need 16 bit address  */
 156 #define CONFIG_ENV_EEPROM_SIZE                          (32 * 1024)
 157
 158 /*
 159  * Enable I2C and select the hardware/software driver
 160  */
 161 #define CONFIG_HARD_I2C         1               /* CPM based I2C */
 162 #undef  CONFIG_SYS_I2C_SOFT                     /* Bit-banged I2C */
 163
 164 #ifdef CONFIG_HARD_I2C
 165 #define CONFIG_SYS_I2C_SPEED            100000  /* clock speed in Hz */
 166 #define CONFIG_SYS_I2C_SLAVE            0xFE    /* I2C slave address */
 167 #endif
 168
 169 #ifdef CONFIG_SYS_I2C_SOFT
 170 #define CONFIG_SYS_I2C
 171 #define CONFIG_SYS_I2C_SOFT_SPEED       50000
 172 #define CONFIG_SYS_I2C_SOFT_SLAVE       0xFE
 173 #define PB_SCL          0x00000020              /* PB 26 */
 174 #define PB_SDA          0x00000010              /* PB 27 */
 175 #define I2C_INIT        (immr->im_cpm.cp_pbdir |=  PB_SCL)
 176 #define I2C_ACTIVE      (immr->im_cpm.cp_pbdir |=  PB_SDA)
 177 #define I2C_TRISTATE    (immr->im_cpm.cp_pbdir &= ~PB_SDA)
 178 #define I2C_READ        ((immr->im_cpm.cp_pbdat & PB_SDA) != 0)
 179 #define I2C_SDA(bit)    if (bit) \
 180                                 immr->im_cpm.cp_pbdat |=  PB_SDA; \
 181                         else \
 182                                 immr->im_cpm.cp_pbdat &= ~PB_SDA
 183 #define I2C_SCL(bit)    if (bit) \
 184                                 immr->im_cpm.cp_pbdat |=  PB_SCL; \
 185                         else \
 186                                 immr->im_cpm.cp_pbdat &= ~PB_SCL
 187 #define I2C_DELAY       udelay(5) /* 1/4 I2C clock duration */
 188 #endif
 189
 190 /*
 191  * Allow environment overwrites by anyone
 192  */
 193 #define CONFIG_ENV_OVERWRITE
 194
 195 #if !defined(CONFIG_SC)
 196 /*
 197  * The MPC860's internal RTC is horribly broken in rev D masks. Three
 198  * internal MPC860T circuit nodes were inadvertently left floating; this
 199  * causes KAPWR current in power down mode to be three orders of magnitude
 200  * higher than specified in the datasheet (from 10 uA to 10 mA).  No
 201  * reasonable battery can keep that kind RTC running during powerdown for any
 202  * length of time, so we use an external RTC on the I2C bus instead.
 203  */
 204 #define CONFIG_RTC_DS1337
 205 #define CONFIG_SYS_I2C_RTC_ADDR                         0x68
 206
 207 #else
 208 /*
 209  * No external RTC on SC variant, so we're stuck with the internal one.
 210  */
 211 #define CONFIG_RTC_MPC8xx
 212 #endif
 213
 214 /*
 215  * Power On Self Test support
 216  */
 217 #define CONFIG_POST                       ( CONFIG_SYS_POST_CACHE               | \
 218                                                                 CONFIG_SYS_POST_MEMORY          | \
 219                                                                 CONFIG_SYS_POST_CPU             | \
 220                                                                 CONFIG_SYS_POST_UART            | \
 221                                                                 CONFIG_SYS_POST_SPR )
 222
 223
 224 /*
 225  * Command line configuration.
 226  */
 227 #include <config_cmd_default.h>
 228
 229 #define CONFIG_CMD_ASKENV
 230 #define CONFIG_CMD_DHCP
 231 #define CONFIG_CMD_I2C
 232 #define CONFIG_CMD_EEPROM
 233 #define CONFIG_CMD_REGINFO
 234 #define CONFIG_CMD_IMMAP
 235 #define CONFIG_CMD_ELF
 236 #define CONFIG_CMD_DATE
 237 #define CONFIG_CMD_FPGA
 238 #define CONFIG_CMD_MII
 239 #define CONFIG_CMD_BEDBUG
 240
 241 #ifdef CONFIG_POST
 242 #define CONFIG_CMD_DIAG
 243 #endif
 244
 245 /*
 246  * There is no IDE/PCMCIA hardware support on the board.
 247  */
 248 #undef  CONFIG_IDE_PCMCIA
 249 #undef  CONFIG_IDE_LED
 250 #undef  CONFIG_IDE_RESET
 251
 252 /*
 253  * Enable the call to misc_init_r() for miscellaneous platform
 254  * dependent initialization.
 255  */
 256 #define CONFIG_MISC_INIT_R
 257
 258 /*
 259  * Enable call to last_stage_init() so we can twiddle some LEDS :)
 260  */
 261 #define CONFIG_LAST_STAGE_INIT
 262
 263 /*
 264  * Virtex2 FPGA configuration support
 265  */
 266 #define CONFIG_FPGA_COUNT               1
 267 #define CONFIG_FPGA
 268 #define CONFIG_FPGA_XILINX
 269 #define CONFIG_FPGA_VIRTEX2
 270 #define CONFIG_SYS_FPGA_PROG_FEEDBACK
 271
 272 /*
 273  * Verbose help from command monitor.
 274  */
 275 #define CONFIG_SYS_LONGHELP
 276 #if !defined(CONFIG_SC)
 277 #define CONFIG_SYS_PROMPT                       "B2> "
 278 #else
 279 #define CONFIG_SYS_PROMPT                       "SC> "
 280 #endif
 281
 282
 283 /*
 284  * Use the "hush" command parser
 285  */
 286 #define CONFIG_SYS_HUSH_PARSER
 287
 288 /*
 289  * Set buffer size for console I/O
 290  */
 291 #if defined(CONFIG_CMD_KGDB)
 292 #define CONFIG_SYS_CBSIZE                       1024
 293 #else
 294 #define CONFIG_SYS_CBSIZE                       256
 295 #endif
 296
 297 /*
 298  * Print buffer size
 299  */
 300 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
 301
 302 /*
 303  * Maximum number of arguments that a command can accept
 304  */
 305 #define CONFIG_SYS_MAXARGS                      16
 306
 307 /*
 308  * Boot argument buffer size
 309  */
 310 #define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE
 311
 312 /*
 313  * Default memory test range
 314  */
 315 #define CONFIG_SYS_MEMTEST_START        0x0100000
 316 #define CONFIG_SYS_MEMTEST_END          (CONFIG_SYS_MEMTEST_START  + (128 * 1024))
 317
 318 /*
 319  * Select the more full-featured memory test
 320  */
 321 #define CONFIG_SYS_ALT_MEMTEST
 322
 323 /*
 324  * Default load address
 325  */
 326 #define CONFIG_SYS_LOAD_ADDR            0x01000000
 327
 328 /*
 329  * Set decrementer frequency (1 ms ticks)
 330  */
 331 #define CONFIG_SYS_HZ                           1000
 332
 333 /*
 334  * Device memory map (after SDRAM remap to 0x0):
 335  *
 336  * CS           Device                          Base Addr       Size
 337  * ----------------------------------------------------
 338  * CS0*         Flash                           0x40000000      64 M
 339  * CS1*         SDRAM                           0x00000000      16 M
 340  * CS2*         Disk-On-Chip            0x50000000      32 K
 341  * CS3*         FPGA                            0x60000000      64 M
 342  * CS4*         SelectMap                       0x70000000      32 K
 343  * CS5*         Mil-Std 1553 I/F        0x80000000      32 K
 344  * CS6*         Unused
 345  * CS7*         Unused
 346  * IMMR         860T Registers          0xfff00000
 347  */
 348
 349 /*
 350  * Base addresses and block sizes
 351  */
 352 #define CONFIG_SYS_IMMR                 0xFF000000
 353
 354 #define SDRAM_BASE                      0x00000000
 355 #define SDRAM_SIZE                      (64 * 1024 * 1024)
 356
 357 #define FLASH_BASE                      0x40000000
 358 #define FLASH_SIZE                      (16 * 1024 * 1024)
 359
 360 #define DOC_BASE                        0x50000000
 361 #define DOC_SIZE                        (32 * 1024)
 362
 363 #define FPGA_BASE                       0x60000000
 364 #define FPGA_SIZE                       (64 * 1024 * 1024)
 365
 366 #define SELECTMAP_BASE          0x70000000
 367 #define SELECTMAP_SIZE          (32 * 1024)
 368
 369 #define M1553_BASE                      0x80000000
 370 #define M1553_SIZE                      (64 * 1024)
 371
 372 /*
 373  * Definitions for initial stack pointer and data area (in DPRAM)
 374  */
 375 #define CONFIG_SYS_INIT_RAM_ADDR                CONFIG_SYS_IMMR
 376 #define CONFIG_SYS_INIT_RAM_SIZE                0x2F00  /* Size of used area in DPRAM           */
 377 #define CONFIG_SYS_INIT_DATA_SIZE               64      /* # bytes reserved for initial data*/
 378 #define CONFIG_SYS_GBL_DATA_OFFSET              (CONFIG_SYS_INIT_RAM_SIZE - CONFIG_SYS_INIT_DATA_SIZE)
 379 #define CONFIG_SYS_INIT_SP_OFFSET               CONFIG_SYS_GBL_DATA_OFFSET
 380
 381 /*
 382  * Start addresses for the final memory configuration
 383  * (Set up by the startup code)
 384  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 385  */
 386 #define CONFIG_SYS_SDRAM_BASE                   SDRAM_BASE
 387
 388 /*
 389  * FLASH organization
 390  */
 391 #define CONFIG_SYS_FLASH_BASE                   FLASH_BASE
 392 #define CONFIG_SYS_FLASH_SIZE                   FLASH_SIZE
 393 #define CONFIG_SYS_FLASH_SECT_SIZE              (128 * 1024)
 394 #define CONFIG_SYS_MAX_FLASH_BANKS              1
 395 #define CONFIG_SYS_MAX_FLASH_SECT               128
 396
 397 /*
 398  * The timeout values are for an entire chip and are in milliseconds.
 399  * Yes I know that the write timeout is huge.  Accroding to the
 400  * datasheet a single byte takes 630 uS (round to 1 ms) max at worst
 401  * case VCC and temp after 100K programming cycles.  It works out
 402  * to 280 minutes (might as well be forever).
 403  */
 404 #define CONFIG_SYS_FLASH_ERASE_TOUT     (CONFIG_SYS_MAX_FLASH_SECT * 5000)
 405 #define CONFIG_SYS_FLASH_WRITE_TOUT     (CONFIG_SYS_MAX_FLASH_SECT * 128 * 1024 * 1)
 406
 407 /*
 408  * Allow direct writes to FLASH from tftp transfers (** dangerous **)
 409  */
 410 #define CONFIG_SYS_DIRECT_FLASH_TFTP
 411
 412 /*
 413  * Reserve memory for U-Boot.
 414  */
 415 #define CONFIG_SYS_MAX_UBOOT_SECTS              4
 416 #define CONFIG_SYS_MONITOR_LEN                  (CONFIG_SYS_MAX_UBOOT_SECTS * CONFIG_SYS_FLASH_SECT_SIZE)
 417 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SYS_FLASH_BASE
 418
 419 /*
 420  * Select environment placement.  NOTE that u-boot.lds must
 421  * be edited if this is changed!
 422  */
 423 #undef  CONFIG_ENV_IS_IN_FLASH
 424 #define CONFIG_ENV_IS_IN_EEPROM
 425
 426 #if defined(CONFIG_ENV_IS_IN_EEPROM)
 427 #define CONFIG_ENV_SIZE                 (2 * 1024)
 428 #define CONFIG_ENV_OFFSET                       (CONFIG_ENV_EEPROM_SIZE - (8 * 1024))
 429 #else
 430 #define CONFIG_ENV_SIZE                 0x1000
 431 #define CONFIG_ENV_SECT_SIZE            CONFIG_SYS_FLASH_SECT_SIZE
 432
 433 /*
 434  * This ultimately gets passed right into the linker script, so we have to
 435  * use a number :(
 436  */
 437 #define CONFIG_ENV_OFFSET                       0x060000
 438 #endif
 439
 440 /*
 441  * Reserve memory for malloc()
 442  */
 443 #define CONFIG_SYS_MALLOC_LEN           (128 * 1024)
 444
 445 /*
 446  * For booting Linux, the board info and command line data
 447  * have to be in the first 8 MB of memory, since this is
 448  * the maximum mapped by the Linux kernel during initialization.
 449  */
 450 #define CONFIG_SYS_BOOTMAPSZ            (8 * 1024 * 1024)
 451
 452 /*
 453  * Cache Configuration
 454  */
 455 #define CONFIG_SYS_CACHELINE_SIZE               16      /* For all MPC8xx CPUs                          */
 456 #if defined(CONFIG_CMD_KGDB)
 457 #define CONFIG_SYS_CACHELINE_SHIFT              4       /* log base 2 of above value            */
 458 #endif
 459
 460 /*------------------------------------------------------------------------
 461  * SYPCR - System Protection Control                                                    UM 11-9
 462  * -----------------------------------------------------------------------
 463  * SYPCR can only be written once after reset!
 464  *
 465  * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
 466  */
 467 #if defined(CONFIG_WATCHDOG)
 468 #define CONFIG_SYS_SYPCR        ( SYPCR_SWTC    | \
 469                                           SYPCR_BMT     | \
 470                                           SYPCR_BME     | \
 471                                           SYPCR_SWF     | \
 472                                           SYPCR_SWE     | \
 473                                           SYPCR_SWRI    | \
 474                                           SYPCR_SWP               \
 475                                         )
 476 #else
 477 #define CONFIG_SYS_SYPCR        ( SYPCR_SWTC    | \
 478                                           SYPCR_BMT     | \
 479                                           SYPCR_BME     | \
 480                                           SYPCR_SWF     | \
 481                                           SYPCR_SWP               \
 482                                         )
 483 #endif
 484
 485 /*-----------------------------------------------------------------------
 486  * SIUMCR - SIU Module Configuration                                                    UM 11-6
 487  *-----------------------------------------------------------------------
 488  * Set debug pin mux, enable SPKROUT and GPLB5*.
 489  */
 490 #define CONFIG_SYS_SIUMCR       ( SIUMCR_DBGC11 | \
 491                                           SIUMCR_DBPC11 | \
 492                                           SIUMCR_MLRC11 | \
 493                                           SIUMCR_GB5E     \
 494                                         )
 495
 496 /*-----------------------------------------------------------------------
 497  * TBSCR - Time Base Status and Control                                                 UM 11-26
 498  *-----------------------------------------------------------------------
 499  * Clear Reference Interrupt Status, Timebase freeze enabled
 500  */
 501 #define CONFIG_SYS_TBSCR        ( TBSCR_REFA | \
 502                                           TBSCR_REFB | \
 503                                           TBSCR_TBF        \
 504                                         )
 505
 506 /*-----------------------------------------------------------------------
 507  * RTCSC - Real-Time Clock Status and Control Register                  UM 11-27
 508  *-----------------------------------------------------------------------
 509  */
 510 #define CONFIG_SYS_RTCSC        ( RTCSC_SEC     | \
 511                                           RTCSC_ALR | \
 512                                           RTCSC_RTF | \
 513                                           RTCSC_RTE       \
 514                                         )
 515
 516 /*-----------------------------------------------------------------------
 517  * PISCR - Periodic Interrupt Status and Control                                UM 11-31
 518  *-----------------------------------------------------------------------
 519  * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
 520  */
 521 #define CONFIG_SYS_PISCR        ( PISCR_PS              | \
 522                                           PISCR_PITF      \
 523                                         )
 524
 525 /*-----------------------------------------------------------------------
 526  * PLPRCR - PLL, Low-Power, and Reset Control Register                  UM 15-30
 527  *-----------------------------------------------------------------------
 528  * Reset PLL lock status sticky bit, timer expired status bit and timer
 529  * interrupt status bit. Set MF for 1:2:1 mode.
 530  */
 531 #define CONFIG_SYS_PLPRCR       ( ((0x1 << PLPRCR_MF_SHIFT) & PLPRCR_MF_MSK)    | \
 532                                           PLPRCR_SPLSS  | \
 533                                           PLPRCR_TEXPS  | \
 534                                           PLPRCR_TMIST    \
 535                                         )
 536
 537 /*-----------------------------------------------------------------------
 538  * SCCR - System Clock and reset Control Register                               UM 15-27
 539  *-----------------------------------------------------------------------
 540  * Set clock output, timebase and RTC source and divider,
 541  * power management and some other internal clocks
 542  */
 543 #define SCCR_MASK   SCCR_EBDF11
 544
 545 #if !defined(CONFIG_SC)
 546 #define CONFIG_SYS_SCCR ( SCCR_TBS                      |       /* timebase = GCLK/2    */ \
 547                                           SCCR_COM00            |       /* full strength CLKOUT */ \
 548                                           SCCR_DFSYNC00 |       /* SYNCLK / 1 (normal)  */ \
 549                                           SCCR_DFBRG00          |       /* BRGCLK / 1 (normal)  */ \
 550                                           SCCR_DFNL000          | \
 551                                           SCCR_DFNH000            \
 552                                         )
 553 #else
 554 #define CONFIG_SYS_SCCR ( SCCR_TBS                      |       /* timebase = GCLK/2    */ \
 555                                           SCCR_COM00            |       /* full strength CLKOUT */ \
 556                                           SCCR_DFSYNC00 |       /* SYNCLK / 1 (normal)  */ \
 557                                           SCCR_DFBRG00          |       /* BRGCLK / 1 (normal)  */ \
 558                                           SCCR_DFNL000          | \
 559                                           SCCR_DFNH000          | \
 560                                           SCCR_RTDIV            | \
 561                                           SCCR_RTSEL              \
 562                                         )
 563 #endif
 564
 565 /*-----------------------------------------------------------------------
 566  * DER - Debug Enable Register                                                                  UM 37-46
 567  *-----------------------------------------------------------------------
 568  * Mask all events that can cause entry into debug mode
 569  */
 570 #define CONFIG_SYS_DER                          0
 571
 572 /*
 573  * Initialize Memory Controller:
 574  *
 575  * BR0 and OR0 (FLASH memory)
 576  */
 577 #define FLASH_BASE0_PRELIM      FLASH_BASE
 578
 579 /*
 580  * Flash address mask
 581  */
 582 #define CONFIG_SYS_PRELIM_OR_AM 0xfe000000
 583
 584 /*
 585  * FLASH timing:
 586  * 33 Mhz bus with ACS = 11, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 1
 587  */
 588 #define CONFIG_SYS_OR_TIMING_FLASH      ( OR_CSNT_SAM   | \
 589                                                           OR_ACS_DIV2   | \
 590                                                           OR_BI                 | \
 591                                                           OR_SCY_2_CLK  | \
 592                                                           OR_TRLX               | \
 593                                                           OR_EHTR                 \
 594                                                         )
 595
 596 #define CONFIG_SYS_OR0_PRELIM   ( CONFIG_SYS_PRELIM_OR_AM               | \
 597                                                   CONFIG_SYS_OR_TIMING_FLASH      \
 598                                                 )
 599
 600 #define CONFIG_SYS_BR0_PRELIM   ( (FLASH_BASE0_PRELIM & BR_BA_MSK)      | \
 601                                                   BR_MS_GPCM                                            | \
 602                                                   BR_PS_8                                                       | \
 603                                                   BR_V                                                            \
 604                                                 )
 605
 606 /*
 607  * SDRAM configuration
 608  */
 609 #define CONFIG_SYS_OR1_AM       0xfc000000
 610 #define CONFIG_SYS_OR1          ( (CONFIG_SYS_OR1_AM & OR_AM_MSK)       | \
 611                                           OR_CSNT_SAM                             \
 612                                         )
 613
 614 #define CONFIG_SYS_BR1          ( (SDRAM_BASE & BR_BA_MSK)      | \
 615                                           BR_MS_UPMA                            | \
 616                                           BR_PS_32                                      | \
 617                                           BR_V                                            \
 618                                         )
 619
 620 /*
 621  * Refresh rate 7.8 us (= 64 ms / 8K = 31.2 uS quad bursts) for one bank
 622  * of 256 MBit SDRAM
 623  */
 624 #define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16
 625
 626 /*
 627  * Periodic timer for refresh @ 33 MHz system clock
 628  */
 629 #define CONFIG_SYS_MAMR_PTA     64
 630
 631 /*
 632  * MAMR settings for SDRAM
 633  */
 634 #define CONFIG_SYS_MAMR_8COL    ( (CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)       | \
 635                                                   MAMR_PTAE                             | \
 636                                                   MAMR_AMA_TYPE_1                       | \
 637                                                   MAMR_DSA_1_CYCL                       | \
 638                                                   MAMR_G0CLA_A10                        | \
 639                                                   MAMR_RLFA_1X                          | \
 640                                                   MAMR_WLFA_1X                          | \
 641                                                   MAMR_TLFA_4X                            \
 642                                                 )
 643
 644 /*
 645  * CS2* configuration for Disk On Chip:
 646  * 33 MHz bus with TRLX=1, ACS=11, CSNT=1, EBDF=1, SCY=2, EHTR=1,
 647  * no burst.
 648  */
 649 #define CONFIG_SYS_OR2_PRELIM   ( (0xffff0000 & OR_AM_MSK)      | \
 650                                                   OR_CSNT_SAM                           | \
 651                                                   OR_ACS_DIV2                           | \
 652                                                   OR_BI                                         | \
 653                                                   OR_SCY_2_CLK                          | \
 654                                                   OR_TRLX                                       | \
 655                                                   OR_EHTR                                         \
 656                                                 )
 657
 658 #define CONFIG_SYS_BR2_PRELIM   ( (DOC_BASE & BR_BA_MSK)        | \
 659                                                   BR_PS_8                                       | \
 660                                                   BR_MS_GPCM                            | \
 661                                                   BR_V                                            \
 662                                                 )
 663
 664 /*
 665  * CS3* configuration for FPGA:
 666  * 33 MHz bus with SCY=15, no burst.
 667  * The FPGA uses TA and TEA to terminate bus cycles, but we
 668  * clear SETA and set the cycle length to a large number so that
 669  * the cycle will still complete even if there is a configuration
 670  * error that prevents TA from asserting on FPGA accesss.
 671  */
 672 #define CONFIG_SYS_OR3_PRELIM   ( (0xfc000000 & OR_AM_MSK)  | \
 673                                                   OR_SCY_15_CLK                         | \
 674                                                   OR_BI                                   \
 675                                                 )
 676
 677 #define CONFIG_SYS_BR3_PRELIM   ( (FPGA_BASE & BR_BA_MSK)       | \
 678                                                   BR_PS_32                                      | \
 679                                                   BR_MS_GPCM                            | \
 680                                                   BR_V                                            \
 681                                                 )
 682 /*
 683  * CS4* configuration for FPGA SelectMap configuration interface.
 684  * 33 MHz bus, UPMB, no burst. Do not assert GPLB5 on falling edge
 685  * of GCLK1_50
 686  */
 687 #define CONFIG_SYS_OR4_PRELIM   ( (0xffff0000 & OR_AM_MSK)      | \
 688                                                   OR_G5LS                                               | \
 689                                                   OR_BI                                                   \
 690                                                 )
 691
 692 #define CONFIG_SYS_BR4_PRELIM   ( (SELECTMAP_BASE & BR_BA_MSK)  | \
 693                                                   BR_PS_8                                               | \
 694                                                   BR_MS_UPMB                                    | \
 695                                                   BR_V                                                    \
 696                                                 )
 697
 698 /*
 699  * CS5* configuration for Mil-Std 1553 databus interface.
 700  * 33 MHz bus, GPCM, no burst.
 701  * The 1553 interface  uses TA and TEA to terminate bus cycles,
 702  * but we clear SETA and set the cycle length to a large number so that
 703  * the cycle will still complete even if there is a configuration
 704  * error that prevents TA from asserting on FPGA accesss.
 705  */
 706 #define CONFIG_SYS_OR5_PRELIM   ( (0xffff0000 & OR_AM_MSK)  | \
 707                                                   OR_SCY_15_CLK                         | \
 708                                                   OR_EHTR                                       | \
 709                                                   OR_TRLX                                       | \
 710                                                   OR_CSNT_SAM                           | \
 711                                                   OR_BI                                           \
 712                                                 )
 713
 714 #define CONFIG_SYS_BR5_PRELIM   ( (M1553_BASE & BR_BA_MSK)      | \
 715                                                   BR_PS_16                                      | \
 716                                                   BR_MS_GPCM                            | \
 717                                                   BR_V                                            \
 718                                                 )
 719
 720 /*
 721  * FEC interrupt assignment
 722  */
 723 #define FEC_INTERRUPT   SIU_LEVEL1
 724
 725 /*
 726  * Sanity checks
 727  */
 728 #if defined(CONFIG_SCC1_ENET) && defined(CONFIG_FEC_ENET)
 729 #error Both CONFIG_SCC1_ENET and CONFIG_FEC_ENET configured
 730 #endif
 731
 732 #endif  /* __CONFIG_GEN860T_H */