include/configs/GEN860T.h

   1 /*
   2  * (C) Copyright 2000
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  * Keith Outwater, keith_outwater@mvis.com
   5  *
   6  * SPDX-License-Identifier:     GPL-2.0+
   7  */
   8
   9 /*
  10  * board/config_GEN860T.h - board specific configuration options
  11  */
  12
  13 #ifndef __CONFIG_GEN860T_H
  14 #define __CONFIG_H
  15
  16 /*
  17  * High Level Configuration Options
  18  */
  19 #define CONFIG_MPC860
  20 #define CONFIG_GEN860T
  21
  22 #define CONFIG_SYS_TEXT_BASE            0x40000000
  23
  24 /*
  25  * Identify the board
  26  */
  27 #if !defined(CONFIG_SC)
  28 #define CONFIG_IDENT_STRING             " B2"
  29 #else
  30 #define CONFIG_IDENT_STRING             " SC"
  31 #endif
  32
  33 /*
  34  * Don't depend on the RTC clock to determine clock frequency -
  35  * the 860's internal rtc uses a 32.768 KHz clock which is
  36  * generated by the DS1337 - and the DS1337 clock can be turned off.
  37  */
  38 #if !defined(CONFIG_SC)
  39 #define CONFIG_8xx_GCLK_FREQ            66600000
  40 #else
  41 #define CONFIG_8xx_GCLK_FREQ            48000000
  42 #endif
  43
  44 /*
  45  * The RS-232 console port is on SMC1
  46  */
  47 #define CONFIG_8xx_CONS_SMC1
  48 #define CONFIG_BAUDRATE                 38400
  49
  50 /*
  51  * Print console information
  52  */
  53 #undef   CONFIG_SYS_CONSOLE_INFO_QUIET
  54
  55 /*
  56  * Set the autoboot delay in seconds.  A delay of -1 disables autoboot
  57  */
  58 #define CONFIG_BOOTDELAY                                5
  59
  60 /*
  61  * Pass the clock frequency to the Linux kernel in units of MHz
  62  */
  63 #define CONFIG_CLOCKS_IN_MHZ
  64
  65 #define CONFIG_PREBOOT          \
  66         "echo;echo"
  67
  68 #undef  CONFIG_BOOTARGS
  69 #define CONFIG_BOOTCOMMAND      \
  70         "bootp;" \
  71         "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
  72         "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \
  73         "bootm"
  74
  75 /*
  76  * Turn off echo for serial download by default.  Allow baud rate to be changed
  77  * for downloads
  78  */
  79 #undef  CONFIG_LOADS_ECHO
  80 #define CONFIG_SYS_LOADS_BAUD_CHANGE
  81
  82 /*
  83  * Turn off the watchdog timer
  84  */
  85 #undef  CONFIG_WATCHDOG
  86
  87 /*
  88  * Do not reboot if a panic occurs
  89  */
  90 #define CONFIG_PANIC_HANG
  91
  92 /*
  93  * Enable the status LED
  94  */
  95 #define CONFIG_STATUS_LED
  96
  97 /*
  98  * Reset address. We pick an address such that when an instruction
  99  * is executed at that address, a machine check exception occurs
 100  */
 101 #define CONFIG_SYS_RESET_ADDRESS                                ((ulong) -1)
 102
 103 /*
 104  * BOOTP options
 105  */
 106 #define CONFIG_BOOTP_SUBNETMASK
 107 #define CONFIG_BOOTP_GATEWAY
 108 #define CONFIG_BOOTP_HOSTNAME
 109 #define CONFIG_BOOTP_BOOTPATH
 110 #define CONFIG_BOOTP_BOOTFILESIZE
 111
 112
 113 /*
 114  * The GEN860T network interface uses the on-chip 10/100 FEC with
 115  * an Intel LXT971A PHY connected to the 860T's MII. The PHY's
 116  * MII address is hardwired on the board to zero.
 117  */
 118 #define CONFIG_FEC_ENET
 119 #define CONFIG_SYS_DISCOVER_PHY
 120 #define CONFIG_MII
 121 #define CONFIG_MII_INIT                 1
 122 #define CONFIG_PHY_ADDR                 0
 123
 124 /*
 125  * Set default IP stuff just to get bootstrap entries into the
 126  * environment so that we can source the full default environment.
 127  */
 128 #define CONFIG_ETHADDR                                  9a:52:63:15:85:25
 129 #define CONFIG_SERVERIP                                 10.0.4.201
 130 #define CONFIG_IPADDR                                   10.0.4.111
 131
 132 /*
 133  * This board has a 32 kibibyte EEPROM (Atmel AT24C256) connected to
 134  * the MPC860T I2C interface.
 135  */
 136 #define CONFIG_SYS_I2C_EEPROM_ADDR                              0x50
 137 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS               6               /* 64 byte pages                */
 138 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   12              /* 10 mS w/ 20% margin  */
 139 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN                  2               /* need 16 bit address  */
 140 #define CONFIG_ENV_EEPROM_SIZE                          (32 * 1024)
 141
 142 /*
 143  * Enable I2C and select the hardware/software driver
 144  */
 145 #define CONFIG_HARD_I2C         1                               /* CPM based I2C                        */
 146 #undef  CONFIG_SOFT_I2C                                         /* Bit-banged I2C                       */
 147
 148 #ifdef CONFIG_HARD_I2C
 149 #define CONFIG_SYS_I2C_SPEED            100000                  /* clock speed in Hz            */
 150 #define CONFIG_SYS_I2C_SLAVE            0xFE                    /* I2C slave address            */
 151 #endif
 152
 153 #ifdef CONFIG_SOFT_I2C
 154 #define PB_SCL                          0x00000020              /* PB 26                                        */
 155 #define PB_SDA                          0x00000010              /* PB 27                                        */
 156 #define I2C_INIT                        (immr->im_cpm.cp_pbdir |=  PB_SCL)
 157 #define I2C_ACTIVE                      (immr->im_cpm.cp_pbdir |=  PB_SDA)
 158 #define I2C_TRISTATE            (immr->im_cpm.cp_pbdir &= ~PB_SDA)
 159 #define I2C_READ                        ((immr->im_cpm.cp_pbdat & PB_SDA) != 0)
 160 #define I2C_SDA(bit)            if(bit) immr->im_cpm.cp_pbdat |=  PB_SDA; \
 161                                                                 else    immr->im_cpm.cp_pbdat &= ~PB_SDA
 162 #define I2C_SCL(bit)            if(bit) immr->im_cpm.cp_pbdat |=  PB_SCL; \
 163                                                                 else    immr->im_cpm.cp_pbdat &= ~PB_SCL
 164 #define I2C_DELAY                       udelay(5)               /* 1/4 I2C clock duration       */
 165 #endif
 166
 167 /*
 168  * Allow environment overwrites by anyone
 169  */
 170 #define CONFIG_ENV_OVERWRITE
 171
 172 #if !defined(CONFIG_SC)
 173 /*
 174  * The MPC860's internal RTC is horribly broken in rev D masks. Three
 175  * internal MPC860T circuit nodes were inadvertently left floating; this
 176  * causes KAPWR current in power down mode to be three orders of magnitude
 177  * higher than specified in the datasheet (from 10 uA to 10 mA).  No
 178  * reasonable battery can keep that kind RTC running during powerdown for any
 179  * length of time, so we use an external RTC on the I2C bus instead.
 180  */
 181 #define CONFIG_RTC_DS1337
 182 #define CONFIG_SYS_I2C_RTC_ADDR                         0x68
 183
 184 #else
 185 /*
 186  * No external RTC on SC variant, so we're stuck with the internal one.
 187  */
 188 #define CONFIG_RTC_MPC8xx
 189 #endif
 190
 191 /*
 192  * Power On Self Test support
 193  */
 194 #define CONFIG_POST                       ( CONFIG_SYS_POST_CACHE               | \
 195                                                                 CONFIG_SYS_POST_MEMORY          | \
 196                                                                 CONFIG_SYS_POST_CPU             | \
 197                                                                 CONFIG_SYS_POST_UART            | \
 198                                                                 CONFIG_SYS_POST_SPR )
 199
 200
 201 /*
 202  * Command line configuration.
 203  */
 204 #include <config_cmd_default.h>
 205
 206 #define CONFIG_CMD_ASKENV
 207 #define CONFIG_CMD_DHCP
 208 #define CONFIG_CMD_I2C
 209 #define CONFIG_CMD_EEPROM
 210 #define CONFIG_CMD_REGINFO
 211 #define CONFIG_CMD_IMMAP
 212 #define CONFIG_CMD_ELF
 213 #define CONFIG_CMD_DATE
 214 #define CONFIG_CMD_FPGA
 215 #define CONFIG_CMD_MII
 216 #define CONFIG_CMD_BEDBUG
 217
 218 #ifdef CONFIG_POST
 219 #define CONFIG_CMD_DIAG
 220 #endif
 221
 222 /*
 223  * There is no IDE/PCMCIA hardware support on the board.
 224  */
 225 #undef  CONFIG_IDE_PCMCIA
 226 #undef  CONFIG_IDE_LED
 227 #undef  CONFIG_IDE_RESET
 228
 229 /*
 230  * Enable the call to misc_init_r() for miscellaneous platform
 231  * dependent initialization.
 232  */
 233 #define CONFIG_MISC_INIT_R
 234
 235 /*
 236  * Enable call to last_stage_init() so we can twiddle some LEDS :)
 237  */
 238 #define CONFIG_LAST_STAGE_INIT
 239
 240 /*
 241  * Virtex2 FPGA configuration support
 242  */
 243 #define CONFIG_FPGA_COUNT               1
 244 #define CONFIG_FPGA
 245 #define CONFIG_FPGA_XILINX
 246 #define CONFIG_FPGA_VIRTEX2
 247 #define CONFIG_SYS_FPGA_PROG_FEEDBACK
 248
 249 /*
 250  * Verbose help from command monitor.
 251  */
 252 #define CONFIG_SYS_LONGHELP
 253 #if !defined(CONFIG_SC)
 254 #define CONFIG_SYS_PROMPT                       "B2> "
 255 #else
 256 #define CONFIG_SYS_PROMPT                       "SC> "
 257 #endif
 258
 259
 260 /*
 261  * Use the "hush" command parser
 262  */
 263 #define CONFIG_SYS_HUSH_PARSER
 264
 265 /*
 266  * Set buffer size for console I/O
 267  */
 268 #if defined(CONFIG_CMD_KGDB)
 269 #define CONFIG_SYS_CBSIZE                       1024
 270 #else
 271 #define CONFIG_SYS_CBSIZE                       256
 272 #endif
 273
 274 /*
 275  * Print buffer size
 276  */
 277 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
 278
 279 /*
 280  * Maximum number of arguments that a command can accept
 281  */
 282 #define CONFIG_SYS_MAXARGS                      16
 283
 284 /*
 285  * Boot argument buffer size
 286  */
 287 #define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE
 288
 289 /*
 290  * Default memory test range
 291  */
 292 #define CONFIG_SYS_MEMTEST_START        0x0100000
 293 #define CONFIG_SYS_MEMTEST_END          (CONFIG_SYS_MEMTEST_START  + (128 * 1024))
 294
 295 /*
 296  * Select the more full-featured memory test
 297  */
 298 #define CONFIG_SYS_ALT_MEMTEST
 299
 300 /*
 301  * Default load address
 302  */
 303 #define CONFIG_SYS_LOAD_ADDR            0x01000000
 304
 305 /*
 306  * Set decrementer frequency (1 ms ticks)
 307  */
 308 #define CONFIG_SYS_HZ                           1000
 309
 310 /*
 311  * Device memory map (after SDRAM remap to 0x0):
 312  *
 313  * CS           Device                          Base Addr       Size
 314  * ----------------------------------------------------
 315  * CS0*         Flash                           0x40000000      64 M
 316  * CS1*         SDRAM                           0x00000000      16 M
 317  * CS2*         Disk-On-Chip            0x50000000      32 K
 318  * CS3*         FPGA                            0x60000000      64 M
 319  * CS4*         SelectMap                       0x70000000      32 K
 320  * CS5*         Mil-Std 1553 I/F        0x80000000      32 K
 321  * CS6*         Unused
 322  * CS7*         Unused
 323  * IMMR         860T Registers          0xfff00000
 324  */
 325
 326 /*
 327  * Base addresses and block sizes
 328  */
 329 #define CONFIG_SYS_IMMR                 0xFF000000
 330
 331 #define SDRAM_BASE                      0x00000000
 332 #define SDRAM_SIZE                      (64 * 1024 * 1024)
 333
 334 #define FLASH_BASE                      0x40000000
 335 #define FLASH_SIZE                      (16 * 1024 * 1024)
 336
 337 #define DOC_BASE                        0x50000000
 338 #define DOC_SIZE                        (32 * 1024)
 339
 340 #define FPGA_BASE                       0x60000000
 341 #define FPGA_SIZE                       (64 * 1024 * 1024)
 342
 343 #define SELECTMAP_BASE          0x70000000
 344 #define SELECTMAP_SIZE          (32 * 1024)
 345
 346 #define M1553_BASE                      0x80000000
 347 #define M1553_SIZE                      (64 * 1024)
 348
 349 /*
 350  * Definitions for initial stack pointer and data area (in DPRAM)
 351  */
 352 #define CONFIG_SYS_INIT_RAM_ADDR                CONFIG_SYS_IMMR
 353 #define CONFIG_SYS_INIT_RAM_SIZE                0x2F00  /* Size of used area in DPRAM           */
 354 #define CONFIG_SYS_INIT_DATA_SIZE               64      /* # bytes reserved for initial data*/
 355 #define CONFIG_SYS_GBL_DATA_OFFSET              (CONFIG_SYS_INIT_RAM_SIZE - CONFIG_SYS_INIT_DATA_SIZE)
 356 #define CONFIG_SYS_INIT_SP_OFFSET               CONFIG_SYS_GBL_DATA_OFFSET
 357
 358 /*
 359  * Start addresses for the final memory configuration
 360  * (Set up by the startup code)
 361  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 362  */
 363 #define CONFIG_SYS_SDRAM_BASE                   SDRAM_BASE
 364
 365 /*
 366  * FLASH organization
 367  */
 368 #define CONFIG_SYS_FLASH_BASE                   FLASH_BASE
 369 #define CONFIG_SYS_FLASH_SIZE                   FLASH_SIZE
 370 #define CONFIG_SYS_FLASH_SECT_SIZE              (128 * 1024)
 371 #define CONFIG_SYS_MAX_FLASH_BANKS              1
 372 #define CONFIG_SYS_MAX_FLASH_SECT               128
 373
 374 /*
 375  * The timeout values are for an entire chip and are in milliseconds.
 376  * Yes I know that the write timeout is huge.  Accroding to the
 377  * datasheet a single byte takes 630 uS (round to 1 ms) max at worst
 378  * case VCC and temp after 100K programming cycles.  It works out
 379  * to 280 minutes (might as well be forever).
 380  */
 381 #define CONFIG_SYS_FLASH_ERASE_TOUT     (CONFIG_SYS_MAX_FLASH_SECT * 5000)
 382 #define CONFIG_SYS_FLASH_WRITE_TOUT     (CONFIG_SYS_MAX_FLASH_SECT * 128 * 1024 * 1)
 383
 384 /*
 385  * Allow direct writes to FLASH from tftp transfers (** dangerous **)
 386  */
 387 #define CONFIG_SYS_DIRECT_FLASH_TFTP
 388
 389 /*
 390  * Reserve memory for U-Boot.
 391  */
 392 #define CONFIG_SYS_MAX_UBOOT_SECTS              4
 393 #define CONFIG_SYS_MONITOR_LEN                  (CONFIG_SYS_MAX_UBOOT_SECTS * CONFIG_SYS_FLASH_SECT_SIZE)
 394 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SYS_FLASH_BASE
 395
 396 /*
 397  * Select environment placement.  NOTE that u-boot.lds must
 398  * be edited if this is changed!
 399  */
 400 #undef  CONFIG_ENV_IS_IN_FLASH
 401 #define CONFIG_ENV_IS_IN_EEPROM
 402
 403 #if defined(CONFIG_ENV_IS_IN_EEPROM)
 404 #define CONFIG_ENV_SIZE                 (2 * 1024)
 405 #define CONFIG_ENV_OFFSET                       (CONFIG_ENV_EEPROM_SIZE - (8 * 1024))
 406 #else
 407 #define CONFIG_ENV_SIZE                 0x1000
 408 #define CONFIG_ENV_SECT_SIZE            CONFIG_SYS_FLASH_SECT_SIZE
 409
 410 /*
 411  * This ultimately gets passed right into the linker script, so we have to
 412  * use a number :(
 413  */
 414 #define CONFIG_ENV_OFFSET                       0x060000
 415 #endif
 416
 417 /*
 418  * Reserve memory for malloc()
 419  */
 420 #define CONFIG_SYS_MALLOC_LEN           (128 * 1024)
 421
 422 /*
 423  * For booting Linux, the board info and command line data
 424  * have to be in the first 8 MB of memory, since this is
 425  * the maximum mapped by the Linux kernel during initialization.
 426  */
 427 #define CONFIG_SYS_BOOTMAPSZ            (8 * 1024 * 1024)
 428
 429 /*
 430  * Cache Configuration
 431  */
 432 #define CONFIG_SYS_CACHELINE_SIZE               16      /* For all MPC8xx CPUs                          */
 433 #if defined(CONFIG_CMD_KGDB)
 434 #define CONFIG_SYS_CACHELINE_SHIFT              4       /* log base 2 of above value            */
 435 #endif
 436
 437 /*------------------------------------------------------------------------
 438  * SYPCR - System Protection Control                                                    UM 11-9
 439  * -----------------------------------------------------------------------
 440  * SYPCR can only be written once after reset!
 441  *
 442  * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
 443  */
 444 #if defined(CONFIG_WATCHDOG)
 445 #define CONFIG_SYS_SYPCR        ( SYPCR_SWTC    | \
 446                                           SYPCR_BMT     | \
 447                                           SYPCR_BME     | \
 448                                           SYPCR_SWF     | \
 449                                           SYPCR_SWE     | \
 450                                           SYPCR_SWRI    | \
 451                                           SYPCR_SWP               \
 452                                         )
 453 #else
 454 #define CONFIG_SYS_SYPCR        ( SYPCR_SWTC    | \
 455                                           SYPCR_BMT     | \
 456                                           SYPCR_BME     | \
 457                                           SYPCR_SWF     | \
 458                                           SYPCR_SWP               \
 459                                         )
 460 #endif
 461
 462 /*-----------------------------------------------------------------------
 463  * SIUMCR - SIU Module Configuration                                                    UM 11-6
 464  *-----------------------------------------------------------------------
 465  * Set debug pin mux, enable SPKROUT and GPLB5*.
 466  */
 467 #define CONFIG_SYS_SIUMCR       ( SIUMCR_DBGC11 | \
 468                                           SIUMCR_DBPC11 | \
 469                                           SIUMCR_MLRC11 | \
 470                                           SIUMCR_GB5E     \
 471                                         )
 472
 473 /*-----------------------------------------------------------------------
 474  * TBSCR - Time Base Status and Control                                                 UM 11-26
 475  *-----------------------------------------------------------------------
 476  * Clear Reference Interrupt Status, Timebase freeze enabled
 477  */
 478 #define CONFIG_SYS_TBSCR        ( TBSCR_REFA | \
 479                                           TBSCR_REFB | \
 480                                           TBSCR_TBF        \
 481                                         )
 482
 483 /*-----------------------------------------------------------------------
 484  * RTCSC - Real-Time Clock Status and Control Register                  UM 11-27
 485  *-----------------------------------------------------------------------
 486  */
 487 #define CONFIG_SYS_RTCSC        ( RTCSC_SEC     | \
 488                                           RTCSC_ALR | \
 489                                           RTCSC_RTF | \
 490                                           RTCSC_RTE       \
 491                                         )
 492
 493 /*-----------------------------------------------------------------------
 494  * PISCR - Periodic Interrupt Status and Control                                UM 11-31
 495  *-----------------------------------------------------------------------
 496  * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
 497  */
 498 #define CONFIG_SYS_PISCR        ( PISCR_PS              | \
 499                                           PISCR_PITF      \
 500                                         )
 501
 502 /*-----------------------------------------------------------------------
 503  * PLPRCR - PLL, Low-Power, and Reset Control Register                  UM 15-30
 504  *-----------------------------------------------------------------------
 505  * Reset PLL lock status sticky bit, timer expired status bit and timer
 506  * interrupt status bit. Set MF for 1:2:1 mode.
 507  */
 508 #define CONFIG_SYS_PLPRCR       ( ((0x1 << PLPRCR_MF_SHIFT) & PLPRCR_MF_MSK)    | \
 509                                           PLPRCR_SPLSS  | \
 510                                           PLPRCR_TEXPS  | \
 511                                           PLPRCR_TMIST    \
 512                                         )
 513
 514 /*-----------------------------------------------------------------------
 515  * SCCR - System Clock and reset Control Register                               UM 15-27
 516  *-----------------------------------------------------------------------
 517  * Set clock output, timebase and RTC source and divider,
 518  * power management and some other internal clocks
 519  */
 520 #define SCCR_MASK   SCCR_EBDF11
 521
 522 #if !defined(CONFIG_SC)
 523 #define CONFIG_SYS_SCCR ( SCCR_TBS                      |       /* timebase = GCLK/2    */ \
 524                                           SCCR_COM00            |       /* full strength CLKOUT */ \
 525                                           SCCR_DFSYNC00 |       /* SYNCLK / 1 (normal)  */ \
 526                                           SCCR_DFBRG00          |       /* BRGCLK / 1 (normal)  */ \
 527                                           SCCR_DFNL000          | \
 528                                           SCCR_DFNH000            \
 529                                         )
 530 #else
 531 #define CONFIG_SYS_SCCR ( SCCR_TBS                      |       /* timebase = GCLK/2    */ \
 532                                           SCCR_COM00            |       /* full strength CLKOUT */ \
 533                                           SCCR_DFSYNC00 |       /* SYNCLK / 1 (normal)  */ \
 534                                           SCCR_DFBRG00          |       /* BRGCLK / 1 (normal)  */ \
 535                                           SCCR_DFNL000          | \
 536                                           SCCR_DFNH000          | \
 537                                           SCCR_RTDIV            | \
 538                                           SCCR_RTSEL              \
 539                                         )
 540 #endif
 541
 542 /*-----------------------------------------------------------------------
 543  * DER - Debug Enable Register                                                                  UM 37-46
 544  *-----------------------------------------------------------------------
 545  * Mask all events that can cause entry into debug mode
 546  */
 547 #define CONFIG_SYS_DER                          0
 548
 549 /*
 550  * Initialize Memory Controller:
 551  *
 552  * BR0 and OR0 (FLASH memory)
 553  */
 554 #define FLASH_BASE0_PRELIM      FLASH_BASE
 555
 556 /*
 557  * Flash address mask
 558  */
 559 #define CONFIG_SYS_PRELIM_OR_AM 0xfe000000
 560
 561 /*
 562  * FLASH timing:
 563  * 33 Mhz bus with ACS = 11, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 1
 564  */
 565 #define CONFIG_SYS_OR_TIMING_FLASH      ( OR_CSNT_SAM   | \
 566                                                           OR_ACS_DIV2   | \
 567                                                           OR_BI                 | \
 568                                                           OR_SCY_2_CLK  | \
 569                                                           OR_TRLX               | \
 570                                                           OR_EHTR                 \
 571                                                         )
 572
 573 #define CONFIG_SYS_OR0_PRELIM   ( CONFIG_SYS_PRELIM_OR_AM               | \
 574                                                   CONFIG_SYS_OR_TIMING_FLASH      \
 575                                                 )
 576
 577 #define CONFIG_SYS_BR0_PRELIM   ( (FLASH_BASE0_PRELIM & BR_BA_MSK)      | \
 578                                                   BR_MS_GPCM                                            | \
 579                                                   BR_PS_8                                                       | \
 580                                                   BR_V                                                            \
 581                                                 )
 582
 583 /*
 584  * SDRAM configuration
 585  */
 586 #define CONFIG_SYS_OR1_AM       0xfc000000
 587 #define CONFIG_SYS_OR1          ( (CONFIG_SYS_OR1_AM & OR_AM_MSK)       | \
 588                                           OR_CSNT_SAM                             \
 589                                         )
 590
 591 #define CONFIG_SYS_BR1          ( (SDRAM_BASE & BR_BA_MSK)      | \
 592                                           BR_MS_UPMA                            | \
 593                                           BR_PS_32                                      | \
 594                                           BR_V                                            \
 595                                         )
 596
 597 /*
 598  * Refresh rate 7.8 us (= 64 ms / 8K = 31.2 uS quad bursts) for one bank
 599  * of 256 MBit SDRAM
 600  */
 601 #define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16
 602
 603 /*
 604  * Periodic timer for refresh @ 33 MHz system clock
 605  */
 606 #define CONFIG_SYS_MAMR_PTA     64
 607
 608 /*
 609  * MAMR settings for SDRAM
 610  */
 611 #define CONFIG_SYS_MAMR_8COL    ( (CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)       | \
 612                                                   MAMR_PTAE                             | \
 613                                                   MAMR_AMA_TYPE_1                       | \
 614                                                   MAMR_DSA_1_CYCL                       | \
 615                                                   MAMR_G0CLA_A10                        | \
 616                                                   MAMR_RLFA_1X                          | \
 617                                                   MAMR_WLFA_1X                          | \
 618                                                   MAMR_TLFA_4X                            \
 619                                                 )
 620
 621 /*
 622  * CS2* configuration for Disk On Chip:
 623  * 33 MHz bus with TRLX=1, ACS=11, CSNT=1, EBDF=1, SCY=2, EHTR=1,
 624  * no burst.
 625  */
 626 #define CONFIG_SYS_OR2_PRELIM   ( (0xffff0000 & OR_AM_MSK)      | \
 627                                                   OR_CSNT_SAM                           | \
 628                                                   OR_ACS_DIV2                           | \
 629                                                   OR_BI                                         | \
 630                                                   OR_SCY_2_CLK                          | \
 631                                                   OR_TRLX                                       | \
 632                                                   OR_EHTR                                         \
 633                                                 )
 634
 635 #define CONFIG_SYS_BR2_PRELIM   ( (DOC_BASE & BR_BA_MSK)        | \
 636                                                   BR_PS_8                                       | \
 637                                                   BR_MS_GPCM                            | \
 638                                                   BR_V                                            \
 639                                                 )
 640
 641 /*
 642  * CS3* configuration for FPGA:
 643  * 33 MHz bus with SCY=15, no burst.
 644  * The FPGA uses TA and TEA to terminate bus cycles, but we
 645  * clear SETA and set the cycle length to a large number so that
 646  * the cycle will still complete even if there is a configuration
 647  * error that prevents TA from asserting on FPGA accesss.
 648  */
 649 #define CONFIG_SYS_OR3_PRELIM   ( (0xfc000000 & OR_AM_MSK)  | \
 650                                                   OR_SCY_15_CLK                         | \
 651                                                   OR_BI                                   \
 652                                                 )
 653
 654 #define CONFIG_SYS_BR3_PRELIM   ( (FPGA_BASE & BR_BA_MSK)       | \
 655                                                   BR_PS_32                                      | \
 656                                                   BR_MS_GPCM                            | \
 657                                                   BR_V                                            \
 658                                                 )
 659 /*
 660  * CS4* configuration for FPGA SelectMap configuration interface.
 661  * 33 MHz bus, UPMB, no burst. Do not assert GPLB5 on falling edge
 662  * of GCLK1_50
 663  */
 664 #define CONFIG_SYS_OR4_PRELIM   ( (0xffff0000 & OR_AM_MSK)      | \
 665                                                   OR_G5LS                                               | \
 666                                                   OR_BI                                                   \
 667                                                 )
 668
 669 #define CONFIG_SYS_BR4_PRELIM   ( (SELECTMAP_BASE & BR_BA_MSK)  | \
 670                                                   BR_PS_8                                               | \
 671                                                   BR_MS_UPMB                                    | \
 672                                                   BR_V                                                    \
 673                                                 )
 674
 675 /*
 676  * CS5* configuration for Mil-Std 1553 databus interface.
 677  * 33 MHz bus, GPCM, no burst.
 678  * The 1553 interface  uses TA and TEA to terminate bus cycles,
 679  * but we clear SETA and set the cycle length to a large number so that
 680  * the cycle will still complete even if there is a configuration
 681  * error that prevents TA from asserting on FPGA accesss.
 682  */
 683 #define CONFIG_SYS_OR5_PRELIM   ( (0xffff0000 & OR_AM_MSK)  | \
 684                                                   OR_SCY_15_CLK                         | \
 685                                                   OR_EHTR                                       | \
 686                                                   OR_TRLX                                       | \
 687                                                   OR_CSNT_SAM                           | \
 688                                                   OR_BI                                           \
 689                                                 )
 690
 691 #define CONFIG_SYS_BR5_PRELIM   ( (M1553_BASE & BR_BA_MSK)      | \
 692                                                   BR_PS_16                                      | \
 693                                                   BR_MS_GPCM                            | \
 694                                                   BR_V                                            \
 695                                                 )
 696
 697 /*
 698  * FEC interrupt assignment
 699  */
 700 #define FEC_INTERRUPT   SIU_LEVEL1
 701
 702 /*
 703  * Sanity checks
 704  */
 705 #if defined(CONFIG_SCC1_ENET) && defined(CONFIG_FEC_ENET)
 706 #error Both CONFIG_SCC1_ENET and CONFIG_FEC_ENET configured
 707 #endif
 708
 709 #endif  /* __CONFIG_GEN860T_H */