3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 * board/config.h - configuration options, board specific
32 * High Level Configuration Options
36 #define CONFIG_MPC823 1 /* This is a MPC823 CPU */
37 #define CONFIG_FLAGADM 1 /* ...on a FLAGA DM */
38 #define CONFIG_8xx_GCLK_FREQ 48000000 /*48MHz*/
40 #undef CONFIG_8xx_CONS_SMC1 /* Console is on SMC1 */
41 #define CONFIG_8xx_CONS_SMC2 1
42 #undef CONFIG_8xx_CONS_NONE
44 #define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */
45 #define CONFIG_BOOTDELAY 3 /* autoboot after 5 seconds */
47 #undef CONFIG_CLOCKS_IN_MHZ
50 #define CONFIG_BOOTARGS "root=/dev/nfs rw ip=bootp"
51 #define CONFIG_BOOTCOMMAND \
52 "setenv bootargs root=/dev/ram ip=off panic=1;" \
53 "bootm 40040000 400e0000"
55 #define CONFIG_BOOTARGS "root=/dev/nfs rw ip=bootp panic=1"
56 #define CONFIG_BOOTCOMMAND "bootp 0x400000; bootm 0x400000"
59 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
60 #undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */
62 /*#define CONFIG_WATCHDOG*/ /* watchdog enabled */
63 #undef CONFIG_WATCHDOG /* watchdog disabled */
65 #define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
67 #define CONFIG_COMMANDS (CFG_CMD_BDI | CFG_CMD_IMI | CFG_CMD_CACHE | \
68 CFG_CMD_MEMORY | CFG_CMD_FLASH | CFG_CMD_LOADB | CFG_CMD_LOADS | \
69 CFG_CMD_ENV | CFG_CMD_REGINFO | CFG_CMD_IMMAP | CFG_CMD_NET)
71 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
72 #include <cmd_confdefs.h>
75 * Miscellaneous configurable options
77 #define CFG_LONGHELP /* undef to save memory */
78 #define CFG_PROMPT "EEG> " /* Monitor Command Prompt */
79 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
80 #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
82 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
84 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
85 #define CFG_MAXARGS 16 /* max number of command args */
86 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
88 #define CFG_MEMTEST_START 0x0100000 /* memtest works on */
89 #define CFG_MEMTEST_END 0x0f00000 /* 1 ... 15 MB in DRAM */
91 #define CFG_LOAD_ADDR 0x40040000 /* default load address */
93 #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
95 #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
98 * Low Level Configuration Settings
99 * (address mappings, register initial values, etc.)
100 * You should know what you are doing if you make changes here.
102 /*-----------------------------------------------------------------------
103 * Internal Memory Mapped Register
105 #define CFG_IMMR 0xFF000000
107 /*-----------------------------------------------------------------------
108 * Definitions for initial stack pointer and data area (in DPRAM)
110 #define CFG_INIT_RAM_ADDR CFG_IMMR
111 #define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
112 #define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
113 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
114 #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
116 /*-----------------------------------------------------------------------
117 * Start addresses for the final memory configuration
118 * (Set up by the startup code)
119 * Please note that CFG_SDRAM_BASE _must_ start at 0
121 #define CFG_SDRAM_BASE 0x00000000
122 #define CFG_FLASH_BASE 0x40000000
123 #define CFG_MONITOR_LEN (128 << 10) /* Reserve 128 kB for Monitor */
124 #define CFG_MONITOR_BASE CFG_FLASH_BASE
125 #define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
128 * For booting Linux, the board info and command line data
129 * have to be in the first 8 MB of memory, since this is
130 * the maximum mapped by the Linux kernel during initialization.
132 #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
134 /*-----------------------------------------------------------------------
137 #define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
138 #define CFG_MAX_FLASH_SECT 71 /* max number of sectors on one chip */
140 #define CFG_FLASH_ERASE_TOUT 8000 /* Timeout for Flash Erase (in ms) */
141 #define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
143 #define CFG_ENV_IS_IN_FLASH 1
144 /* This is a litlebit wasteful, but one sector is 128kb and we have to
145 * assigne a whole sector for the environment, so that we can safely
146 * erase and write it without disturbing the boot sector
148 #define CFG_ENV_OFFSET 0x20000 /* Offset of Environment Sector */
149 #define CFG_ENV_SIZE 0x20000 /* Total Size of Environment Sector */
151 /*-----------------------------------------------------------------------
152 * Cache Configuration
154 #define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
155 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
156 #define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
159 /*-----------------------------------------------------------------------
160 * SYPCR - System Protection Control 11-9
161 * SYPCR can only be written once after reset!
162 *-----------------------------------------------------------------------
163 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
165 #ifdef CONFIG_WATCHDOG
166 #define CFG_SYPCR (SYPCR_SWTC | SYPCR_SWF | SYPCR_SWE | SYPCR_SWRI | SYPCR_SWP)
168 #define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF)
171 /*-----------------------------------------------------------------------
172 * SIUMCR - SIU Module Configuration 11-6
173 *-----------------------------------------------------------------------
174 * PCMCIA config., multi-function pin tri-state
176 #define CFG_PRE_SIUMCR (SIUMCR_DBGC11 | SIUMCR_MPRE | \
177 SIUMCR_MLRC01 | SIUMCR_GB5E)
178 #define CFG_SIUMCR (CFG_PRE_SIUMCR | SIUMCR_DLK)
180 /*-----------------------------------------------------------------------
181 * TBSCR - Time Base Status and Control 11-26
182 *-----------------------------------------------------------------------
183 * Clear Reference Interrupt Status, Timebase freezing enabled
185 #define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
187 /*-----------------------------------------------------------------------
188 * RTCSC - Real-Time Clock Status and Control Register 11-27
189 *-----------------------------------------------------------------------
191 #define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
193 /*-----------------------------------------------------------------------
194 * PISCR - Periodic Interrupt Status and Control 11-31
195 *-----------------------------------------------------------------------
196 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
198 #define CFG_PISCR (PISCR_PS | PISCR_PITF)
200 /*-----------------------------------------------------------------------
201 * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
202 *-----------------------------------------------------------------------
203 * Reset PLL lock status sticky bit, timer expired status bit and timer
204 * interrupt status bit miltiplier of 0x00b i.e. operation clock is
205 * 4MHz * (0x00b+1) = 4MHz * 12 = 48MHz
207 #define CFG_PLPRCR (0x00b00000 | PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
209 /*-----------------------------------------------------------------------
210 * SCCR - System Clock and reset Control Register 15-27
211 *-----------------------------------------------------------------------
212 * Set clock output, timebase and RTC source and divider,
213 * power management and some other internal clocks
215 #define SCCR_MASK SCCR_EBDF11
216 #define CFG_SCCR ( SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
217 SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
223 * In the Flaga DM we have:
224 * Flash on BR0/OR0/CS0a at 0x40000000
225 * Display on BR1/OR1/CS1 at 0x20000000
226 * SDRAM on BR2/OR2/CS2 at 0x00000000
228 * DSP1 on BR4/OR4/CS4 at 0x80000000
229 * DSP2 on BR5/OR5/CS5 at 0xa0000000
231 * For now we just configure the Flash and the SDRAM and leave the others
235 #define CFG_FLASH_PROTECTION 0
237 #define FLASH_BASE0 0x40000000 /* FLASH bank #0 */
239 /* used to re-map FLASH both when starting from SRAM or FLASH:
240 * restrict access enough to keep SRAM working (if any)
241 * but not too much to meddle with FLASH accesses
243 #define CFG_OR_AM 0xff000000 /* OR addr mask */
244 #define CFG_OR_ATM 0x00006000
246 /* FLASH timing: ACS = 10, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 1 */
247 #define CFG_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_DIV4 | OR_BI | \
248 OR_SCY_3_CLK | OR_TRLX | OR_EHTR )
250 #define CFG_OR0_PRELIM (CFG_OR_AM | CFG_OR_ATM | CFG_OR_TIMING_FLASH)
251 #define CFG_BR0_PRELIM ((FLASH_BASE0 & BR_BA_MSK) | BR_PS_16 | BR_V )
254 * BR2 and OR2 (SDRAM)
257 #define SDRAM_BASE2 0x00000000 /* SDRAM bank #0 */
258 #define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */
260 /* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
261 #define CFG_OR_TIMING_SDRAM ( 0x00000800 )
263 #define CFG_OR2_PRELIM (CFG_OR_AM | CFG_OR_TIMING_SDRAM)
264 #define CFG_BR2_PRELIM ((SDRAM_BASE2 & BR_BA_MSK) | BR_MS_UPMA | BR_V )
266 #define CFG_BR2 CFG_BR2_PRELIM
267 #define CFG_OR2 CFG_OR2_PRELIM
270 * MAMR settings for SDRAM
272 #define CFG_MAMR_48_SDR (CFG_MAMR_PTA | MAMR_WLFA_1X | MAMR_RLFA_1X \
276 * Memory Periodic Timer Prescaler
279 /* periodic timer for refresh */
280 #define CFG_MAMR_PTA 0x0F000000
285 * We do not wan't preliminary setup of the DSP, anyway we need the
286 * UPMB setup correctly before we can access the DSP.
289 #define DSP_BASE 0x80000000
291 #define CFG_OR4 ( OR_AM_MSK | OR_CSNT_SAM | OR_BI | OR_G5LS)
292 #define CFG_BR4 ( (DSP_BASE & BR_BA_MSK) | BR_PS_16 | BR_MS_UPMB | BR_V )
295 * Internal Definitions
299 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
300 #define BOOTFLAG_WARM 0x02 /* Software reboot */
302 #endif /* __CONFIG_H */