2 * A collection of structures, addresses, and values associated with
3 * the Motorola 860T FADS board. Copied from the MBX stuff.
4 * Magnus Damm added defines for 8xxrom and extended bd_info.
5 * Helmut Buchsbaum added bitvalues for BCSRx
7 * Copyright (c) 1998 Dan Malek (dmalek@jlc.net)
11 * 1999-nov-26: The FADS is using the following physical memorymap:
13 * ff020000 -> ff02ffff : pcmcia io remapping
14 * ff010000 -> ff01ffff : BCSR connected to CS1, setup by U-Boot
15 * ff000000 -> ff00ffff : IMAP internal in the cpu
16 * e0000000 -> f3ffffff : pcmcia memory remapping by m8xx_pcmcia
17 * fe000000 -> fe1fffff : flash connected to CS0, setup by U-Boot
18 * 00000000 -> nnnnnnnn : sdram/dram setup by U-Boot
21 #define CONFIG_SYS_PCMCIA_IO_ADDR 0xff020000
22 #define CONFIG_SYS_PCMCIA_IO_SIZE 0x10000
23 #define CONFIG_SYS_PCMCIA_MEM_ADDR 0xe0000000
24 #define CONFIG_SYS_PCMCIA_MEM_SIZE 0x10000
25 #define CONFIG_SYS_IMMR 0xFF000000
26 #define CONFIG_SYS_SDRAM_SIZE (4<<20) /* standard FADS has 4M */
27 #define CONFIG_SYS_SDRAM_BASE 0x00000000
28 #define CONFIG_SYS_FLASH_BASE 0x02800000
29 #define BCSR_ADDR ((uint) 0xff010000)
30 #define FLASH_BASE0_PRELIM 0x02800000 /* FLASH bank #0 */
32 /* ------------------------------------------------------------------------- */
35 * board/config.h - configuration options, board specific
41 #define CONFIG_SYS_TEXT_BASE 0xFE000000
43 #define CONFIG_ETHADDR 08:00:22:50:70:63 /* Ethernet address */
44 #define CONFIG_ENV_OVERWRITE 1 /* Overwrite the environment */
46 #define CONFIG_VIDEO 1 /* To enable video controller support */
47 #define CONFIG_HARD_I2C 1 /* To I2C with hardware support */
48 #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
49 #define CONFIG_SYS_I2C_SLAVE 0x7F
51 /*#define CONFIG_PCMCIA 1 / * To enable PCMCIA support */
55 #define CONFIG_VIDEO_LOGO 1 /* Show the logo */
56 #define CONFIG_VIDEO_ENCODER_AD7176 1 /* Enable this encoder */
57 #define CONFIG_VIDEO_ENCODER_AD7176_ADDR 0x54 /* Default on fads */
58 #define CONFIG_VIDEO_SIZE (2*1024*1024)
59 /* #define CONFIG_VIDEO_ADDR (gd->bd->bi_memsize - CONFIG_VIDEO_SIZE) Frame buffer address */
61 /* Wireless 56Khz 4PPM keyboard on SMCx */
63 /*#define CONFIG_KEYBOARD 1 */
64 #define CONFIG_WL_4PPM_KEYBOARD_SMC 0 /* SMC to use (0 indexed) */
67 * High Level Configuration Options
70 #define CONFIG_MPC823 1
71 #define CONFIG_MPC823FADS 1
74 #define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
75 #undef CONFIG_8xx_CONS_SMC2
76 #undef CONFIG_8xx_CONS_NONE
77 #define CONFIG_BAUDRATE 115200
79 /* Set the CPU speed to 50Mhz on the FADS */
82 #define MPC8XX_FACT 10 /* Multiply by 10 */
83 #define MPC8XX_XIN 5000000 /* 5 MHz in */
85 #define MPC8XX_FACT 10 /* Multiply by 10 */
86 #define MPC8XX_XIN 5000000 /* 5 MHz in */
87 #define CONFIG_SYS_PLPRCR_MF (MPC8XX_FACT-1) << 20 /* From 0 to 4095 */
89 #define MPC8XX_HZ ((MPC8XX_XIN) * (MPC8XX_FACT))
91 #define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */
94 #define CONFIG_BOOTDELAY 2 /* autoboot after 2 seconds */
95 #define CONFIG_LOADS_ECHO 0 /* Dont echoes received characters */
96 #define CONFIG_BOOTARGS ""
97 #define CONFIG_BOOTCOMMAND \
99 "setenv bootargs console=tty0 console=ttyS0 " \
100 "root=/dev/nfs nfsroot=${serverip}:${rootpath} " \
101 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}:eth0:off ;" \
104 #define CONFIG_BOOTDELAY 0 /* autoboot disabled */
107 #undef CONFIG_WATCHDOG /* watchdog disabled */
113 #define CONFIG_BOOTP_SUBNETMASK
114 #define CONFIG_BOOTP_GATEWAY
115 #define CONFIG_BOOTP_HOSTNAME
116 #define CONFIG_BOOTP_BOOTPATH
117 #define CONFIG_BOOTP_BOOTFILESIZE
118 #define CONFIG_BOOTP_SUBNETMASK
119 #define CONFIG_BOOTP_GATEWAY
120 #define CONFIG_BOOTP_HOSTNAME
121 #define CONFIG_BOOTP_NISDOMAIN
122 #define CONFIG_BOOTP_BOOTPATH
123 #define CONFIG_BOOTP_DNS
124 #define CONFIG_BOOTP_DNS2
125 #define CONFIG_BOOTP_SEND_HOSTNAME
126 #define CONFIG_BOOTP_NTPSERVER
127 #define CONFIG_BOOTP_TIMEOFFSET
131 * Command line configuration.
133 #include <config_cmd_default.h>
137 * Miscellaneous configurable options
139 #define CONFIG_SYS_LONGHELP /* undef to save memory */
140 #define CONFIG_SYS_PROMPT ":>" /* Monitor Command Prompt */
141 #if defined(CONFIG_CMD_KGDB)
142 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
144 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
146 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
147 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
148 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
150 #define CONFIG_SYS_MEMTEST_START 0x00004000 /* memtest works on */
151 #define CONFIG_SYS_MEMTEST_END 0x01000000 /* 0 ... 16 MB in DRAM */
153 #define CONFIG_SYS_LOAD_ADDR 0x00100000 /* default load address */
156 * Low Level Configuration Settings
157 * (address mappings, register initial values, etc.)
158 * You should know what you are doing if you make changes here.
160 /*-----------------------------------------------------------------------
161 * Internal Memory Mapped Register
163 #define CONFIG_SYS_IMMR_SIZE ((uint)(64 * 1024))
165 /*-----------------------------------------------------------------------
166 * Definitions for initial stack pointer and data area (in DPRAM)
168 #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
169 #define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */
170 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
171 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
173 /*-----------------------------------------------------------------------
174 * Start addresses for the final memory configuration
175 * (Set up by the startup code)
176 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
177 * Also NOTE that it doesn't mean SDRAM - it means MEMORY.
179 #define CONFIG_SYS_FLASH_SIZE ((uint)(8 * 1024 * 1024)) /* max 8Mbyte */
181 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
183 #define CONFIG_SYS_MONITOR_LEN (512 << 10) /* Reserve 512 kB for Monitor */
185 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
186 #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
189 * For booting Linux, the board info and command line data
190 * have to be in the first 8 MB of memory, since this is
191 * the maximum mapped by the Linux kernel during initialization.
193 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
194 /*-----------------------------------------------------------------------
197 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
198 #define CONFIG_SYS_MAX_FLASH_SECT 8 /* max number of sectors on one chip */
200 #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
201 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
203 #define CONFIG_ENV_IS_IN_FLASH 1
204 #define CONFIG_ENV_OFFSET 0x00040000 /* Offset of Environment Sector */
205 #define CONFIG_ENV_SIZE 0x40000 /* Total Size of Environment Sector */
206 #define CONFIG_SYS_USE_PPCENV /* Environment embedded in sect .ppcenv */
208 /*-----------------------------------------------------------------------
209 * Cache Configuration
211 #define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
212 #if defined(CONFIG_CMD_KGDB)
213 #define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */
216 /*-----------------------------------------------------------------------
217 * SYPCR - System Protection Control 11-9
218 * SYPCR can only be written once after reset!
219 *-----------------------------------------------------------------------
220 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
222 #if defined(CONFIG_WATCHDOG)
223 #define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
224 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
226 #define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
229 /*-----------------------------------------------------------------------
230 * SIUMCR - SIU Module Configuration 11-6
231 *-----------------------------------------------------------------------
232 * PCMCIA config., multi-function pin tri-state
234 #define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
236 /*-----------------------------------------------------------------------
237 * TBSCR - Time Base Status and Control 11-26
238 *-----------------------------------------------------------------------
239 * Clear Reference Interrupt Status, Timebase freezing enabled
241 #define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBE)
243 /*-----------------------------------------------------------------------
244 * PISCR - Periodic Interrupt Status and Control 11-31
245 *-----------------------------------------------------------------------
246 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
248 #define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF)
250 /*-----------------------------------------------------------------------
251 * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
252 *-----------------------------------------------------------------------
253 * Reset PLL lock status sticky bit, timer expired status bit and timer *
254 * interrupt status bit - leave PLL multiplication factor unchanged !
256 #define CONFIG_SYS_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST | CONFIG_SYS_PLPRCR_MF)
258 /*-----------------------------------------------------------------------
259 * SCCR - System Clock and reset Control Register 15-27
260 *-----------------------------------------------------------------------
261 * Set clock output, timebase and RTC source and divider,
262 * power management and some other internal clocks
264 #define SCCR_MASK SCCR_EBDF11
265 #define CONFIG_SYS_SCCR (SCCR_TBS | \
266 SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
267 SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
270 /*-----------------------------------------------------------------------
272 *-----------------------------------------------------------------------
275 #define CONFIG_SYS_DER 0
277 /* Because of the way the 860 starts up and assigns CS0 the
278 * entire address space, we have to set the memory controller
279 * differently. Normally, you write the option register
280 * first, and then enable the chip select by writing the
281 * base register. For CS0, you must write the base register
282 * first, followed by the option register.
286 * Init Memory Controller:
288 * BR0/1 and OR0/1 (FLASH)
290 /* the other CS:s are determined by looking at parameters in BCSRx */
292 #define BCSR_SIZE ((uint)(64 * 1024))
294 #define FLASH_BASE1_PRELIM 0x00000000 /* FLASH bank #1 */
296 #define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */
297 #define CONFIG_SYS_PRELIM_OR_AM 0xFFE00000 /* OR addr mask */
299 /* FLASH timing: ACS = 10, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 0 */
300 #define CONFIG_SYS_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_DIV4 | OR_BI | OR_SCY_3_CLK | OR_TRLX)
302 #define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
303 #define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) /* 1 Mbyte until detected and only 1 Mbyte is needed*/
304 #define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
306 /* BCSRx - Board Control and Status Registers */
307 #define CONFIG_SYS_OR1_REMAP CONFIG_SYS_OR0_REMAP
308 #define CONFIG_SYS_OR1_PRELIM 0xffff8110 /* 64Kbyte address space */
309 #define CONFIG_SYS_BR1_PRELIM ((BCSR_ADDR) | BR_V )
313 * Memory Periodic Timer Prescaler
316 /* periodic timer for refresh */
317 #define CONFIG_SYS_MAMR_PTA 97 /* start with divider for 100 MHz */
319 /* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit */
320 #define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */
321 #define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */
323 /* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */
324 #define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */
325 #define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */
328 * MAMR settings for SDRAM
332 #define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
333 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
334 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
336 #define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
337 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
338 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
340 #define CONFIG_SYS_MAMR 0x13a01114
342 /* values according to the manual */
344 #define BCSR0 ((uint) (BCSR_ADDR + 00))
345 #define BCSR1 ((uint) (BCSR_ADDR + 0x04))
346 #define BCSR2 ((uint) (BCSR_ADDR + 0x08))
347 #define BCSR3 ((uint) (BCSR_ADDR + 0x0c))
348 #define BCSR4 ((uint) (BCSR_ADDR + 0x10))
350 /* FADS bitvalues by Helmut Buchsbaum
351 * see MPC8xxADS User's Manual for a proper description
352 * of the following structures
355 #define BCSR0_ERB ((uint)0x80000000)
356 #define BCSR0_IP ((uint)0x40000000)
357 #define BCSR0_BDIS ((uint)0x10000000)
358 #define BCSR0_BPS_MASK ((uint)0x0C000000)
359 #define BCSR0_ISB_MASK ((uint)0x01800000)
360 #define BCSR0_DBGC_MASK ((uint)0x00600000)
361 #define BCSR0_DBPC_MASK ((uint)0x00180000)
362 #define BCSR0_EBDF_MASK ((uint)0x00060000)
364 #define BCSR1_FLASH_EN ((uint)0x80000000)
365 #define BCSR1_DRAM_EN ((uint)0x40000000)
366 #define BCSR1_ETHEN ((uint)0x20000000)
367 #define BCSR1_IRDEN ((uint)0x10000000)
368 #define BCSR1_FLASH_CFG_EN ((uint)0x08000000)
369 #define BCSR1_CNT_REG_EN_PROTECT ((uint)0x04000000)
370 #define BCSR1_BCSR_EN ((uint)0x02000000)
371 #define BCSR1_RS232EN_1 ((uint)0x01000000)
372 #define BCSR1_PCCEN ((uint)0x00800000)
373 #define BCSR1_PCCVCC0 ((uint)0x00400000)
374 #define BCSR1_PCCVPP_MASK ((uint)0x00300000)
375 #define BCSR1_DRAM_HALF_WORD ((uint)0x00080000)
376 #define BCSR1_RS232EN_2 ((uint)0x00040000)
377 #define BCSR1_SDRAM_EN ((uint)0x00020000)
378 #define BCSR1_PCCVCC1 ((uint)0x00010000)
380 #define BCSR2_FLASH_PD_MASK ((uint)0xF0000000)
381 #define BCSR2_FLASH_PD_SHIFT 28
382 #define BCSR2_DRAM_PD_MASK ((uint)0x07800000)
383 #define BCSR2_DRAM_PD_SHIFT 23
384 #define BCSR2_EXTTOLI_MASK ((uint)0x00780000)
385 #define BCSR2_DBREVNR_MASK ((uint)0x00030000)
387 #define BCSR3_DBID_MASK ((ushort)0x3800)
388 #define BCSR3_CNT_REG_EN_PROTECT ((ushort)0x0400)
389 #define BCSR3_BREVNR0 ((ushort)0x0080)
390 #define BCSR3_FLASH_PD_MASK ((ushort)0x0070)
391 #define BCSR3_BREVN1 ((ushort)0x0008)
392 #define BCSR3_BREVN2_MASK ((ushort)0x0003)
394 #define BCSR4_ETHLOOP ((uint)0x80000000)
395 #define BCSR4_TFPLDL ((uint)0x40000000)
396 #define BCSR4_TPSQEL ((uint)0x20000000)
397 #define BCSR4_SIGNAL_LAMP ((uint)0x10000000)
399 #define BCSR4_USB_EN ((uint)0x08000000)
400 #endif /* CONFIG_MPC823 */
401 #ifdef CONFIG_MPC860SAR
402 #define BCSR4_UTOPIA_EN ((uint)0x08000000)
403 #endif /* CONFIG_MPC860SAR */
404 #ifdef CONFIG_MPC860T
405 #define BCSR4_FETH_EN ((uint)0x08000000)
406 #endif /* CONFIG_MPC860T */
408 #define BCSR4_USB_SPEED ((uint)0x04000000)
409 #endif /* CONFIG_MPC823 */
410 #ifdef CONFIG_MPC860T
411 #define BCSR4_FETHCFG0 ((uint)0x04000000)
412 #endif /* CONFIG_MPC860T */
414 #define BCSR4_VCCO ((uint)0x02000000)
415 #endif /* CONFIG_MPC823 */
416 #ifdef CONFIG_MPC860T
417 #define BCSR4_FETHFDE ((uint)0x02000000)
418 #endif /* CONFIG_MPC860T */
420 #define BCSR4_VIDEO_ON ((uint)0x00800000)
421 #endif /* CONFIG_MPC823 */
423 #define BCSR4_VDO_EKT_CLK_EN ((uint)0x00400000)
424 #endif /* CONFIG_MPC823 */
425 #ifdef CONFIG_MPC860T
426 #define BCSR4_FETHCFG1 ((uint)0x00400000)
427 #endif /* CONFIG_MPC860T */
429 #define BCSR4_VIDEO_RST ((uint)0x00200000)
430 #endif /* CONFIG_MPC823 */
431 #ifdef CONFIG_MPC860T
432 #define BCSR4_FETHRST ((uint)0x00200000)
433 #endif /* CONFIG_MPC860T */
435 #define BCSR4_MODEM_EN ((uint)0x00100000)
436 #endif /* CONFIG_MPC823 */
438 #define BCSR4_DATA_VOICE ((uint)0x00080000)
439 #endif /* CONFIG_MPC823 */
441 #define BCSR4_DATA_VOICE ((uint)0x00080000)
442 #endif /* CONFIG_MPC850 */
444 #define CONFIG_DRAM_50MHZ 1
445 #define CONFIG_SDRAM_50MHZ
447 /* We don't use the 8259.
449 #define NR_8259_INTS 0
454 #define CONFIG_SCC_ENET 1
455 #define CONFIG_SCC2_ENET 1
456 #undef CONFIG_FEC_ENET
457 #undef CONFIG_CPM_IIC
458 #undef CONFIG_UCODE_PATCH
460 #define CONFIG_DISK_SPINUP_TIME 1000000
462 /* PCMCIA configuration */
464 #define PCMCIA_MAX_SLOTS 1
467 #define PCMCIA_SLOT_A 1
470 #define CONFIG_SYS_DAUGHTERBOARD
472 #endif /* __CONFIG_H */