2 * A collection of structures, addresses, and values associated with
3 * the Motorola DUET ADS board. Values common to all FADS family boards
4 * are in board/fads/fads.h
6 * Copyright (C) 2003 Arabella Software Ltd.
7 * Yuli Barcohen <yuli@arabellasw.com>
14 #define CONFIG_DUET_ADS 1 /* Duet (MPC87x/88x) ADS */
15 #define CONFIG_FADS 1 /* We are FADS compatible (more or less) */
17 #define CONFIG_MPC885 1 /* MPC885 CPU (Duet family) */
19 #define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
20 #undef CONFIG_8xx_CONS_SMC2
21 #undef CONFIG_8xx_CONS_NONE
22 #define CONFIG_BAUDRATE 38400
24 #define CFG_8XX_FACT 5 /* Multiply by 5 */
25 #define CFG_8XX_XIN 10000000 /* 10 MHz in */
27 #define CONFIG_SDRAM_50MHZ 1
29 /*-----------------------------------------------------------------------
30 * PLPRCR - PLL, Low-Power, and Reset Control Register 14-22
31 *-----------------------------------------------------------------------
32 * set the PLL, the low-power modes and the reset control
34 #define CFG_PLPRCR ((CFG_8XX_FACT << PLPRCR_MFI_SHIFT) | PLPRCR_TEXPS)
38 #define CFG_PHYDEV_ADDR (BCSR_ADDR + 0x20000)
40 #define CFG_OR5_PRELIM 0xFFFF8110 /* 64Kbyte address space */
41 #define CFG_BR5_PRELIM (CFG_PHYDEV_ADDR | BR_PS_8 | BR_V)
43 #define BCSR5 (CFG_PHYDEV_ADDR + 0x300)
45 #define BCSR5_MII2_EN 0x40
46 #define BCSR5_MII2_RST 0x20
47 #define BCSR5_T1_RST 0x10
48 #define BCSR5_ATM155_RST 0x08
49 #define BCSR5_ATM25_RST 0x04
50 #define BCSR5_MII1_EN 0x02
51 #define BCSR5_MII1_RST 0x01
53 #endif /* __CONFIG_H */