2 * (C) Copyright 2003, Psyent Corporation <www.psyent.com>
3 * Scott McNutt <smcnutt@psyent.com>
4 * Stephan Linz <linz@li-pro.net>
6 * See file CREDITS for list of people who contributed to this
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
28 /***********************************************************************
29 * Include the whole NIOS CPU configuration.
31 * !!! HAVE TO BE HERE !!! DON'T MOVE THIS PART !!!
33 ***********************************************************************/
35 #if defined(CONFIG_NIOS_SAFE_32)
36 #include <configs/DK1C20_safe_32.h>
37 #elif defined(CONFIG_NIOS_STANDARD_32)
38 #include <configs/DK1C20_standard_32.h>
40 #error *** CFG_ERROR: you have to setup right NIOS CPU configuration
43 /*------------------------------------------------------------------------
44 * BOARD/CPU -- TOP-LEVEL
45 *----------------------------------------------------------------------*/
46 #define CONFIG_NIOS 1 /* NIOS-32 core */
47 #define CONFIG_DK1C20 1 /* Cyclone DK-1C20 board*/
48 #define CONFIG_SYS_CLK_FREQ CFG_NIOS_CPU_CLK/* 50 MHz core clock */
49 #define CFG_HZ 1000 /* 1 msec time tick */
51 #define CONFIG_BOARD_EARLY_INIT_F 1 /* enable early board-spec. init*/
53 /*------------------------------------------------------------------------
54 * BASE ADDRESSES / SIZE (Flash, SRAM, SDRAM)
55 *----------------------------------------------------------------------*/
56 #if (CFG_NIOS_CPU_SDRAM_SIZE != 0)
58 #define CFG_SDRAM_BASE CFG_NIOS_CPU_SDRAM_BASE
59 #define CFG_SDRAM_SIZE CFG_NIOS_CPU_SDRAM_SIZE
62 #error *** CFG_ERROR: you have to setup any SDRAM in NIOS CPU config
65 #define CFG_SRAM_BASE CFG_NIOS_CPU_SRAM_BASE
66 #define CFG_SRAM_SIZE CFG_NIOS_CPU_SRAM_SIZE
67 #define CFG_VECT_BASE CFG_NIOS_CPU_VEC_BASE
69 /*------------------------------------------------------------------------
70 * MEMORY ORGANIZATION - For the most part, you can put things pretty
71 * much anywhere. This is pretty flexible for Nios. So here we make some
72 * arbitrary choices & assume that the monitor is placed at the end of
73 * a memory resource (so you must make sure TEXT_BASE is chosen
76 * -The heap is placed below the monitor.
77 * -Global data is placed below the heap.
78 * -The stack is placed below global data (&grows down).
79 *----------------------------------------------------------------------*/
80 #define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256k */
81 #define CFG_GBL_DATA_SIZE 128 /* Global data size rsvd*/
82 #define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024)
84 #define CFG_MONITOR_BASE TEXT_BASE
85 #define CFG_MALLOC_BASE (CFG_MONITOR_BASE - CFG_MALLOC_LEN)
86 #define CFG_GBL_DATA_OFFSET (CFG_MALLOC_BASE - CFG_GBL_DATA_SIZE)
87 #define CFG_INIT_SP CFG_GBL_DATA_OFFSET
89 /*------------------------------------------------------------------------
91 *----------------------------------------------------------------------*/
92 #if (CFG_NIOS_CPU_FLASH_SIZE != 0)
94 #define CFG_FLASH_BASE CFG_NIOS_CPU_FLASH_BASE
95 #define CFG_FLASH_SIZE CFG_NIOS_CPU_FLASH_SIZE
96 #define CFG_MAX_FLASH_SECT 128 /* Max # sects per bank */
97 #define CFG_MAX_FLASH_BANKS 1 /* Max # of flash banks */
98 #define CFG_FLASH_ERASE_TOUT 8000 /* Erase timeout (msec) */
99 #define CFG_FLASH_WRITE_TOUT 100 /* Write timeout (msec) */
100 #define CFG_FLASH_WORD_SIZE unsigned char /* flash word size */
103 #error *** CFG_ERROR: you have to setup any Flash memory in NIOS CPU config
106 /*------------------------------------------------------------------------
108 *----------------------------------------------------------------------*/
109 #if (CFG_NIOS_CPU_FLASH_SIZE != 0)
111 #define CFG_ENV_IS_IN_FLASH 1 /* Environment in flash */
112 #define CFG_ENV_ADDR CFG_FLASH_BASE /* Mem addr of env */
113 #define CFG_ENV_SIZE (64 * 1024) /* 64 KByte (1 sector) */
114 #define CONFIG_ENV_OVERWRITE /* Serial/eth change Ok */
117 #define CFG_ENV_IS_NOWHERE 1 /* NO Environment */
120 /*------------------------------------------------------------------------
122 *----------------------------------------------------------------------*/
123 #if (CFG_NIOS_CPU_UART_NUMS != 0)
125 #define CFG_NIOS_CONSOLE CFG_NIOS_CPU_UART0 /* 1st UART is Cons. */
127 #if (CFG_NIOS_CPU_UART0_BR != 0)
128 #define CFG_NIOS_FIXEDBAUD 1 /* Baudrate is fixed */
129 #define CONFIG_BAUDRATE CFG_NIOS_CPU_UART0_BR
131 #undef CFG_NIOS_FIXEDBAUD
132 #define CONFIG_BAUDRATE 115200
135 #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
138 #error *** CFG_ERROR: you have to setup at least one UART in NIOS CPU config
141 /*------------------------------------------------------------------------
142 * TIMER FOR TIMEBASE -- Nios doesn't have the equivalent of ppc PIT,
143 * so an avalon bus timer is required.
144 *----------------------------------------------------------------------*/
145 #if (CFG_NIOS_CPU_TIMER_NUMS != 0)
147 #if (CFG_NIOS_CPU_TICK_TIMER == 0)
149 #error *** CFG_ERROR: tick timer at TIMER0 not supported, expand your config.h
151 #elif (CFG_NIOS_CPU_TICK_TIMER == 1)
153 #define CFG_NIOS_TMRBASE CFG_NIOS_CPU_TIMER1 /* TIMER1 as tick */
154 #define CFG_NIOS_TMRIRQ CFG_NIOS_CPU_TIMER1_IRQ
156 #if (CFG_NIOS_CPU_TIMER1_PER >= CFG_HZ)
157 #define CFG_NIOS_TMRMS (CFG_NIOS_CPU_TIMER1_PER / CFG_HZ)
159 #error *** CFG_ERROR: you have to use a timer periode of more than CFG_HZ
162 #endif /* CFG_NIOS_CPU_TICK_TIMER */
165 #error *** CFG_ERROR: you have to setup at least one TIMER in NIOS CPU config
168 /*------------------------------------------------------------------------
170 *----------------------------------------------------------------------*/
171 #if (CFG_NIOS_CPU_LAN_NUMS == 1)
173 #if (CFG_NIOS_CPU_LAN0_TYPE == 0) /* LAN91C111 */
175 #define CONFIG_DRIVER_SMC91111 /* Using SMC91c111 */
176 #undef CONFIG_SMC91111_EXT_PHY /* Internal PHY */
177 #define CONFIG_SMC91111_BASE (CFG_NIOS_CPU_LAN0_BASE + CFG_NIOS_CPU_LAN0_OFFS)
179 #if (CFG_NIOS_CPU_LAN0_BUSW == 32)
180 #define CONFIG_SMC_USE_32_BIT 1
182 #undef CONFIG_SMC_USE_32_BIT
185 #elif (CFG_NIOS_CPU_LAN0_TYPE == 1) /* CS8900A */
187 /********************************************/
188 /* !!! CS8900 is __not__ tested on NIOS !!! */
189 /********************************************/
190 #define CONFIG_DRIVER_CS8900 /* Using CS8900 */
191 #define CS8900_BASE (CFG_NIOS_CPU_LAN0_BASE + CFG_NIOS_CPU_LAN0_OFFS)
193 #if (CFG_NIOS_CPU_LAN0_BUSW == 32)
195 #define CS8900_BUS32 1
197 #define CS8900_BUS16 1
202 #error *** CFG_ERROR: invalid LAN0 chip type, check your NIOS CPU config
205 #define CONFIG_ETHADDR 08:00:3e:26:0a:5b
206 #define CONFIG_NETMASK 255.255.255.0
207 #define CONFIG_IPADDR 192.168.2.21
208 #define CONFIG_SERVERIP 192.168.2.16
211 #error *** CFG_ERROR: you have to setup just one LAN only or expand your config.h
214 /*------------------------------------------------------------------------
216 *----------------------------------------------------------------------*/
217 #if (CFG_NIOS_CPU_PIO_NUMS != 0)
219 #if (CFG_NIOS_CPU_LED_PIO == 0)
221 #error *** CFG_ERROR: status LEDs at PIO0 not supported, expand your config.h
223 #elif (CFG_NIOS_CPU_LED_PIO == 1)
225 #error *** CFG_ERROR: status LEDs at PIO1 not supported, expand your config.h
227 #elif (CFG_NIOS_CPU_LED_PIO == 2)
229 #define STATUS_LED_BASE CFG_NIOS_CPU_PIO2
230 #define STATUS_LED_BITS CFG_NIOS_CPU_PIO2_BITS
231 #define STATUS_LED_ACTIVE 1 /* LED on for bit == 1 */
233 #if (CFG_NIOS_CPU_PIO2_TYPE == 1)
234 #define STATUS_LED_WRONLY 1
236 #undef STATUS_LED_WRONLY
239 #elif (CFG_NIOS_CPU_LED_PIO == 3)
241 #error *** CFG_ERROR: status LEDs at PIO3 not supported, expand your config.h
243 #elif (CFG_NIOS_CPU_LED_PIO == 4)
245 #error *** CFG_ERROR: status LEDs at PIO4 not supported, expand your config.h
247 #elif (CFG_NIOS_CPU_LED_PIO == 5)
249 #error *** CFG_ERROR: status LEDs at PIO5 not supported, expand your config.h
251 #elif (CFG_NIOS_CPU_LED_PIO == 6)
253 #error *** CFG_ERROR: status LEDs at PIO6 not supported, expand your config.h
255 #elif (CFG_NIOS_CPU_LED_PIO == 7)
257 #error *** CFG_ERROR: status LEDs at PIO7 not supported, expand your config.h
259 #elif (CFG_NIOS_CPU_LED_PIO == 8)
261 #error *** CFG_ERROR: status LEDs at PIO8 not supported, expand your config.h
263 #elif (CFG_NIOS_CPU_LED_PIO == 9)
265 #error *** CFG_ERROR: status LEDs at PIO9 not supported, expand your config.h
268 #error *** CFG_ERROR: you have to set CFG_NIOS_CPU_LED_PIO in right case
271 #define CONFIG_STATUS_LED 1 /* enable status led driver */
273 #define STATUS_LED_BIT (1 << 0) /* LED[0] */
274 #define STATUS_LED_STATE STATUS_LED_BLINKING
275 #define STATUS_LED_BOOT_STATE STATUS_LED_OFF
276 #define STATUS_LED_PERIOD (CFG_HZ / 10) /* ca. 1 Hz */
277 #define STATUS_LED_BOOT 0 /* boot LED */
279 #if (STATUS_LED_BITS > 1)
280 #define STATUS_LED_BIT1 (1 << 1) /* LED[1] */
281 #define STATUS_LED_STATE1 STATUS_LED_OFF
282 #define STATUS_LED_PERIOD1 (CFG_HZ / 50) /* ca. 5 Hz */
283 #define STATUS_LED_RED 1 /* fail LED */
286 #if (STATUS_LED_BITS > 2)
287 #define STATUS_LED_BIT2 (1 << 2) /* LED[2] */
288 #define STATUS_LED_STATE2 STATUS_LED_OFF
289 #define STATUS_LED_PERIOD2 (CFG_HZ / 10) /* ca. 1 Hz */
290 #define STATUS_LED_YELLOW 2 /* info LED */
293 #if (STATUS_LED_BITS > 3)
294 #define STATUS_LED_BIT3 (1 << 3) /* LED[3] */
295 #define STATUS_LED_STATE3 STATUS_LED_OFF
296 #define STATUS_LED_PERIOD3 (CFG_HZ / 10) /* ca. 1 Hz */
297 #define STATUS_LED_GREEN 3 /* info LED */
300 #define STATUS_LED_PAR 1 /* makes status_led.h happy */
302 #endif /* CFG_NIOS_CPU_PIO_NUMS */
304 /*------------------------------------------------------------------------
305 * SEVEN SEGMENT LED DISPLAY
306 *----------------------------------------------------------------------*/
307 #if (CFG_NIOS_CPU_PIO_NUMS != 0)
309 #if (CFG_NIOS_CPU_SEVENSEG_PIO == 0)
311 #error *** CFG_ERROR: seven segment display at PIO0 not supported, expand your config.h
313 #elif (CFG_NIOS_CPU_SEVENSEG_PIO == 1)
315 #error *** CFG_ERROR: seven segment display at PIO1 not supported, expand your config.h
317 #elif (CFG_NIOS_CPU_SEVENSEG_PIO == 2)
319 #error *** CFG_ERROR: seven segment display at PIO2 not supported, expand your config.h
321 #elif (CFG_NIOS_CPU_SEVENSEG_PIO == 3)
323 #define SEVENSEG_BASE CFG_NIOS_CPU_PIO3
324 #define SEVENSEG_BITS CFG_NIOS_CPU_PIO3_BITS
325 #define SEVENSEG_ACTIVE 0 /* LED on for bit == 1 */
327 #if (CFG_NIOS_CPU_PIO3_TYPE == 1)
328 #define SEVENSEG_WRONLY 1
330 #undef SEVENSEG_WRONLY
333 #elif (CFG_NIOS_CPU_SEVENSEG_PIO == 4)
335 #error *** CFG_ERROR: seven segment display at PIO4 not supported, expand your config.h
337 #elif (CFG_NIOS_CPU_SEVENSEG_PIO == 5)
339 #error *** CFG_ERROR: seven segment display at PIO5 not supported, expand your config.h
341 #elif (CFG_NIOS_CPU_SEVENSEG_PIO == 6)
343 #error *** CFG_ERROR: seven segment display at PIO6 not supported, expand your config.h
345 #elif (CFG_NIOS_CPU_SEVENSEG_PIO == 7)
347 #error *** CFG_ERROR: seven segment display at PIO7 not supported, expand your config.h
349 #elif (CFG_NIOS_CPU_SEVENSEG_PIO == 8)
351 #error *** CFG_ERROR: seven segment display at PIO8 not supported, expand your config.h
353 #elif (CFG_NIOS_CPU_SEVENSEG_PIO == 9)
355 #error *** CFG_ERROR: seven segment display at PIO9 not supported, expand your config.h
358 #error *** CFG_ERROR: you have to set CFG_NIOS_CPU_SEVENSEG_PIO in right case
361 #define CONFIG_SEVENSEG 1 /* enable seven segment led driver */
364 * Dual 7-Segment Display pin assignment -- read more in your
365 * "Nios Development Board Reference Manual"
368 * (U8) HI:D[15..8] (U9) LO:D[7..0]
373 * |______| |______| ___
374 * | D8 | | D0 | | A |
376 * D10| |D12 D2| |D4 | G |
377 * |______| |______| E|___|C
382 #define SEVENSEG_DIGIT_HI_LO_EQUAL 1 /* high nibble equal low nibble */
383 #define SEVENSEG_DIGIT_A (1 << 6) /* bit 6 is segment A */
384 #define SEVENSEG_DIGIT_B (1 << 5) /* bit 5 is segment B */
385 #define SEVENSEG_DIGIT_C (1 << 4) /* bit 4 is segment C */
386 #define SEVENSEG_DIGIT_D (1 << 3) /* bit 3 is segment D */
387 #define SEVENSEG_DIGIT_E (1 << 2) /* bit 2 is segment E */
388 #define SEVENSEG_DIGIT_F (1 << 1) /* bit 1 is segment F */
389 #define SEVENSEG_DIGIT_G (1 << 0) /* bit 0 is segment G */
390 #define SEVENSEG_DIGIT_DP (1 << 7) /* bit 7 is decimal point */
392 #endif /* CFG_NIOS_CPU_PIO_NUMS */
394 /*------------------------------------------------------------------------
395 * ASMI - Active Serial Memory Interface.
397 * ASMI is for Cyclone devices only and only works when the configuration
398 * is loaded via JTAG or ASMI. Please see doc/README.dk1c20 for details.
399 *----------------------------------------------------------------------*/
400 #define CONFIG_NIOS_ASMI /* Enable ASMI */
401 #define CFG_NIOS_ASMIBASE CFG_NIOS_CPU_ASMI0 /* ASMI base address */
403 /*------------------------------------------------------------------------
405 *----------------------------------------------------------------------*/
406 #define CONFIG_COMMANDS (CFG_CMD_ALL & ~( \
436 #include <cmd_confdefs.h>
438 /*------------------------------------------------------------------------
440 *----------------------------------------------------------------------*/
441 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
442 #define CONFIG_KGDB_BAUDRATE 9600
445 /*------------------------------------------------------------------------
447 *----------------------------------------------------------------------*/
448 #define CFG_LONGHELP /* undef to save memory */
449 #define CFG_PROMPT "DK1C20 > " /* Monitor Command Prompt */
450 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
451 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
452 #define CFG_MAXARGS 16 /* max number of command args*/
453 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
455 #if (CFG_SRAM_SIZE != 0)
456 #define CFG_LOAD_ADDR CFG_SRAM_BASE /* Default load address */
461 #if (CFG_SDRAM_SIZE != 0)
462 #define CFG_MEMTEST_START CFG_SDRAM_BASE /* SDRAM til stack area */
463 #define CFG_MEMTEST_END (CFG_INIT_SP - (1024 * 1024)) /* 1MB stack */
465 #undef CFG_MEMTEST_START
466 #undef CFG_MEMTEST_END
470 #endif /* __CONFIG_H */