2 * (C) Copyright 2001-2005
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * SPDX-License-Identifier: GPL-2.0+
10 * Configuration settings for the CU824 board.
14 /* ------------------------------------------------------------------------- */
17 * board/config.h - configuration options, board specific
24 * High Level Configuration Options
28 #define CONFIG_MPC824X 1
29 #define CONFIG_MPC8240 1
30 #define CONFIG_CU824 1
32 #define CONFIG_SYS_TEXT_BASE 0xFFF00000
34 #define CONFIG_CONS_INDEX 1
35 #define CONFIG_BAUDRATE 9600
37 #define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo"
39 #define CONFIG_BOOTCOMMAND "bootm FE020000" /* autoboot command */
40 #define CONFIG_BOOTDELAY 5
45 #define CONFIG_BOOTP_SUBNETMASK
46 #define CONFIG_BOOTP_GATEWAY
47 #define CONFIG_BOOTP_HOSTNAME
48 #define CONFIG_BOOTP_BOOTPATH
49 #define CONFIG_BOOTP_BOOTFILESIZE
52 #define CONFIG_TIMESTAMP /* Print image info with timestamp */
56 * Command line configuration.
58 #include <config_cmd_default.h>
60 #define CONFIG_CMD_BEDBUG
61 #define CONFIG_CMD_DHCP
62 #define CONFIG_CMD_PCI
63 #define CONFIG_CMD_NFS
64 #define CONFIG_CMD_SNTP
68 * Miscellaneous configurable options
70 #define CONFIG_SYS_LONGHELP /* undef to save memory */
71 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
72 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
75 #define CONFIG_SYS_HUSH_PARSER 1 /* use "hush" command parser */
80 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
82 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
83 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
84 #define CONFIG_SYS_LOAD_ADDR 0x00100000 /* Default load address */
86 /*-----------------------------------------------------------------------
87 * Start addresses for the final memory configuration
88 * (Set up by the startup code)
89 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
91 #define CONFIG_SYS_SDRAM_BASE 0x00000000
92 #define CONFIG_SYS_FLASH_BASE 0xFF000000
94 #define CONFIG_SYS_RESET_ADDRESS 0xFFF00100
96 #define CONFIG_SYS_EUMB_ADDR 0xFCE00000
98 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
100 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
101 #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
103 #define CONFIG_SYS_MEMTEST_START 0x00004000 /* memtest works on */
104 #define CONFIG_SYS_MEMTEST_END 0x02000000 /* 0 ... 32 MB in DRAM */
106 /* Maximum amount of RAM.
108 #define CONFIG_SYS_MAX_RAM_SIZE 0x10000000
111 #if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
112 #undef CONFIG_SYS_RAMBOOT
114 #define CONFIG_SYS_RAMBOOT
118 /*-----------------------------------------------------------------------
119 * Definitions for initial stack pointer and data area
122 #define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
123 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000
124 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
127 * NS16550 Configuration
129 #define CONFIG_SYS_NS16550
130 #define CONFIG_SYS_NS16550_SERIAL
132 #define CONFIG_SYS_NS16550_REG_SIZE 4
134 #define CONFIG_SYS_NS16550_CLK (14745600 / 2)
136 #define CONFIG_SYS_NS16550_COM1 0xFE800080
137 #define CONFIG_SYS_NS16550_COM2 0xFE8000C0
140 * Low Level Configuration Settings
141 * (address mappings, register initial values, etc.)
142 * You should know what you are doing if you make changes here.
143 * For the detail description refer to the MPC8240 user's manual.
146 #define CONFIG_SYS_CLK_FREQ 33000000
147 #define CONFIG_SYS_HZ 1000
149 /* Bit-field values for MCCR1.
151 #define CONFIG_SYS_ROMNAL 0
152 #define CONFIG_SYS_ROMFAL 7
154 /* Bit-field values for MCCR2.
156 #define CONFIG_SYS_REFINT 430 /* Refresh interval */
158 /* Burst To Precharge. Bits of this value go to MCCR3 and MCCR4.
160 #define CONFIG_SYS_BSTOPRE 192
162 /* Bit-field values for MCCR3.
164 #define CONFIG_SYS_REFREC 2 /* Refresh to activate interval */
165 #define CONFIG_SYS_RDLAT 3 /* Data latancy from read command */
167 /* Bit-field values for MCCR4.
169 #define CONFIG_SYS_PRETOACT 2 /* Precharge to activate interval */
170 #define CONFIG_SYS_ACTTOPRE 5 /* Activate to Precharge interval */
171 #define CONFIG_SYS_SDMODE_CAS_LAT 2 /* SDMODE CAS latancy */
172 #define CONFIG_SYS_SDMODE_WRAP 0 /* SDMODE wrap type */
173 #define CONFIG_SYS_SDMODE_BURSTLEN 2 /* SDMODE Burst length */
174 #define CONFIG_SYS_ACTORW 2
175 #define CONFIG_SYS_REGISTERD_TYPE_BUFFER 1
177 /* Memory bank settings.
178 * Only bits 20-29 are actually used from these vales to set the
179 * start/end addresses. The upper two bits will always be 0, and the lower
180 * 20 bits will be 0x00000 for a start address, or 0xfffff for an end
181 * address. Refer to the MPC8240 book.
184 #define CONFIG_SYS_BANK0_START 0x00000000
185 #define CONFIG_SYS_BANK0_END (CONFIG_SYS_MAX_RAM_SIZE - 1)
186 #define CONFIG_SYS_BANK0_ENABLE 1
187 #define CONFIG_SYS_BANK1_START 0x3ff00000
188 #define CONFIG_SYS_BANK1_END 0x3fffffff
189 #define CONFIG_SYS_BANK1_ENABLE 0
190 #define CONFIG_SYS_BANK2_START 0x3ff00000
191 #define CONFIG_SYS_BANK2_END 0x3fffffff
192 #define CONFIG_SYS_BANK2_ENABLE 0
193 #define CONFIG_SYS_BANK3_START 0x3ff00000
194 #define CONFIG_SYS_BANK3_END 0x3fffffff
195 #define CONFIG_SYS_BANK3_ENABLE 0
196 #define CONFIG_SYS_BANK4_START 0x3ff00000
197 #define CONFIG_SYS_BANK4_END 0x3fffffff
198 #define CONFIG_SYS_BANK4_ENABLE 0
199 #define CONFIG_SYS_BANK5_START 0x3ff00000
200 #define CONFIG_SYS_BANK5_END 0x3fffffff
201 #define CONFIG_SYS_BANK5_ENABLE 0
202 #define CONFIG_SYS_BANK6_START 0x3ff00000
203 #define CONFIG_SYS_BANK6_END 0x3fffffff
204 #define CONFIG_SYS_BANK6_ENABLE 0
205 #define CONFIG_SYS_BANK7_START 0x3ff00000
206 #define CONFIG_SYS_BANK7_END 0x3fffffff
207 #define CONFIG_SYS_BANK7_ENABLE 0
209 #define CONFIG_SYS_ODCR 0xff
211 #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
212 #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
214 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE)
215 #define CONFIG_SYS_IBAT1U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
217 #define CONFIG_SYS_IBAT2L (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
218 #define CONFIG_SYS_IBAT2U (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP)
220 #define CONFIG_SYS_IBAT3L (0xFC000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
221 #define CONFIG_SYS_IBAT3U (0xFC000000 | BATU_BL_64M | BATU_VS | BATU_VP)
223 #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
224 #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
225 #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
226 #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
227 #define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
228 #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
229 #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
230 #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
233 * For booting Linux, the board info and command line data
234 * have to be in the first 8 MB of memory, since this is
235 * the maximum mapped by the Linux kernel during initialization.
237 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
239 /*-----------------------------------------------------------------------
242 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* Max number of flash banks */
243 #define CONFIG_SYS_MAX_FLASH_SECT 39 /* Max number of sectors in one bank */
245 #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
246 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
248 /* Warining: environment is not EMBEDDED in the U-Boot code.
249 * It's stored in flash separately.
251 #define CONFIG_ENV_IS_IN_FLASH 1
253 #define CONFIG_ENV_ADDR 0xFF008000
254 #define CONFIG_ENV_SIZE 0x8000 /* Size of the Environment Sector */
256 #define CONFIG_ENV_ADDR 0xFFFC0000
257 #define CONFIG_ENV_SIZE 0x4000 /* Size of the Environment */
258 #define CONFIG_ENV_OFFSET 0 /* starting right at the beginning */
259 #define CONFIG_ENV_SECT_SIZE 0x40000 /* Size of the Environment Sector */
262 /*-----------------------------------------------------------------------
263 * Cache Configuration
265 #define CONFIG_SYS_CACHELINE_SIZE 32
266 #if defined(CONFIG_CMD_KGDB)
267 # define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
270 /*-----------------------------------------------------------------------
272 *-----------------------------------------------------------------------
274 #define CONFIG_PCI /* include pci support */
275 #define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
276 #undef CONFIG_PCI_PNP
280 #define CONFIG_TULIP_USE_IO
282 #define CONFIG_SYS_ETH_DEV_FN 0x7800
283 #define CONFIG_SYS_ETH_IOBASE 0x00104000
285 #define CONFIG_EEPRO100
286 #define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
287 #define PCI_ENET0_IOADDR 0x00104000
288 #define PCI_ENET0_MEMADDR 0x80000000
289 #endif /* __CONFIG_H */