2 * (C) Copyright 2001-2005
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 * Configuration settings for the CU824 board.
30 /* ------------------------------------------------------------------------- */
33 * board/config.h - configuration options, board specific
40 * High Level Configuration Options
44 #define CONFIG_MPC824X 1
45 #define CONFIG_MPC8240 1
46 #define CONFIG_CU824 1
48 #define CONFIG_SYS_TEXT_BASE 0xFFF00000
50 #define CONFIG_CONS_INDEX 1
51 #define CONFIG_BAUDRATE 9600
53 #define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo"
55 #define CONFIG_BOOTCOMMAND "bootm FE020000" /* autoboot command */
56 #define CONFIG_BOOTDELAY 5
61 #define CONFIG_BOOTP_SUBNETMASK
62 #define CONFIG_BOOTP_GATEWAY
63 #define CONFIG_BOOTP_HOSTNAME
64 #define CONFIG_BOOTP_BOOTPATH
65 #define CONFIG_BOOTP_BOOTFILESIZE
68 #define CONFIG_TIMESTAMP /* Print image info with timestamp */
72 * Command line configuration.
74 #include <config_cmd_default.h>
76 #define CONFIG_CMD_BEDBUG
77 #define CONFIG_CMD_DHCP
78 #define CONFIG_CMD_PCI
79 #define CONFIG_CMD_NFS
80 #define CONFIG_CMD_SNTP
84 * Miscellaneous configurable options
86 #define CONFIG_SYS_LONGHELP /* undef to save memory */
87 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
88 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
91 #define CONFIG_SYS_HUSH_PARSER 1 /* use "hush" command parser */
93 #ifdef CONFIG_SYS_HUSH_PARSER
94 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
99 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
101 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
102 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
103 #define CONFIG_SYS_LOAD_ADDR 0x00100000 /* Default load address */
105 /*-----------------------------------------------------------------------
106 * Start addresses for the final memory configuration
107 * (Set up by the startup code)
108 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
110 #define CONFIG_SYS_SDRAM_BASE 0x00000000
111 #define CONFIG_SYS_FLASH_BASE 0xFF000000
113 #define CONFIG_SYS_RESET_ADDRESS 0xFFF00100
115 #define CONFIG_SYS_EUMB_ADDR 0xFCE00000
117 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
119 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
120 #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
122 #define CONFIG_SYS_MEMTEST_START 0x00004000 /* memtest works on */
123 #define CONFIG_SYS_MEMTEST_END 0x02000000 /* 0 ... 32 MB in DRAM */
125 /* Maximum amount of RAM.
127 #define CONFIG_SYS_MAX_RAM_SIZE 0x10000000
130 #if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
131 #undef CONFIG_SYS_RAMBOOT
133 #define CONFIG_SYS_RAMBOOT
137 /*-----------------------------------------------------------------------
138 * Definitions for initial stack pointer and data area
141 #define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
142 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000
143 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
146 * NS16550 Configuration
148 #define CONFIG_SYS_NS16550
149 #define CONFIG_SYS_NS16550_SERIAL
151 #define CONFIG_SYS_NS16550_REG_SIZE 4
153 #define CONFIG_SYS_NS16550_CLK (14745600 / 2)
155 #define CONFIG_SYS_NS16550_COM1 0xFE800080
156 #define CONFIG_SYS_NS16550_COM2 0xFE8000C0
159 * Low Level Configuration Settings
160 * (address mappings, register initial values, etc.)
161 * You should know what you are doing if you make changes here.
162 * For the detail description refer to the MPC8240 user's manual.
165 #define CONFIG_SYS_CLK_FREQ 33000000
166 #define CONFIG_SYS_HZ 1000
168 /* Bit-field values for MCCR1.
170 #define CONFIG_SYS_ROMNAL 0
171 #define CONFIG_SYS_ROMFAL 7
173 /* Bit-field values for MCCR2.
175 #define CONFIG_SYS_REFINT 430 /* Refresh interval */
177 /* Burst To Precharge. Bits of this value go to MCCR3 and MCCR4.
179 #define CONFIG_SYS_BSTOPRE 192
181 /* Bit-field values for MCCR3.
183 #define CONFIG_SYS_REFREC 2 /* Refresh to activate interval */
184 #define CONFIG_SYS_RDLAT 3 /* Data latancy from read command */
186 /* Bit-field values for MCCR4.
188 #define CONFIG_SYS_PRETOACT 2 /* Precharge to activate interval */
189 #define CONFIG_SYS_ACTTOPRE 5 /* Activate to Precharge interval */
190 #define CONFIG_SYS_SDMODE_CAS_LAT 2 /* SDMODE CAS latancy */
191 #define CONFIG_SYS_SDMODE_WRAP 0 /* SDMODE wrap type */
192 #define CONFIG_SYS_SDMODE_BURSTLEN 2 /* SDMODE Burst length */
193 #define CONFIG_SYS_ACTORW 2
194 #define CONFIG_SYS_REGISTERD_TYPE_BUFFER 1
196 /* Memory bank settings.
197 * Only bits 20-29 are actually used from these vales to set the
198 * start/end addresses. The upper two bits will always be 0, and the lower
199 * 20 bits will be 0x00000 for a start address, or 0xfffff for an end
200 * address. Refer to the MPC8240 book.
203 #define CONFIG_SYS_BANK0_START 0x00000000
204 #define CONFIG_SYS_BANK0_END (CONFIG_SYS_MAX_RAM_SIZE - 1)
205 #define CONFIG_SYS_BANK0_ENABLE 1
206 #define CONFIG_SYS_BANK1_START 0x3ff00000
207 #define CONFIG_SYS_BANK1_END 0x3fffffff
208 #define CONFIG_SYS_BANK1_ENABLE 0
209 #define CONFIG_SYS_BANK2_START 0x3ff00000
210 #define CONFIG_SYS_BANK2_END 0x3fffffff
211 #define CONFIG_SYS_BANK2_ENABLE 0
212 #define CONFIG_SYS_BANK3_START 0x3ff00000
213 #define CONFIG_SYS_BANK3_END 0x3fffffff
214 #define CONFIG_SYS_BANK3_ENABLE 0
215 #define CONFIG_SYS_BANK4_START 0x3ff00000
216 #define CONFIG_SYS_BANK4_END 0x3fffffff
217 #define CONFIG_SYS_BANK4_ENABLE 0
218 #define CONFIG_SYS_BANK5_START 0x3ff00000
219 #define CONFIG_SYS_BANK5_END 0x3fffffff
220 #define CONFIG_SYS_BANK5_ENABLE 0
221 #define CONFIG_SYS_BANK6_START 0x3ff00000
222 #define CONFIG_SYS_BANK6_END 0x3fffffff
223 #define CONFIG_SYS_BANK6_ENABLE 0
224 #define CONFIG_SYS_BANK7_START 0x3ff00000
225 #define CONFIG_SYS_BANK7_END 0x3fffffff
226 #define CONFIG_SYS_BANK7_ENABLE 0
228 #define CONFIG_SYS_ODCR 0xff
230 #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
231 #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
233 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE)
234 #define CONFIG_SYS_IBAT1U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
236 #define CONFIG_SYS_IBAT2L (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
237 #define CONFIG_SYS_IBAT2U (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP)
239 #define CONFIG_SYS_IBAT3L (0xFC000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
240 #define CONFIG_SYS_IBAT3U (0xFC000000 | BATU_BL_64M | BATU_VS | BATU_VP)
242 #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
243 #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
244 #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
245 #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
246 #define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
247 #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
248 #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
249 #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
252 * For booting Linux, the board info and command line data
253 * have to be in the first 8 MB of memory, since this is
254 * the maximum mapped by the Linux kernel during initialization.
256 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
258 /*-----------------------------------------------------------------------
261 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* Max number of flash banks */
262 #define CONFIG_SYS_MAX_FLASH_SECT 39 /* Max number of sectors in one bank */
264 #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
265 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
267 /* Warining: environment is not EMBEDDED in the U-Boot code.
268 * It's stored in flash separately.
270 #define CONFIG_ENV_IS_IN_FLASH 1
272 #define CONFIG_ENV_ADDR 0xFF008000
273 #define CONFIG_ENV_SIZE 0x8000 /* Size of the Environment Sector */
275 #define CONFIG_ENV_ADDR 0xFFFC0000
276 #define CONFIG_ENV_SIZE 0x4000 /* Size of the Environment */
277 #define CONFIG_ENV_OFFSET 0 /* starting right at the beginning */
278 #define CONFIG_ENV_SECT_SIZE 0x40000 /* Size of the Environment Sector */
281 /*-----------------------------------------------------------------------
282 * Cache Configuration
284 #define CONFIG_SYS_CACHELINE_SIZE 32
285 #if defined(CONFIG_CMD_KGDB)
286 # define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
289 /*-----------------------------------------------------------------------
291 *-----------------------------------------------------------------------
293 #define CONFIG_PCI /* include pci support */
294 #undef CONFIG_PCI_PNP
298 #define CONFIG_TULIP_USE_IO
300 #define CONFIG_SYS_ETH_DEV_FN 0x7800
301 #define CONFIG_SYS_ETH_IOBASE 0x00104000
303 #define CONFIG_EEPRO100
304 #define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
305 #define PCI_ENET0_IOADDR 0x00104000
306 #define PCI_ENET0_MEMADDR 0x80000000
307 #endif /* __CONFIG_H */