include/configs/CPU87.h

   1 /*
   2  * (C) Copyright 2001-2005
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 /*
   9  * board/config.h - configuration options, board specific
  10  */
  11
  12 #ifndef __CONFIG_H
  13 #define __CONFIG_H
  14
  15 /*
  16  * High Level Configuration Options
  17  * (easy to change)
  18  */
  19
  20 #define CONFIG_MPC8260          1       /* This is an MPC8260 CPU               */
  21 #define CONFIG_CPU87            1       /* ...on a CPU87 board  */
  22 #define CONFIG_PCI
  23 #define CONFIG_CPM2             1       /* Has a CPM2 */
  24
  25 #ifdef CONFIG_BOOT_ROM
  26 #define CONFIG_SYS_TEXT_BASE    0xFF800000
  27 #else
  28 #define CONFIG_SYS_TEXT_BASE    0xFF000000
  29 #endif
  30
  31 /*
  32  * select serial console configuration
  33  *
  34  * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
  35  * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
  36  * for SCC).
  37  *
  38  * if CONFIG_CONS_NONE is defined, then the serial console routines must
  39  * defined elsewhere (for example, on the cogent platform, there are serial
  40  * ports on the motherboard which are used for the serial console - see
  41  * cogent/cma101/serial.[ch]).
  42  */
  43 #undef  CONFIG_CONS_ON_SMC              /* define if console on SMC */
  44 #define CONFIG_CONS_ON_SCC              /* define if console on SCC */
  45 #undef  CONFIG_CONS_NONE                /* define if console on something else*/
  46 #define CONFIG_CONS_INDEX       1       /* which serial channel for console */
  47
  48 #if defined(CONFIG_CONS_NONE) || defined(CONFIG_CONS_USE_EXTC)
  49 #define CONFIG_BAUDRATE         230400
  50 #else
  51 #define CONFIG_BAUDRATE         9600
  52 #endif
  53
  54 /*
  55  * select ethernet configuration
  56  *
  57  * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
  58  * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
  59  * for FCC)
  60  *
  61  * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
  62  * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset.
  63  */
  64 #undef  CONFIG_ETHER_ON_SCC             /* define if ether on SCC       */
  65 #define CONFIG_ETHER_ON_FCC             /* define if ether on FCC       */
  66 #undef  CONFIG_ETHER_NONE               /* define if ether on something else */
  67 #define CONFIG_ETHER_INDEX      1       /* which SCC/FCC channel for ethernet */
  68
  69 #define CONFIG_HAS_ETH1         1
  70 #define CONFIG_HAS_ETH2         1
  71
  72 #if defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 1)
  73
  74 /*
  75  * - Rx-CLK is CLK11
  76  * - Tx-CLK is CLK12
  77  * - RAM for BD/Buffers is on the 60x Bus (see 28-13)
  78  * - Enable Full Duplex in FSMR
  79  */
  80 # define CONFIG_SYS_CMXFCR_MASK1        (CMXFCR_FC1|CMXFCR_RF1CS_MSK|CMXFCR_TF1CS_MSK)
  81 # define CONFIG_SYS_CMXFCR_VALUE1       (CMXFCR_RF1CS_CLK11|CMXFCR_TF1CS_CLK12)
  82 # define CONFIG_SYS_CPMFCR_RAMTYPE      0
  83 # define CONFIG_SYS_FCC_PSMR            (FCC_PSMR_FDE|FCC_PSMR_LPB)
  84
  85 #elif defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 2)
  86
  87 /*
  88  * - Rx-CLK is CLK13
  89  * - Tx-CLK is CLK14
  90  * - RAM for BD/Buffers is on the 60x Bus (see 28-13)
  91  * - Enable Full Duplex in FSMR
  92  */
  93 # define CONFIG_SYS_CMXFCR_MASK2        (CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK)
  94 # define CONFIG_SYS_CMXFCR_VALUE2       (CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14)
  95 # define CONFIG_SYS_CPMFCR_RAMTYPE      0
  96 # define CONFIG_SYS_FCC_PSMR            (FCC_PSMR_FDE|FCC_PSMR_LPB)
  97
  98 #endif /* CONFIG_ETHER_ON_FCC, CONFIG_ETHER_INDEX */
  99
 100 /* system clock rate (CLKIN) - equal to the 60x and local bus speed */
 101 #define CONFIG_8260_CLKIN       100000000       /* in Hz */
 102
 103 #define CONFIG_BOOTDELAY        5       /* autoboot after 5 seconds     */
 104
 105 #define CONFIG_PREBOOT                                                          \
 106         "echo; "                                                                \
 107         "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS; "   \
 108         "echo"
 109
 110 #undef  CONFIG_BOOTARGS
 111 #define CONFIG_BOOTCOMMAND                                                      \
 112         "bootp; "                                                               \
 113         "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} "     \
 114         "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; "   \
 115         "bootm"
 116
 117 /*-----------------------------------------------------------------------
 118  * I2C/EEPROM/RTC configuration
 119  */
 120 #define CONFIG_SOFT_I2C                 /* Software I2C support enabled */
 121
 122 # define CONFIG_SYS_I2C_SPEED           50000
 123 # define CONFIG_SYS_I2C_SLAVE           0xFE
 124 /*
 125  * Software (bit-bang) I2C driver configuration
 126  */
 127 #define I2C_PORT        3               /* Port A=0, B=1, C=2, D=3 */
 128 #define I2C_ACTIVE      (iop->pdir |=  0x00010000)
 129 #define I2C_TRISTATE    (iop->pdir &= ~0x00010000)
 130 #define I2C_READ        ((iop->pdat & 0x00010000) != 0)
 131 #define I2C_SDA(bit)    if(bit) iop->pdat |=  0x00010000; \
 132                         else    iop->pdat &= ~0x00010000
 133 #define I2C_SCL(bit)    if(bit) iop->pdat |=  0x00020000; \
 134                         else    iop->pdat &= ~0x00020000
 135 #define I2C_DELAY       udelay(5)       /* 1/4 I2C clock duration */
 136
 137 #define CONFIG_RTC_PCF8563
 138 #define CONFIG_SYS_I2C_RTC_ADDR 0x51
 139
 140 #undef  CONFIG_WATCHDOG                 /* watchdog disabled            */
 141
 142 /*-----------------------------------------------------------------------
 143  * Disk-On-Chip configuration
 144  */
 145
 146 #define CONFIG_SYS_MAX_DOC_DEVICE       1       /* Max number of DOC devices    */
 147
 148 #define CONFIG_SYS_DOC_SUPPORT_2000
 149 #define CONFIG_SYS_DOC_SUPPORT_MILLENNIUM
 150
 151 /*-----------------------------------------------------------------------
 152  * Miscellaneous configuration options
 153  */
 154
 155 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download  */
 156 #undef  CONFIG_SYS_LOADS_BAUD_CHANGE            /* don't allow baudrate change  */
 157
 158 /*
 159  * BOOTP options
 160  */
 161 #define CONFIG_BOOTP_SUBNETMASK
 162 #define CONFIG_BOOTP_GATEWAY
 163 #define CONFIG_BOOTP_HOSTNAME
 164 #define CONFIG_BOOTP_BOOTPATH
 165 #define CONFIG_BOOTP_BOOTFILESIZE
 166
 167
 168 /*
 169  * Command line configuration.
 170  */
 171 #include <config_cmd_default.h>
 172
 173 #define CONFIG_CMD_BEDBUG
 174 #define CONFIG_CMD_DATE
 175 #define CONFIG_CMD_EEPROM
 176 #define CONFIG_CMD_I2C
 177
 178 #ifdef CONFIG_PCI
 179 #define CONFIG_PCI_INDIRECT_BRIDGE
 180     #define CONFIG_CMD_PCI
 181 #endif
 182
 183 /*
 184  * Miscellaneous configurable options
 185  */
 186 #define CONFIG_SYS_LONGHELP                     /* undef to save memory         */
 187 #define CONFIG_SYS_PROMPT       "=> "           /* Monitor Command Prompt       */
 188 #if defined(CONFIG_CMD_KGDB)
 189 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size      */
 190 #else
 191 #define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size      */
 192 #endif
 193 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
 194 #define CONFIG_SYS_MAXARGS      16              /* max number of command args   */
 195 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size    */
 196
 197 #define CONFIG_SYS_MEMTEST_START        0x0400000       /* memtest works on     */
 198 #define CONFIG_SYS_MEMTEST_END 0x0C00000        /* 4 ... 12 MB in DRAM  */
 199
 200 #define CONFIG_SYS_LOAD_ADDR    0x100000        /* default load address */
 201
 202 #define CONFIG_SYS_HZ           1000            /* decrementer freq: 1 ms ticks */
 203
 204 #define CONFIG_SYS_RESET_ADDRESS 0xFFF00100     /* "bad" address                */
 205
 206 #define CONFIG_LOOPW
 207
 208 /*
 209  * For booting Linux, the board info and command line data
 210  * have to be in the first 8 MB of memory, since this is
 211  * the maximum mapped by the Linux kernel during initialization.
 212  */
 213 #define CONFIG_SYS_BOOTMAPSZ            (8 << 20) /* Initial Memory map for Linux */
 214
 215 /*-----------------------------------------------------------------------
 216  * Flash configuration
 217  */
 218
 219 #define CONFIG_SYS_BOOTROM_BASE 0xFF800000
 220 #define CONFIG_SYS_BOOTROM_SIZE 0x00080000
 221 #define CONFIG_SYS_FLASH_BASE           0xFF000000
 222 #define CONFIG_SYS_FLASH_SIZE           0x00800000
 223
 224 /*-----------------------------------------------------------------------
 225  * FLASH organization
 226  */
 227 #define CONFIG_SYS_MAX_FLASH_BANKS      2       /* max num of memory banks      */
 228 #define CONFIG_SYS_MAX_FLASH_SECT       135     /* max num of sects on one chip */
 229
 230 #define CONFIG_SYS_FLASH_ERASE_TOUT     240000  /* Flash Erase Timeout (in ms)  */
 231 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (in ms)  */
 232
 233 /*-----------------------------------------------------------------------
 234  * Other areas to be mapped
 235  */
 236
 237 /* CS3: Dual ported SRAM */
 238 #define CONFIG_SYS_DPSRAM_BASE          0x40000000
 239 #define CONFIG_SYS_DPSRAM_SIZE          0x00100000
 240
 241 /* CS4: DiskOnChip */
 242 #define CONFIG_SYS_DOC_BASE             0xF4000000
 243 #define CONFIG_SYS_DOC_SIZE             0x00100000
 244
 245 /* CS5: FDC37C78 controller */
 246 #define CONFIG_SYS_FDC37C78_BASE        0xF1000000
 247 #define CONFIG_SYS_FDC37C78_SIZE        0x00100000
 248
 249 /* CS6: Board configuration registers */
 250 #define CONFIG_SYS_BCRS_BASE            0xF2000000
 251 #define CONFIG_SYS_BCRS_SIZE            0x00010000
 252
 253 /* CS7: VME Extended Access Range */
 254 #define CONFIG_SYS_VMEEAR_BASE          0x60000000
 255 #define CONFIG_SYS_VMEEAR_SIZE          0x01000000
 256
 257 /* CS8: VME Standard Access Range */
 258 #define CONFIG_SYS_VMESAR_BASE          0xFE000000
 259 #define CONFIG_SYS_VMESAR_SIZE          0x01000000
 260
 261 /* CS9: VME Short I/O Access Range */
 262 #define CONFIG_SYS_VMESIOAR_BASE        0xFD000000
 263 #define CONFIG_SYS_VMESIOAR_SIZE        0x01000000
 264
 265 /*-----------------------------------------------------------------------
 266  * Hard Reset Configuration Words
 267  *
 268  * if you change bits in the HRCW, you must also change the CONFIG_SYS_*
 269  * defines for the various registers affected by the HRCW e.g. changing
 270  * HRCW_DPPCxx requires you to also change CONFIG_SYS_SIUMCR.
 271  */
 272 #if defined(CONFIG_BOOT_ROM)
 273 #define CONFIG_SYS_HRCW_MASTER          (HRCW_CIP | HRCW_ISB100 | HRCW_BMS | \
 274                                  HRCW_BPS01 | HRCW_CS10PC01)
 275 #else
 276 #define CONFIG_SYS_HRCW_MASTER          (HRCW_CIP | HRCW_ISB100 | HRCW_BMS | HRCW_CS10PC01)
 277 #endif
 278
 279 /* no slaves so just fill with zeros */
 280 #define CONFIG_SYS_HRCW_SLAVE1          0
 281 #define CONFIG_SYS_HRCW_SLAVE2          0
 282 #define CONFIG_SYS_HRCW_SLAVE3          0
 283 #define CONFIG_SYS_HRCW_SLAVE4          0
 284 #define CONFIG_SYS_HRCW_SLAVE5          0
 285 #define CONFIG_SYS_HRCW_SLAVE6          0
 286 #define CONFIG_SYS_HRCW_SLAVE7          0
 287
 288 /*-----------------------------------------------------------------------
 289  * Internal Memory Mapped Register
 290  */
 291 #define CONFIG_SYS_IMMR         0xF0000000
 292
 293 /*-----------------------------------------------------------------------
 294  * Definitions for initial stack pointer and data area (in DPRAM)
 295  */
 296 #define CONFIG_SYS_INIT_RAM_ADDR        CONFIG_SYS_IMMR
 297 #define CONFIG_SYS_INIT_RAM_SIZE        0x4000  /* Size of used area in DPRAM   */
 298 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 299 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 300
 301 /*-----------------------------------------------------------------------
 302  * Start addresses for the final memory configuration
 303  * (Set up by the startup code)
 304  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 305  *
 306  * 60x SDRAM is mapped at CONFIG_SYS_SDRAM_BASE.
 307  */
 308 #define CONFIG_SYS_SDRAM_BASE           0x00000000
 309 #define CONFIG_SYS_SDRAM_MAX_SIZE       0x08000000      /* max. 128 MB          */
 310 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
 311 #define CONFIG_SYS_MONITOR_LEN          (256 << 10)     /* Reserve 256 kB for Monitor */
 312 #define CONFIG_SYS_MALLOC_LEN           (128 << 10)     /* Reserve 128 kB for malloc()*/
 313
 314 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
 315 # define CONFIG_SYS_RAMBOOT
 316 #endif
 317
 318 #ifdef  CONFIG_PCI
 319 #define CONFIG_PCI_PNP
 320 #define CONFIG_EEPRO100
 321 #define CONFIG_SYS_RX_ETH_BUFFER        8               /* use 8 rx buffer on eepro100  */
 322 #endif
 323
 324 #if 0
 325 /* environment is in Flash */
 326 #define CONFIG_ENV_IS_IN_FLASH  1
 327 #ifdef CONFIG_BOOT_ROM
 328 # define CONFIG_ENV_ADDR                (CONFIG_SYS_FLASH_BASE+0x70000)
 329 # define CONFIG_ENV_SIZE                0x10000
 330 # define CONFIG_ENV_SECT_SIZE   0x10000
 331 #endif
 332 #else
 333 /* environment is in EEPROM */
 334 #define CONFIG_ENV_IS_IN_EEPROM 1
 335 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x58    /* EEPROM X24C16                */
 336 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
 337 /* mask of address bits that overflow into the "EEPROM chip address"    */
 338 #define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW     0x07
 339 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS       4
 340 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   10      /* and takes up to 10 msec */
 341 #define CONFIG_ENV_OFFSET               512
 342 #define CONFIG_ENV_SIZE         (2048 - 512)
 343 #endif
 344
 345 /*-----------------------------------------------------------------------
 346  * Cache Configuration
 347  */
 348 #define CONFIG_SYS_CACHELINE_SIZE       32      /* For MPC8260 CPU              */
 349 #if defined(CONFIG_CMD_KGDB)
 350 # define CONFIG_SYS_CACHELINE_SHIFT     5       /* log base 2 of the above value */
 351 #endif
 352
 353 /*-----------------------------------------------------------------------
 354  * HIDx - Hardware Implementation-dependent Registers                    2-11
 355  *-----------------------------------------------------------------------
 356  * HID0 also contains cache control - initially enable both caches and
 357  * invalidate contents, then the final state leaves only the instruction
 358  * cache enabled. Note that Power-On and Hard reset invalidate the caches,
 359  * but Soft reset does not.
 360  *
 361  * HID1 has only read-only information - nothing to set.
 362  */
 363 #define CONFIG_SYS_HID0_INIT    (HID0_ICE|HID0_DCE|HID0_ICFI|\
 364                          HID0_DCI|HID0_IFEM|HID0_ABE)
 365 #define CONFIG_SYS_HID0_FINAL   (HID0_IFEM|HID0_ABE)
 366 #define CONFIG_SYS_HID2 0
 367
 368 /*-----------------------------------------------------------------------
 369  * RMR - Reset Mode Register                                     5-5
 370  *-----------------------------------------------------------------------
 371  * turn on Checkstop Reset Enable
 372  */
 373 #define CONFIG_SYS_RMR          RMR_CSRE
 374
 375 /*-----------------------------------------------------------------------
 376  * BCR - Bus Configuration                                       4-25
 377  *-----------------------------------------------------------------------
 378  */
 379 #define BCR_APD01       0x10000000
 380 #define CONFIG_SYS_BCR          (BCR_APD01|BCR_ETM|BCR_LETM)    /* 8260 mode */
 381
 382 /*-----------------------------------------------------------------------
 383  * SIUMCR - SIU Module Configuration                             4-31
 384  *-----------------------------------------------------------------------
 385  */
 386 #define CONFIG_SYS_SIUMCR       (SIUMCR_BBD|SIUMCR_DPPC00|SIUMCR_APPC10|\
 387                          SIUMCR_CS10PC01|SIUMCR_BCTLC10)
 388
 389 /*-----------------------------------------------------------------------
 390  * SYPCR - System Protection Control                             4-35
 391  * SYPCR can only be written once after reset!
 392  *-----------------------------------------------------------------------
 393  * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
 394  */
 395 #if defined(CONFIG_WATCHDOG)
 396 #define CONFIG_SYS_SYPCR        (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
 397                          SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE)
 398 #else
 399 #define CONFIG_SYS_SYPCR        (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
 400                          SYPCR_SWRI|SYPCR_SWP)
 401 #endif /* CONFIG_WATCHDOG */
 402
 403 /*-----------------------------------------------------------------------
 404  * TMCNTSC - Time Counter Status and Control                     4-40
 405  *-----------------------------------------------------------------------
 406  * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
 407  * and enable Time Counter
 408  */
 409 #define CONFIG_SYS_TMCNTSC      (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
 410
 411 /*-----------------------------------------------------------------------
 412  * PISCR - Periodic Interrupt Status and Control                 4-42
 413  *-----------------------------------------------------------------------
 414  * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
 415  * Periodic timer
 416  */
 417 #define CONFIG_SYS_PISCR        (PISCR_PS|PISCR_PTF|PISCR_PTE)
 418
 419 /*-----------------------------------------------------------------------
 420  * SCCR - System Clock Control                                   9-8
 421  *-----------------------------------------------------------------------
 422  * Ensure DFBRG is Divide by 16
 423  */
 424 #define CONFIG_SYS_SCCR SCCR_DFBRG01
 425
 426 /*-----------------------------------------------------------------------
 427  * RCCR - RISC Controller Configuration                         13-7
 428  *-----------------------------------------------------------------------
 429  */
 430 #define CONFIG_SYS_RCCR 0
 431
 432 #define CONFIG_SYS_MIN_AM_MASK 0xC0000000
 433
 434 /*
 435  * we use the same values for 32 MB, 128 MB and 256 MB SDRAM
 436  * refresh rate = 7.68 uS (100 MHz Bus Clock)
 437  */
 438
 439 /*-----------------------------------------------------------------------
 440  * MPTPR - Memory Refresh Timer Prescaler Register              10-18
 441  *-----------------------------------------------------------------------
 442  */
 443 #define CONFIG_SYS_MPTPR        0x2000
 444
 445 /*-----------------------------------------------------------------------
 446  * PSRT - Refresh Timer Register                                10-16
 447  *-----------------------------------------------------------------------
 448  */
 449 #define CONFIG_SYS_PSRT 0x16
 450
 451 /*-----------------------------------------------------------------------
 452  * PSRT - SDRAM Mode Register                                   10-10
 453  *-----------------------------------------------------------------------
 454  */
 455
 456         /* SDRAM initialization values for 8-column chips
 457          */
 458 #define CONFIG_SYS_OR2_8COL     (CONFIG_SYS_MIN_AM_MASK         |\
 459                          ORxS_BPD_4                     |\
 460                          ORxS_ROWST_PBI0_A9             |\
 461                          ORxS_NUMR_12)
 462
 463 #define CONFIG_SYS_PSDMR_8COL   (PSDMR_SDAM_A13_IS_A5           |\
 464                          PSDMR_BSMA_A14_A16             |\
 465                          PSDMR_SDA10_PBI0_A10           |\
 466                          PSDMR_RFRC_7_CLK               |\
 467                          PSDMR_PRETOACT_2W              |\
 468                          PSDMR_ACTTORW_2W               |\
 469                          PSDMR_LDOTOPRE_1C              |\
 470                          PSDMR_WRC_1C                   |\
 471                          PSDMR_CL_2)
 472
 473         /* SDRAM initialization values for 9-column chips
 474          */
 475 #define CONFIG_SYS_OR2_9COL     (CONFIG_SYS_MIN_AM_MASK         |\
 476                          ORxS_BPD_4                     |\
 477                          ORxS_ROWST_PBI0_A7             |\
 478                          ORxS_NUMR_13)
 479
 480 #define CONFIG_SYS_PSDMR_9COL   (PSDMR_SDAM_A14_IS_A5           |\
 481                          PSDMR_BSMA_A13_A15             |\
 482                          PSDMR_SDA10_PBI0_A9            |\
 483                          PSDMR_RFRC_7_CLK               |\
 484                          PSDMR_PRETOACT_2W              |\
 485                          PSDMR_ACTTORW_2W               |\
 486                          PSDMR_LDOTOPRE_1C              |\
 487                          PSDMR_WRC_1C                   |\
 488                          PSDMR_CL_2)
 489
 490         /* SDRAM initialization values for 10-column chips
 491          */
 492 #define CONFIG_SYS_OR2_10COL    (CONFIG_SYS_MIN_AM_MASK         |\
 493                          ORxS_BPD_4                     |\
 494                          ORxS_ROWST_PBI1_A4             |\
 495                          ORxS_NUMR_13)
 496
 497 #define CONFIG_SYS_PSDMR_10COL  (PSDMR_PBI                      |\
 498                          PSDMR_SDAM_A17_IS_A5           |\
 499                          PSDMR_BSMA_A13_A15             |\
 500                          PSDMR_SDA10_PBI1_A6            |\
 501                          PSDMR_RFRC_7_CLK               |\
 502                          PSDMR_PRETOACT_2W              |\
 503                          PSDMR_ACTTORW_2W               |\
 504                          PSDMR_LDOTOPRE_1C              |\
 505                          PSDMR_WRC_1C                   |\
 506                          PSDMR_CL_2)
 507
 508 /*
 509  * Init Memory Controller:
 510  *
 511  * Bank Bus     Machine PortSz  Device
 512  * ---- ---     ------- ------  ------
 513  *  0   60x     GPCM    8  bit  Boot ROM
 514  *  1   60x     GPCM    64 bit  FLASH
 515  *  2   60x     SDRAM   64 bit  SDRAM
 516  *
 517  */
 518
 519 #define CONFIG_SYS_MRS_OFFS     0x00000000
 520
 521 #ifdef CONFIG_BOOT_ROM
 522 /* Bank 0 - Boot ROM
 523  */
 524 #define CONFIG_SYS_BR0_PRELIM   ((CONFIG_SYS_BOOTROM_BASE & BRx_BA_MSK)|\
 525                          BRx_PS_8                       |\
 526                          BRx_MS_GPCM_P                  |\
 527                          BRx_V)
 528
 529 #define CONFIG_SYS_OR0_PRELIM   (P2SZ_TO_AM(CONFIG_SYS_BOOTROM_SIZE)    |\
 530                          ORxG_CSNT                      |\
 531                          ORxG_ACS_DIV1                  |\
 532                          ORxG_SCY_5_CLK                 |\
 533                          ORxU_EHTR_8IDLE)
 534
 535 /* Bank 1 - FLASH
 536  */
 537 #define CONFIG_SYS_BR1_PRELIM   ((CONFIG_SYS_FLASH_BASE & BRx_BA_MSK)   |\
 538                          BRx_PS_64                      |\
 539                          BRx_MS_GPCM_P                  |\
 540                          BRx_V)
 541
 542 #define CONFIG_SYS_OR1_PRELIM   (P2SZ_TO_AM(CONFIG_SYS_FLASH_SIZE)      |\
 543                          ORxG_CSNT                      |\
 544                          ORxG_ACS_DIV1                  |\
 545                          ORxG_SCY_5_CLK                 |\
 546                          ORxU_EHTR_8IDLE)
 547
 548 #else /* CONFIG_BOOT_ROM */
 549 /* Bank 0 - FLASH
 550  */
 551 #define CONFIG_SYS_BR0_PRELIM   ((CONFIG_SYS_FLASH_BASE & BRx_BA_MSK)   |\
 552                          BRx_PS_64                      |\
 553                          BRx_MS_GPCM_P                  |\
 554                          BRx_V)
 555
 556 #define CONFIG_SYS_OR0_PRELIM   (P2SZ_TO_AM(CONFIG_SYS_FLASH_SIZE)      |\
 557                          ORxG_CSNT                      |\
 558                          ORxG_ACS_DIV1                  |\
 559                          ORxG_SCY_5_CLK                 |\
 560                          ORxU_EHTR_8IDLE)
 561
 562 /* Bank 1 - Boot ROM
 563  */
 564 #define CONFIG_SYS_BR1_PRELIM   ((CONFIG_SYS_BOOTROM_BASE & BRx_BA_MSK)|\
 565                          BRx_PS_8                       |\
 566                          BRx_MS_GPCM_P                  |\
 567                          BRx_V)
 568
 569 #define CONFIG_SYS_OR1_PRELIM   (P2SZ_TO_AM(CONFIG_SYS_BOOTROM_SIZE)    |\
 570                          ORxG_CSNT                      |\
 571                          ORxG_ACS_DIV1                  |\
 572                          ORxG_SCY_5_CLK                 |\
 573                          ORxU_EHTR_8IDLE)
 574
 575 #endif /* CONFIG_BOOT_ROM */
 576
 577
 578 /* Bank 2 - 60x bus SDRAM
 579  */
 580 #ifndef CONFIG_SYS_RAMBOOT
 581 #define CONFIG_SYS_BR2_PRELIM   ((CONFIG_SYS_SDRAM_BASE & BRx_BA_MSK)   |\
 582                          BRx_PS_64                      |\
 583                          BRx_MS_SDRAM_P                 |\
 584                          BRx_V)
 585
 586 #define CONFIG_SYS_OR2_PRELIM    CONFIG_SYS_OR2_8COL
 587
 588 #define CONFIG_SYS_PSDMR         CONFIG_SYS_PSDMR_8COL
 589 #endif /* CONFIG_SYS_RAMBOOT */
 590
 591 /* Bank 3 - Dual Ported SRAM
 592  */
 593 #define CONFIG_SYS_BR3_PRELIM   ((CONFIG_SYS_DPSRAM_BASE & BRx_BA_MSK) |\
 594                          BRx_PS_16                      |\
 595                          BRx_MS_GPCM_P                  |\
 596                          BRx_V)
 597
 598 #define CONFIG_SYS_OR3_PRELIM   (P2SZ_TO_AM(CONFIG_SYS_DPSRAM_SIZE)     |\
 599                          ORxG_CSNT                      |\
 600                          ORxG_ACS_DIV1                  |\
 601                          ORxG_SCY_7_CLK                 |\
 602                          ORxG_SETA)
 603
 604 /* Bank 4 - DiskOnChip
 605  */
 606 #define CONFIG_SYS_BR4_PRELIM   ((CONFIG_SYS_DOC_BASE & BRx_BA_MSK)     |\
 607                          BRx_PS_8                       |\
 608                          BRx_MS_GPCM_P                  |\
 609                          BRx_V)
 610
 611 #define CONFIG_SYS_OR4_PRELIM   (P2SZ_TO_AM(CONFIG_SYS_DOC_SIZE)        |\
 612                          ORxG_CSNT                      |\
 613                          ORxG_ACS_DIV2                  |\
 614                          ORxG_SCY_9_CLK                 |\
 615                          ORxU_EHTR_8IDLE)
 616
 617 /* Bank 5 - FDC37C78 controller
 618  */
 619 #define CONFIG_SYS_BR5_PRELIM   ((CONFIG_SYS_FDC37C78_BASE & BRx_BA_MSK) |\
 620                          BRx_PS_8                         |\
 621                          BRx_MS_GPCM_P                    |\
 622                          BRx_V)
 623
 624 #define CONFIG_SYS_OR5_PRELIM   (P2SZ_TO_AM(CONFIG_SYS_FDC37C78_SIZE)     |\
 625                          ORxG_ACS_DIV2                    |\
 626                          ORxG_SCY_10_CLK                  |\
 627                          ORxU_EHTR_8IDLE)
 628
 629 /* Bank 6 - Board control registers
 630  */
 631 #define CONFIG_SYS_BR6_PRELIM   ((CONFIG_SYS_BCRS_BASE & BRx_BA_MSK)    |\
 632                          BRx_PS_8                       |\
 633                          BRx_MS_GPCM_P                  |\
 634                          BRx_V)
 635
 636 #define CONFIG_SYS_OR6_PRELIM   (P2SZ_TO_AM(CONFIG_SYS_BCRS_SIZE)       |\
 637                          ORxG_CSNT                      |\
 638                          ORxG_SCY_7_CLK)
 639
 640 /* Bank 7 - VME Extended Access Range
 641  */
 642 #define CONFIG_SYS_BR7_PRELIM   ((CONFIG_SYS_VMEEAR_BASE & BRx_BA_MSK) |\
 643                          BRx_PS_32                      |\
 644                          BRx_MS_GPCM_P                  |\
 645                          BRx_V)
 646
 647 #define CONFIG_SYS_OR7_PRELIM   (P2SZ_TO_AM(CONFIG_SYS_VMEEAR_SIZE)     |\
 648                          ORxG_CSNT                      |\
 649                          ORxG_ACS_DIV1                  |\
 650                          ORxG_SCY_7_CLK                 |\
 651                          ORxG_SETA)
 652
 653 /* Bank 8 - VME Standard Access Range
 654  */
 655 #define CONFIG_SYS_BR8_PRELIM   ((CONFIG_SYS_VMESAR_BASE & BRx_BA_MSK) |\
 656                          BRx_PS_16                      |\
 657                          BRx_MS_GPCM_P                  |\
 658                          BRx_V)
 659
 660 #define CONFIG_SYS_OR8_PRELIM   (P2SZ_TO_AM(CONFIG_SYS_VMESAR_SIZE)     |\
 661                          ORxG_CSNT                      |\
 662                          ORxG_ACS_DIV1                  |\
 663                          ORxG_SCY_7_CLK                 |\
 664                          ORxG_SETA)
 665
 666 /* Bank 9 - VME Short I/O Access Range
 667  */
 668 #define CONFIG_SYS_BR9_PRELIM   ((CONFIG_SYS_VMESIOAR_BASE & BRx_BA_MSK) |\
 669                          BRx_PS_16                        |\
 670                          BRx_MS_GPCM_P                    |\
 671                          BRx_V)
 672
 673 #define CONFIG_SYS_OR9_PRELIM   (P2SZ_TO_AM(CONFIG_SYS_VMESIOAR_SIZE)     |\
 674                          ORxG_CSNT                        |\
 675                          ORxG_ACS_DIV1                    |\
 676                          ORxG_SCY_7_CLK                   |\
 677                          ORxG_SETA)
 678
 679 #endif  /* __CONFIG_H */