Merge branch 'master' of git://git.denx.de/u-boot-imx
[platform/kernel/u-boot.git] / include / configs / CPU87.h
1 /*
2  * (C) Copyright 2001-2005
3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4  *
5  * See file CREDITS for list of people who contributed to this
6  * project.
7  *
8  * This program is free software; you can redistribute it and/or
9  * modify it under the terms of the GNU General Public License as
10  * published by the Free Software Foundation; either version 2 of
11  * the License, or (at your option) any later version.
12  *
13  * This program is distributed in the hope that it will be useful,
14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
16  * GNU General Public License for more details.
17  *
18  * You should have received a copy of the GNU General Public License
19  * along with this program; if not, write to the Free Software
20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21  * MA 02111-1307 USA
22  */
23
24 /*
25  * board/config.h - configuration options, board specific
26  */
27
28 #ifndef __CONFIG_H
29 #define __CONFIG_H
30
31 /*
32  * High Level Configuration Options
33  * (easy to change)
34  */
35
36 #define CONFIG_MPC8260          1       /* This is an MPC8260 CPU               */
37 #define CONFIG_CPU87            1       /* ...on a CPU87 board  */
38 #define CONFIG_PCI
39 #define CONFIG_CPM2             1       /* Has a CPM2 */
40
41 #ifdef CONFIG_BOOT_ROM
42 #define CONFIG_SYS_TEXT_BASE    0xFF800000
43 #else
44 #define CONFIG_SYS_TEXT_BASE    0xFF000000
45 #endif
46
47 /*
48  * select serial console configuration
49  *
50  * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
51  * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
52  * for SCC).
53  *
54  * if CONFIG_CONS_NONE is defined, then the serial console routines must
55  * defined elsewhere (for example, on the cogent platform, there are serial
56  * ports on the motherboard which are used for the serial console - see
57  * cogent/cma101/serial.[ch]).
58  */
59 #undef  CONFIG_CONS_ON_SMC              /* define if console on SMC */
60 #define CONFIG_CONS_ON_SCC              /* define if console on SCC */
61 #undef  CONFIG_CONS_NONE                /* define if console on something else*/
62 #define CONFIG_CONS_INDEX       1       /* which serial channel for console */
63
64 #if defined(CONFIG_CONS_NONE) || defined(CONFIG_CONS_USE_EXTC)
65 #define CONFIG_BAUDRATE         230400
66 #else
67 #define CONFIG_BAUDRATE         9600
68 #endif
69
70 /*
71  * select ethernet configuration
72  *
73  * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
74  * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
75  * for FCC)
76  *
77  * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
78  * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset.
79  */
80 #undef  CONFIG_ETHER_ON_SCC             /* define if ether on SCC       */
81 #define CONFIG_ETHER_ON_FCC             /* define if ether on FCC       */
82 #undef  CONFIG_ETHER_NONE               /* define if ether on something else */
83 #define CONFIG_ETHER_INDEX      1       /* which SCC/FCC channel for ethernet */
84
85 #define CONFIG_HAS_ETH1         1
86 #define CONFIG_HAS_ETH2         1
87
88 #if defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 1)
89
90 /*
91  * - Rx-CLK is CLK11
92  * - Tx-CLK is CLK12
93  * - RAM for BD/Buffers is on the 60x Bus (see 28-13)
94  * - Enable Full Duplex in FSMR
95  */
96 # define CONFIG_SYS_CMXFCR_MASK (CMXFCR_FC1|CMXFCR_RF1CS_MSK|CMXFCR_TF1CS_MSK)
97 # define CONFIG_SYS_CMXFCR_VALUE        (CMXFCR_RF1CS_CLK11|CMXFCR_TF1CS_CLK12)
98 # define CONFIG_SYS_CPMFCR_RAMTYPE      0
99 # define CONFIG_SYS_FCC_PSMR            (FCC_PSMR_FDE|FCC_PSMR_LPB)
100
101 #elif defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 2)
102
103 /*
104  * - Rx-CLK is CLK13
105  * - Tx-CLK is CLK14
106  * - RAM for BD/Buffers is on the 60x Bus (see 28-13)
107  * - Enable Full Duplex in FSMR
108  */
109 # define CONFIG_SYS_CMXFCR_MASK (CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK)
110 # define CONFIG_SYS_CMXFCR_VALUE        (CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14)
111 # define CONFIG_SYS_CPMFCR_RAMTYPE      0
112 # define CONFIG_SYS_FCC_PSMR            (FCC_PSMR_FDE|FCC_PSMR_LPB)
113
114 #endif /* CONFIG_ETHER_ON_FCC, CONFIG_ETHER_INDEX */
115
116 /* system clock rate (CLKIN) - equal to the 60x and local bus speed */
117 #define CONFIG_8260_CLKIN       100000000       /* in Hz */
118
119 #define CONFIG_BOOTDELAY        5       /* autoboot after 5 seconds     */
120
121 #define CONFIG_PREBOOT                                                          \
122         "echo; "                                                                \
123         "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS; "   \
124         "echo"
125
126 #undef  CONFIG_BOOTARGS
127 #define CONFIG_BOOTCOMMAND                                                      \
128         "bootp; "                                                               \
129         "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} "     \
130         "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; "   \
131         "bootm"
132
133 /*-----------------------------------------------------------------------
134  * I2C/EEPROM/RTC configuration
135  */
136 #define CONFIG_SOFT_I2C                 /* Software I2C support enabled */
137
138 # define CONFIG_SYS_I2C_SPEED           50000
139 # define CONFIG_SYS_I2C_SLAVE           0xFE
140 /*
141  * Software (bit-bang) I2C driver configuration
142  */
143 #define I2C_PORT        3               /* Port A=0, B=1, C=2, D=3 */
144 #define I2C_ACTIVE      (iop->pdir |=  0x00010000)
145 #define I2C_TRISTATE    (iop->pdir &= ~0x00010000)
146 #define I2C_READ        ((iop->pdat & 0x00010000) != 0)
147 #define I2C_SDA(bit)    if(bit) iop->pdat |=  0x00010000; \
148                         else    iop->pdat &= ~0x00010000
149 #define I2C_SCL(bit)    if(bit) iop->pdat |=  0x00020000; \
150                         else    iop->pdat &= ~0x00020000
151 #define I2C_DELAY       udelay(5)       /* 1/4 I2C clock duration */
152
153 #define CONFIG_RTC_PCF8563
154 #define CONFIG_SYS_I2C_RTC_ADDR 0x51
155
156 #undef  CONFIG_WATCHDOG                 /* watchdog disabled            */
157
158 /*-----------------------------------------------------------------------
159  * Disk-On-Chip configuration
160  */
161
162 #define CONFIG_SYS_MAX_DOC_DEVICE       1       /* Max number of DOC devices    */
163
164 #define CONFIG_SYS_DOC_SUPPORT_2000
165 #define CONFIG_SYS_DOC_SUPPORT_MILLENNIUM
166
167 /*-----------------------------------------------------------------------
168  * Miscellaneous configuration options
169  */
170
171 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download  */
172 #undef  CONFIG_SYS_LOADS_BAUD_CHANGE            /* don't allow baudrate change  */
173
174 /*
175  * BOOTP options
176  */
177 #define CONFIG_BOOTP_SUBNETMASK
178 #define CONFIG_BOOTP_GATEWAY
179 #define CONFIG_BOOTP_HOSTNAME
180 #define CONFIG_BOOTP_BOOTPATH
181 #define CONFIG_BOOTP_BOOTFILESIZE
182
183
184 /*
185  * Command line configuration.
186  */
187 #include <config_cmd_default.h>
188
189 #define CONFIG_CMD_BEDBUG
190 #define CONFIG_CMD_DATE
191 #define CONFIG_CMD_EEPROM
192 #define CONFIG_CMD_I2C
193
194 #ifdef CONFIG_PCI
195     #define CONFIG_CMD_PCI
196 #endif
197
198 /*
199  * Miscellaneous configurable options
200  */
201 #define CONFIG_SYS_LONGHELP                     /* undef to save memory         */
202 #define CONFIG_SYS_PROMPT       "=> "           /* Monitor Command Prompt       */
203 #if defined(CONFIG_CMD_KGDB)
204 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size      */
205 #else
206 #define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size      */
207 #endif
208 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
209 #define CONFIG_SYS_MAXARGS      16              /* max number of command args   */
210 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size    */
211
212 #define CONFIG_SYS_MEMTEST_START        0x0400000       /* memtest works on     */
213 #define CONFIG_SYS_MEMTEST_END 0x0C00000        /* 4 ... 12 MB in DRAM  */
214
215 #define CONFIG_SYS_LOAD_ADDR    0x100000        /* default load address */
216
217 #define CONFIG_SYS_HZ           1000            /* decrementer freq: 1 ms ticks */
218
219 #define CONFIG_SYS_BAUDRATE_TABLE       { 9600, 19200, 38400, 57600, 115200 }
220
221 #define CONFIG_SYS_RESET_ADDRESS 0xFFF00100     /* "bad" address                */
222
223 #define CONFIG_LOOPW
224
225 /*
226  * For booting Linux, the board info and command line data
227  * have to be in the first 8 MB of memory, since this is
228  * the maximum mapped by the Linux kernel during initialization.
229  */
230 #define CONFIG_SYS_BOOTMAPSZ            (8 << 20) /* Initial Memory map for Linux */
231
232 /*-----------------------------------------------------------------------
233  * Flash configuration
234  */
235
236 #define CONFIG_SYS_BOOTROM_BASE 0xFF800000
237 #define CONFIG_SYS_BOOTROM_SIZE 0x00080000
238 #define CONFIG_SYS_FLASH_BASE           0xFF000000
239 #define CONFIG_SYS_FLASH_SIZE           0x00800000
240
241 /*-----------------------------------------------------------------------
242  * FLASH organization
243  */
244 #define CONFIG_SYS_MAX_FLASH_BANKS      2       /* max num of memory banks      */
245 #define CONFIG_SYS_MAX_FLASH_SECT       135     /* max num of sects on one chip */
246
247 #define CONFIG_SYS_FLASH_ERASE_TOUT     240000  /* Flash Erase Timeout (in ms)  */
248 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (in ms)  */
249
250 /*-----------------------------------------------------------------------
251  * Other areas to be mapped
252  */
253
254 /* CS3: Dual ported SRAM */
255 #define CONFIG_SYS_DPSRAM_BASE          0x40000000
256 #define CONFIG_SYS_DPSRAM_SIZE          0x00100000
257
258 /* CS4: DiskOnChip */
259 #define CONFIG_SYS_DOC_BASE             0xF4000000
260 #define CONFIG_SYS_DOC_SIZE             0x00100000
261
262 /* CS5: FDC37C78 controller */
263 #define CONFIG_SYS_FDC37C78_BASE        0xF1000000
264 #define CONFIG_SYS_FDC37C78_SIZE        0x00100000
265
266 /* CS6: Board configuration registers */
267 #define CONFIG_SYS_BCRS_BASE            0xF2000000
268 #define CONFIG_SYS_BCRS_SIZE            0x00010000
269
270 /* CS7: VME Extended Access Range */
271 #define CONFIG_SYS_VMEEAR_BASE          0x60000000
272 #define CONFIG_SYS_VMEEAR_SIZE          0x01000000
273
274 /* CS8: VME Standard Access Range */
275 #define CONFIG_SYS_VMESAR_BASE          0xFE000000
276 #define CONFIG_SYS_VMESAR_SIZE          0x01000000
277
278 /* CS9: VME Short I/O Access Range */
279 #define CONFIG_SYS_VMESIOAR_BASE        0xFD000000
280 #define CONFIG_SYS_VMESIOAR_SIZE        0x01000000
281
282 /*-----------------------------------------------------------------------
283  * Hard Reset Configuration Words
284  *
285  * if you change bits in the HRCW, you must also change the CONFIG_SYS_*
286  * defines for the various registers affected by the HRCW e.g. changing
287  * HRCW_DPPCxx requires you to also change CONFIG_SYS_SIUMCR.
288  */
289 #if defined(CONFIG_BOOT_ROM)
290 #define CONFIG_SYS_HRCW_MASTER          (HRCW_CIP | HRCW_ISB100 | HRCW_BMS | \
291                                  HRCW_BPS01 | HRCW_CS10PC01)
292 #else
293 #define CONFIG_SYS_HRCW_MASTER          (HRCW_CIP | HRCW_ISB100 | HRCW_BMS | HRCW_CS10PC01)
294 #endif
295
296 /* no slaves so just fill with zeros */
297 #define CONFIG_SYS_HRCW_SLAVE1          0
298 #define CONFIG_SYS_HRCW_SLAVE2          0
299 #define CONFIG_SYS_HRCW_SLAVE3          0
300 #define CONFIG_SYS_HRCW_SLAVE4          0
301 #define CONFIG_SYS_HRCW_SLAVE5          0
302 #define CONFIG_SYS_HRCW_SLAVE6          0
303 #define CONFIG_SYS_HRCW_SLAVE7          0
304
305 /*-----------------------------------------------------------------------
306  * Internal Memory Mapped Register
307  */
308 #define CONFIG_SYS_IMMR         0xF0000000
309
310 /*-----------------------------------------------------------------------
311  * Definitions for initial stack pointer and data area (in DPRAM)
312  */
313 #define CONFIG_SYS_INIT_RAM_ADDR        CONFIG_SYS_IMMR
314 #define CONFIG_SYS_INIT_RAM_END 0x4000  /* End of used area in DPRAM    */
315 #define CONFIG_SYS_GBL_DATA_SIZE        128 /* size in bytes reserved for initial data*/
316 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
317 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
318
319 /*-----------------------------------------------------------------------
320  * Start addresses for the final memory configuration
321  * (Set up by the startup code)
322  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
323  *
324  * 60x SDRAM is mapped at CONFIG_SYS_SDRAM_BASE.
325  */
326 #define CONFIG_SYS_SDRAM_BASE           0x00000000
327 #define CONFIG_SYS_SDRAM_MAX_SIZE       0x08000000      /* max. 128 MB          */
328 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
329 #define CONFIG_SYS_MONITOR_LEN          (256 << 10)     /* Reserve 256 kB for Monitor */
330 #define CONFIG_SYS_MALLOC_LEN           (128 << 10)     /* Reserve 128 kB for malloc()*/
331
332 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
333 # define CONFIG_SYS_RAMBOOT
334 #endif
335
336 #ifdef  CONFIG_PCI
337 #define CONFIG_PCI_PNP
338 #define CONFIG_EEPRO100
339 #define CONFIG_SYS_RX_ETH_BUFFER        8               /* use 8 rx buffer on eepro100  */
340 #endif
341
342 #if 0
343 /* environment is in Flash */
344 #define CONFIG_ENV_IS_IN_FLASH  1
345 #ifdef CONFIG_BOOT_ROM
346 # define CONFIG_ENV_ADDR                (CONFIG_SYS_FLASH_BASE+0x70000)
347 # define CONFIG_ENV_SIZE                0x10000
348 # define CONFIG_ENV_SECT_SIZE   0x10000
349 #endif
350 #else
351 /* environment is in EEPROM */
352 #define CONFIG_ENV_IS_IN_EEPROM 1
353 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x58    /* EEPROM X24C16                */
354 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
355 /* mask of address bits that overflow into the "EEPROM chip address"    */
356 #define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW     0x07
357 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS       4
358 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   10      /* and takes up to 10 msec */
359 #define CONFIG_ENV_OFFSET               512
360 #define CONFIG_ENV_SIZE         (2048 - 512)
361 #endif
362
363 /*-----------------------------------------------------------------------
364  * Cache Configuration
365  */
366 #define CONFIG_SYS_CACHELINE_SIZE       32      /* For MPC8260 CPU              */
367 #if defined(CONFIG_CMD_KGDB)
368 # define CONFIG_SYS_CACHELINE_SHIFT     5       /* log base 2 of the above value */
369 #endif
370
371 /*-----------------------------------------------------------------------
372  * HIDx - Hardware Implementation-dependent Registers                    2-11
373  *-----------------------------------------------------------------------
374  * HID0 also contains cache control - initially enable both caches and
375  * invalidate contents, then the final state leaves only the instruction
376  * cache enabled. Note that Power-On and Hard reset invalidate the caches,
377  * but Soft reset does not.
378  *
379  * HID1 has only read-only information - nothing to set.
380  */
381 #define CONFIG_SYS_HID0_INIT    (HID0_ICE|HID0_DCE|HID0_ICFI|\
382                          HID0_DCI|HID0_IFEM|HID0_ABE)
383 #define CONFIG_SYS_HID0_FINAL   (HID0_IFEM|HID0_ABE)
384 #define CONFIG_SYS_HID2 0
385
386 /*-----------------------------------------------------------------------
387  * RMR - Reset Mode Register                                     5-5
388  *-----------------------------------------------------------------------
389  * turn on Checkstop Reset Enable
390  */
391 #define CONFIG_SYS_RMR          RMR_CSRE
392
393 /*-----------------------------------------------------------------------
394  * BCR - Bus Configuration                                       4-25
395  *-----------------------------------------------------------------------
396  */
397 #define BCR_APD01       0x10000000
398 #define CONFIG_SYS_BCR          (BCR_APD01|BCR_ETM|BCR_LETM)    /* 8260 mode */
399
400 /*-----------------------------------------------------------------------
401  * SIUMCR - SIU Module Configuration                             4-31
402  *-----------------------------------------------------------------------
403  */
404 #define CONFIG_SYS_SIUMCR       (SIUMCR_BBD|SIUMCR_DPPC00|SIUMCR_APPC10|\
405                          SIUMCR_CS10PC01|SIUMCR_BCTLC10)
406
407 /*-----------------------------------------------------------------------
408  * SYPCR - System Protection Control                             4-35
409  * SYPCR can only be written once after reset!
410  *-----------------------------------------------------------------------
411  * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
412  */
413 #if defined(CONFIG_WATCHDOG)
414 #define CONFIG_SYS_SYPCR        (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
415                          SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE)
416 #else
417 #define CONFIG_SYS_SYPCR        (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
418                          SYPCR_SWRI|SYPCR_SWP)
419 #endif /* CONFIG_WATCHDOG */
420
421 /*-----------------------------------------------------------------------
422  * TMCNTSC - Time Counter Status and Control                     4-40
423  *-----------------------------------------------------------------------
424  * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
425  * and enable Time Counter
426  */
427 #define CONFIG_SYS_TMCNTSC      (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
428
429 /*-----------------------------------------------------------------------
430  * PISCR - Periodic Interrupt Status and Control                 4-42
431  *-----------------------------------------------------------------------
432  * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
433  * Periodic timer
434  */
435 #define CONFIG_SYS_PISCR        (PISCR_PS|PISCR_PTF|PISCR_PTE)
436
437 /*-----------------------------------------------------------------------
438  * SCCR - System Clock Control                                   9-8
439  *-----------------------------------------------------------------------
440  * Ensure DFBRG is Divide by 16
441  */
442 #define CONFIG_SYS_SCCR SCCR_DFBRG01
443
444 /*-----------------------------------------------------------------------
445  * RCCR - RISC Controller Configuration                         13-7
446  *-----------------------------------------------------------------------
447  */
448 #define CONFIG_SYS_RCCR 0
449
450 #define CONFIG_SYS_MIN_AM_MASK 0xC0000000
451
452 /*
453  * we use the same values for 32 MB, 128 MB and 256 MB SDRAM
454  * refresh rate = 7.68 uS (100 MHz Bus Clock)
455  */
456
457 /*-----------------------------------------------------------------------
458  * MPTPR - Memory Refresh Timer Prescaler Register              10-18
459  *-----------------------------------------------------------------------
460  */
461 #define CONFIG_SYS_MPTPR        0x2000
462
463 /*-----------------------------------------------------------------------
464  * PSRT - Refresh Timer Register                                10-16
465  *-----------------------------------------------------------------------
466  */
467 #define CONFIG_SYS_PSRT 0x16
468
469 /*-----------------------------------------------------------------------
470  * PSRT - SDRAM Mode Register                                   10-10
471  *-----------------------------------------------------------------------
472  */
473
474         /* SDRAM initialization values for 8-column chips
475          */
476 #define CONFIG_SYS_OR2_8COL     (CONFIG_SYS_MIN_AM_MASK         |\
477                          ORxS_BPD_4                     |\
478                          ORxS_ROWST_PBI0_A9             |\
479                          ORxS_NUMR_12)
480
481 #define CONFIG_SYS_PSDMR_8COL   (PSDMR_SDAM_A13_IS_A5           |\
482                          PSDMR_BSMA_A14_A16             |\
483                          PSDMR_SDA10_PBI0_A10           |\
484                          PSDMR_RFRC_7_CLK               |\
485                          PSDMR_PRETOACT_2W              |\
486                          PSDMR_ACTTORW_2W               |\
487                          PSDMR_LDOTOPRE_1C              |\
488                          PSDMR_WRC_1C                   |\
489                          PSDMR_CL_2)
490
491         /* SDRAM initialization values for 9-column chips
492          */
493 #define CONFIG_SYS_OR2_9COL     (CONFIG_SYS_MIN_AM_MASK         |\
494                          ORxS_BPD_4                     |\
495                          ORxS_ROWST_PBI0_A7             |\
496                          ORxS_NUMR_13)
497
498 #define CONFIG_SYS_PSDMR_9COL   (PSDMR_SDAM_A14_IS_A5           |\
499                          PSDMR_BSMA_A13_A15             |\
500                          PSDMR_SDA10_PBI0_A9            |\
501                          PSDMR_RFRC_7_CLK               |\
502                          PSDMR_PRETOACT_2W              |\
503                          PSDMR_ACTTORW_2W               |\
504                          PSDMR_LDOTOPRE_1C              |\
505                          PSDMR_WRC_1C                   |\
506                          PSDMR_CL_2)
507
508         /* SDRAM initialization values for 10-column chips
509          */
510 #define CONFIG_SYS_OR2_10COL    (CONFIG_SYS_MIN_AM_MASK         |\
511                          ORxS_BPD_4                     |\
512                          ORxS_ROWST_PBI1_A4             |\
513                          ORxS_NUMR_13)
514
515 #define CONFIG_SYS_PSDMR_10COL  (PSDMR_PBI                      |\
516                          PSDMR_SDAM_A17_IS_A5           |\
517                          PSDMR_BSMA_A13_A15             |\
518                          PSDMR_SDA10_PBI1_A6            |\
519                          PSDMR_RFRC_7_CLK               |\
520                          PSDMR_PRETOACT_2W              |\
521                          PSDMR_ACTTORW_2W               |\
522                          PSDMR_LDOTOPRE_1C              |\
523                          PSDMR_WRC_1C                   |\
524                          PSDMR_CL_2)
525
526 /*
527  * Init Memory Controller:
528  *
529  * Bank Bus     Machine PortSz  Device
530  * ---- ---     ------- ------  ------
531  *  0   60x     GPCM    8  bit  Boot ROM
532  *  1   60x     GPCM    64 bit  FLASH
533  *  2   60x     SDRAM   64 bit  SDRAM
534  *
535  */
536
537 #define CONFIG_SYS_MRS_OFFS     0x00000000
538
539 #ifdef CONFIG_BOOT_ROM
540 /* Bank 0 - Boot ROM
541  */
542 #define CONFIG_SYS_BR0_PRELIM   ((CONFIG_SYS_BOOTROM_BASE & BRx_BA_MSK)|\
543                          BRx_PS_8                       |\
544                          BRx_MS_GPCM_P                  |\
545                          BRx_V)
546
547 #define CONFIG_SYS_OR0_PRELIM   (P2SZ_TO_AM(CONFIG_SYS_BOOTROM_SIZE)    |\
548                          ORxG_CSNT                      |\
549                          ORxG_ACS_DIV1                  |\
550                          ORxG_SCY_5_CLK                 |\
551                          ORxU_EHTR_8IDLE)
552
553 /* Bank 1 - FLASH
554  */
555 #define CONFIG_SYS_BR1_PRELIM   ((CONFIG_SYS_FLASH_BASE & BRx_BA_MSK)   |\
556                          BRx_PS_64                      |\
557                          BRx_MS_GPCM_P                  |\
558                          BRx_V)
559
560 #define CONFIG_SYS_OR1_PRELIM   (P2SZ_TO_AM(CONFIG_SYS_FLASH_SIZE)      |\
561                          ORxG_CSNT                      |\
562                          ORxG_ACS_DIV1                  |\
563                          ORxG_SCY_5_CLK                 |\
564                          ORxU_EHTR_8IDLE)
565
566 #else /* CONFIG_BOOT_ROM */
567 /* Bank 0 - FLASH
568  */
569 #define CONFIG_SYS_BR0_PRELIM   ((CONFIG_SYS_FLASH_BASE & BRx_BA_MSK)   |\
570                          BRx_PS_64                      |\
571                          BRx_MS_GPCM_P                  |\
572                          BRx_V)
573
574 #define CONFIG_SYS_OR0_PRELIM   (P2SZ_TO_AM(CONFIG_SYS_FLASH_SIZE)      |\
575                          ORxG_CSNT                      |\
576                          ORxG_ACS_DIV1                  |\
577                          ORxG_SCY_5_CLK                 |\
578                          ORxU_EHTR_8IDLE)
579
580 /* Bank 1 - Boot ROM
581  */
582 #define CONFIG_SYS_BR1_PRELIM   ((CONFIG_SYS_BOOTROM_BASE & BRx_BA_MSK)|\
583                          BRx_PS_8                       |\
584                          BRx_MS_GPCM_P                  |\
585                          BRx_V)
586
587 #define CONFIG_SYS_OR1_PRELIM   (P2SZ_TO_AM(CONFIG_SYS_BOOTROM_SIZE)    |\
588                          ORxG_CSNT                      |\
589                          ORxG_ACS_DIV1                  |\
590                          ORxG_SCY_5_CLK                 |\
591                          ORxU_EHTR_8IDLE)
592
593 #endif /* CONFIG_BOOT_ROM */
594
595
596 /* Bank 2 - 60x bus SDRAM
597  */
598 #ifndef CONFIG_SYS_RAMBOOT
599 #define CONFIG_SYS_BR2_PRELIM   ((CONFIG_SYS_SDRAM_BASE & BRx_BA_MSK)   |\
600                          BRx_PS_64                      |\
601                          BRx_MS_SDRAM_P                 |\
602                          BRx_V)
603
604 #define CONFIG_SYS_OR2_PRELIM    CONFIG_SYS_OR2_8COL
605
606 #define CONFIG_SYS_PSDMR         CONFIG_SYS_PSDMR_8COL
607 #endif /* CONFIG_SYS_RAMBOOT */
608
609 /* Bank 3 - Dual Ported SRAM
610  */
611 #define CONFIG_SYS_BR3_PRELIM   ((CONFIG_SYS_DPSRAM_BASE & BRx_BA_MSK) |\
612                          BRx_PS_16                      |\
613                          BRx_MS_GPCM_P                  |\
614                          BRx_V)
615
616 #define CONFIG_SYS_OR3_PRELIM   (P2SZ_TO_AM(CONFIG_SYS_DPSRAM_SIZE)     |\
617                          ORxG_CSNT                      |\
618                          ORxG_ACS_DIV1                  |\
619                          ORxG_SCY_7_CLK                 |\
620                          ORxG_SETA)
621
622 /* Bank 4 - DiskOnChip
623  */
624 #define CONFIG_SYS_BR4_PRELIM   ((CONFIG_SYS_DOC_BASE & BRx_BA_MSK)     |\
625                          BRx_PS_8                       |\
626                          BRx_MS_GPCM_P                  |\
627                          BRx_V)
628
629 #define CONFIG_SYS_OR4_PRELIM   (P2SZ_TO_AM(CONFIG_SYS_DOC_SIZE)        |\
630                          ORxG_CSNT                      |\
631                          ORxG_ACS_DIV2                  |\
632                          ORxG_SCY_9_CLK                 |\
633                          ORxU_EHTR_8IDLE)
634
635 /* Bank 5 - FDC37C78 controller
636  */
637 #define CONFIG_SYS_BR5_PRELIM   ((CONFIG_SYS_FDC37C78_BASE & BRx_BA_MSK) |\
638                          BRx_PS_8                         |\
639                          BRx_MS_GPCM_P                    |\
640                          BRx_V)
641
642 #define CONFIG_SYS_OR5_PRELIM   (P2SZ_TO_AM(CONFIG_SYS_FDC37C78_SIZE)     |\
643                          ORxG_ACS_DIV2                    |\
644                          ORxG_SCY_10_CLK                  |\
645                          ORxU_EHTR_8IDLE)
646
647 /* Bank 6 - Board control registers
648  */
649 #define CONFIG_SYS_BR6_PRELIM   ((CONFIG_SYS_BCRS_BASE & BRx_BA_MSK)    |\
650                          BRx_PS_8                       |\
651                          BRx_MS_GPCM_P                  |\
652                          BRx_V)
653
654 #define CONFIG_SYS_OR6_PRELIM   (P2SZ_TO_AM(CONFIG_SYS_BCRS_SIZE)       |\
655                          ORxG_CSNT                      |\
656                          ORxG_SCY_7_CLK)
657
658 /* Bank 7 - VME Extended Access Range
659  */
660 #define CONFIG_SYS_BR7_PRELIM   ((CONFIG_SYS_VMEEAR_BASE & BRx_BA_MSK) |\
661                          BRx_PS_32                      |\
662                          BRx_MS_GPCM_P                  |\
663                          BRx_V)
664
665 #define CONFIG_SYS_OR7_PRELIM   (P2SZ_TO_AM(CONFIG_SYS_VMEEAR_SIZE)     |\
666                          ORxG_CSNT                      |\
667                          ORxG_ACS_DIV1                  |\
668                          ORxG_SCY_7_CLK                 |\
669                          ORxG_SETA)
670
671 /* Bank 8 - VME Standard Access Range
672  */
673 #define CONFIG_SYS_BR8_PRELIM   ((CONFIG_SYS_VMESAR_BASE & BRx_BA_MSK) |\
674                          BRx_PS_16                      |\
675                          BRx_MS_GPCM_P                  |\
676                          BRx_V)
677
678 #define CONFIG_SYS_OR8_PRELIM   (P2SZ_TO_AM(CONFIG_SYS_VMESAR_SIZE)     |\
679                          ORxG_CSNT                      |\
680                          ORxG_ACS_DIV1                  |\
681                          ORxG_SCY_7_CLK                 |\
682                          ORxG_SETA)
683
684 /* Bank 9 - VME Short I/O Access Range
685  */
686 #define CONFIG_SYS_BR9_PRELIM   ((CONFIG_SYS_VMESIOAR_BASE & BRx_BA_MSK) |\
687                          BRx_PS_16                        |\
688                          BRx_MS_GPCM_P                    |\
689                          BRx_V)
690
691 #define CONFIG_SYS_OR9_PRELIM   (P2SZ_TO_AM(CONFIG_SYS_VMESIOAR_SIZE)     |\
692                          ORxG_CSNT                        |\
693                          ORxG_ACS_DIV1                    |\
694                          ORxG_SCY_7_CLK                   |\
695                          ORxG_SETA)
696
697 #endif  /* __CONFIG_H */