2 * (C) Copyright 2001-2005
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * SPDX-License-Identifier: GPL-2.0+
9 * board/config.h - configuration options, board specific
16 * High Level Configuration Options
20 #define CONFIG_MPC8260 1 /* This is an MPC8260 CPU */
21 #define CONFIG_CPU87 1 /* ...on a CPU87 board */
23 #define CONFIG_CPM2 1 /* Has a CPM2 */
25 #ifdef CONFIG_BOOT_ROM
26 #define CONFIG_SYS_TEXT_BASE 0xFF800000
28 #define CONFIG_SYS_TEXT_BASE 0xFF000000
32 * select serial console configuration
34 * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
35 * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
38 * if CONFIG_CONS_NONE is defined, then the serial console routines must
39 * defined elsewhere (for example, on the cogent platform, there are serial
40 * ports on the motherboard which are used for the serial console - see
41 * cogent/cma101/serial.[ch]).
43 #undef CONFIG_CONS_ON_SMC /* define if console on SMC */
44 #define CONFIG_CONS_ON_SCC /* define if console on SCC */
45 #undef CONFIG_CONS_NONE /* define if console on something else*/
46 #define CONFIG_CONS_INDEX 1 /* which serial channel for console */
48 #if defined(CONFIG_CONS_NONE) || defined(CONFIG_CONS_USE_EXTC)
49 #define CONFIG_BAUDRATE 230400
51 #define CONFIG_BAUDRATE 9600
55 * select ethernet configuration
57 * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
58 * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
61 * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
62 * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset.
64 #undef CONFIG_ETHER_ON_SCC /* define if ether on SCC */
65 #define CONFIG_ETHER_ON_FCC /* define if ether on FCC */
66 #undef CONFIG_ETHER_NONE /* define if ether on something else */
67 #define CONFIG_ETHER_INDEX 1 /* which SCC/FCC channel for ethernet */
69 #define CONFIG_HAS_ETH1 1
70 #define CONFIG_HAS_ETH2 1
72 #if defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 1)
77 * - RAM for BD/Buffers is on the 60x Bus (see 28-13)
78 * - Enable Full Duplex in FSMR
80 # define CONFIG_SYS_CMXFCR_MASK1 (CMXFCR_FC1|CMXFCR_RF1CS_MSK|CMXFCR_TF1CS_MSK)
81 # define CONFIG_SYS_CMXFCR_VALUE1 (CMXFCR_RF1CS_CLK11|CMXFCR_TF1CS_CLK12)
82 # define CONFIG_SYS_CPMFCR_RAMTYPE 0
83 # define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB)
85 #elif defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 2)
90 * - RAM for BD/Buffers is on the 60x Bus (see 28-13)
91 * - Enable Full Duplex in FSMR
93 # define CONFIG_SYS_CMXFCR_MASK2 (CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK)
94 # define CONFIG_SYS_CMXFCR_VALUE2 (CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14)
95 # define CONFIG_SYS_CPMFCR_RAMTYPE 0
96 # define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB)
98 #endif /* CONFIG_ETHER_ON_FCC, CONFIG_ETHER_INDEX */
100 /* system clock rate (CLKIN) - equal to the 60x and local bus speed */
101 #define CONFIG_8260_CLKIN 100000000 /* in Hz */
103 #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
105 #define CONFIG_PREBOOT \
107 "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS; " \
110 #undef CONFIG_BOOTARGS
111 #define CONFIG_BOOTCOMMAND \
113 "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
114 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \
117 /*-----------------------------------------------------------------------
118 * I2C/EEPROM/RTC configuration
120 #define CONFIG_SYS_I2C
121 #define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */
122 #define CONFIG_SYS_I2C_SOFT_SPEED 50000
123 #define CONFIG_SYS_I2C_SOFT_SLAVE 0xFE
126 * Software (bit-bang) I2C driver configuration
128 #define I2C_PORT 3 /* Port A=0, B=1, C=2, D=3 */
129 #define I2C_ACTIVE (iop->pdir |= 0x00010000)
130 #define I2C_TRISTATE (iop->pdir &= ~0x00010000)
131 #define I2C_READ ((iop->pdat & 0x00010000) != 0)
132 #define I2C_SDA(bit) if(bit) iop->pdat |= 0x00010000; \
133 else iop->pdat &= ~0x00010000
134 #define I2C_SCL(bit) if(bit) iop->pdat |= 0x00020000; \
135 else iop->pdat &= ~0x00020000
136 #define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
138 #define CONFIG_RTC_PCF8563
139 #define CONFIG_SYS_I2C_RTC_ADDR 0x51
141 #undef CONFIG_WATCHDOG /* watchdog disabled */
143 /*-----------------------------------------------------------------------
144 * Disk-On-Chip configuration
147 #define CONFIG_SYS_MAX_DOC_DEVICE 1 /* Max number of DOC devices */
149 #define CONFIG_SYS_DOC_SUPPORT_2000
150 #define CONFIG_SYS_DOC_SUPPORT_MILLENNIUM
152 /*-----------------------------------------------------------------------
153 * Miscellaneous configuration options
156 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
157 #undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */
162 #define CONFIG_BOOTP_SUBNETMASK
163 #define CONFIG_BOOTP_GATEWAY
164 #define CONFIG_BOOTP_HOSTNAME
165 #define CONFIG_BOOTP_BOOTPATH
166 #define CONFIG_BOOTP_BOOTFILESIZE
170 * Command line configuration.
172 #include <config_cmd_default.h>
174 #define CONFIG_CMD_BEDBUG
175 #define CONFIG_CMD_DATE
176 #define CONFIG_CMD_EEPROM
177 #define CONFIG_CMD_I2C
180 #define CONFIG_PCI_INDIRECT_BRIDGE
181 #define CONFIG_CMD_PCI
185 * Miscellaneous configurable options
187 #define CONFIG_SYS_LONGHELP /* undef to save memory */
188 #if defined(CONFIG_CMD_KGDB)
189 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
191 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
193 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
194 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
195 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
197 #define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
198 #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
200 #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
202 #define CONFIG_SYS_RESET_ADDRESS 0xFFF00100 /* "bad" address */
207 * For booting Linux, the board info and command line data
208 * have to be in the first 8 MB of memory, since this is
209 * the maximum mapped by the Linux kernel during initialization.
211 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
213 /*-----------------------------------------------------------------------
214 * Flash configuration
217 #define CONFIG_SYS_BOOTROM_BASE 0xFF800000
218 #define CONFIG_SYS_BOOTROM_SIZE 0x00080000
219 #define CONFIG_SYS_FLASH_BASE 0xFF000000
220 #define CONFIG_SYS_FLASH_SIZE 0x00800000
222 /*-----------------------------------------------------------------------
225 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max num of memory banks */
226 #define CONFIG_SYS_MAX_FLASH_SECT 135 /* max num of sects on one chip */
228 #define CONFIG_SYS_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */
229 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
231 /*-----------------------------------------------------------------------
232 * Other areas to be mapped
235 /* CS3: Dual ported SRAM */
236 #define CONFIG_SYS_DPSRAM_BASE 0x40000000
237 #define CONFIG_SYS_DPSRAM_SIZE 0x00100000
239 /* CS4: DiskOnChip */
240 #define CONFIG_SYS_DOC_BASE 0xF4000000
241 #define CONFIG_SYS_DOC_SIZE 0x00100000
243 /* CS5: FDC37C78 controller */
244 #define CONFIG_SYS_FDC37C78_BASE 0xF1000000
245 #define CONFIG_SYS_FDC37C78_SIZE 0x00100000
247 /* CS6: Board configuration registers */
248 #define CONFIG_SYS_BCRS_BASE 0xF2000000
249 #define CONFIG_SYS_BCRS_SIZE 0x00010000
251 /* CS7: VME Extended Access Range */
252 #define CONFIG_SYS_VMEEAR_BASE 0x60000000
253 #define CONFIG_SYS_VMEEAR_SIZE 0x01000000
255 /* CS8: VME Standard Access Range */
256 #define CONFIG_SYS_VMESAR_BASE 0xFE000000
257 #define CONFIG_SYS_VMESAR_SIZE 0x01000000
259 /* CS9: VME Short I/O Access Range */
260 #define CONFIG_SYS_VMESIOAR_BASE 0xFD000000
261 #define CONFIG_SYS_VMESIOAR_SIZE 0x01000000
263 /*-----------------------------------------------------------------------
264 * Hard Reset Configuration Words
266 * if you change bits in the HRCW, you must also change the CONFIG_SYS_*
267 * defines for the various registers affected by the HRCW e.g. changing
268 * HRCW_DPPCxx requires you to also change CONFIG_SYS_SIUMCR.
270 #if defined(CONFIG_BOOT_ROM)
271 #define CONFIG_SYS_HRCW_MASTER (HRCW_CIP | HRCW_ISB100 | HRCW_BMS | \
272 HRCW_BPS01 | HRCW_CS10PC01)
274 #define CONFIG_SYS_HRCW_MASTER (HRCW_CIP | HRCW_ISB100 | HRCW_BMS | HRCW_CS10PC01)
277 /* no slaves so just fill with zeros */
278 #define CONFIG_SYS_HRCW_SLAVE1 0
279 #define CONFIG_SYS_HRCW_SLAVE2 0
280 #define CONFIG_SYS_HRCW_SLAVE3 0
281 #define CONFIG_SYS_HRCW_SLAVE4 0
282 #define CONFIG_SYS_HRCW_SLAVE5 0
283 #define CONFIG_SYS_HRCW_SLAVE6 0
284 #define CONFIG_SYS_HRCW_SLAVE7 0
286 /*-----------------------------------------------------------------------
287 * Internal Memory Mapped Register
289 #define CONFIG_SYS_IMMR 0xF0000000
291 /*-----------------------------------------------------------------------
292 * Definitions for initial stack pointer and data area (in DPRAM)
294 #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
295 #define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in DPRAM */
296 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
297 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
299 /*-----------------------------------------------------------------------
300 * Start addresses for the final memory configuration
301 * (Set up by the startup code)
302 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
304 * 60x SDRAM is mapped at CONFIG_SYS_SDRAM_BASE.
306 #define CONFIG_SYS_SDRAM_BASE 0x00000000
307 #define CONFIG_SYS_SDRAM_MAX_SIZE 0x08000000 /* max. 128 MB */
308 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
309 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
310 #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc()*/
312 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
313 # define CONFIG_SYS_RAMBOOT
317 #define CONFIG_PCI_PNP
318 #define CONFIG_EEPRO100
319 #define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
323 /* environment is in Flash */
324 #define CONFIG_ENV_IS_IN_FLASH 1
325 #ifdef CONFIG_BOOT_ROM
326 # define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE+0x70000)
327 # define CONFIG_ENV_SIZE 0x10000
328 # define CONFIG_ENV_SECT_SIZE 0x10000
331 /* environment is in EEPROM */
332 #define CONFIG_ENV_IS_IN_EEPROM 1
333 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x58 /* EEPROM X24C16 */
334 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
335 /* mask of address bits that overflow into the "EEPROM chip address" */
336 #define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07
337 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4
338 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
339 #define CONFIG_ENV_OFFSET 512
340 #define CONFIG_ENV_SIZE (2048 - 512)
343 /*-----------------------------------------------------------------------
344 * Cache Configuration
346 #define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8260 CPU */
347 #if defined(CONFIG_CMD_KGDB)
348 # define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
351 /*-----------------------------------------------------------------------
352 * HIDx - Hardware Implementation-dependent Registers 2-11
353 *-----------------------------------------------------------------------
354 * HID0 also contains cache control - initially enable both caches and
355 * invalidate contents, then the final state leaves only the instruction
356 * cache enabled. Note that Power-On and Hard reset invalidate the caches,
357 * but Soft reset does not.
359 * HID1 has only read-only information - nothing to set.
361 #define CONFIG_SYS_HID0_INIT (HID0_ICE|HID0_DCE|HID0_ICFI|\
362 HID0_DCI|HID0_IFEM|HID0_ABE)
363 #define CONFIG_SYS_HID0_FINAL (HID0_IFEM|HID0_ABE)
364 #define CONFIG_SYS_HID2 0
366 /*-----------------------------------------------------------------------
367 * RMR - Reset Mode Register 5-5
368 *-----------------------------------------------------------------------
369 * turn on Checkstop Reset Enable
371 #define CONFIG_SYS_RMR RMR_CSRE
373 /*-----------------------------------------------------------------------
374 * BCR - Bus Configuration 4-25
375 *-----------------------------------------------------------------------
377 #define BCR_APD01 0x10000000
378 #define CONFIG_SYS_BCR (BCR_APD01|BCR_ETM|BCR_LETM) /* 8260 mode */
380 /*-----------------------------------------------------------------------
381 * SIUMCR - SIU Module Configuration 4-31
382 *-----------------------------------------------------------------------
384 #define CONFIG_SYS_SIUMCR (SIUMCR_BBD|SIUMCR_DPPC00|SIUMCR_APPC10|\
385 SIUMCR_CS10PC01|SIUMCR_BCTLC10)
387 /*-----------------------------------------------------------------------
388 * SYPCR - System Protection Control 4-35
389 * SYPCR can only be written once after reset!
390 *-----------------------------------------------------------------------
391 * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
393 #if defined(CONFIG_WATCHDOG)
394 #define CONFIG_SYS_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
395 SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE)
397 #define CONFIG_SYS_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
398 SYPCR_SWRI|SYPCR_SWP)
399 #endif /* CONFIG_WATCHDOG */
401 /*-----------------------------------------------------------------------
402 * TMCNTSC - Time Counter Status and Control 4-40
403 *-----------------------------------------------------------------------
404 * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
405 * and enable Time Counter
407 #define CONFIG_SYS_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
409 /*-----------------------------------------------------------------------
410 * PISCR - Periodic Interrupt Status and Control 4-42
411 *-----------------------------------------------------------------------
412 * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
415 #define CONFIG_SYS_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE)
417 /*-----------------------------------------------------------------------
418 * SCCR - System Clock Control 9-8
419 *-----------------------------------------------------------------------
420 * Ensure DFBRG is Divide by 16
422 #define CONFIG_SYS_SCCR SCCR_DFBRG01
424 /*-----------------------------------------------------------------------
425 * RCCR - RISC Controller Configuration 13-7
426 *-----------------------------------------------------------------------
428 #define CONFIG_SYS_RCCR 0
430 #define CONFIG_SYS_MIN_AM_MASK 0xC0000000
433 * we use the same values for 32 MB, 128 MB and 256 MB SDRAM
434 * refresh rate = 7.68 uS (100 MHz Bus Clock)
437 /*-----------------------------------------------------------------------
438 * MPTPR - Memory Refresh Timer Prescaler Register 10-18
439 *-----------------------------------------------------------------------
441 #define CONFIG_SYS_MPTPR 0x2000
443 /*-----------------------------------------------------------------------
444 * PSRT - Refresh Timer Register 10-16
445 *-----------------------------------------------------------------------
447 #define CONFIG_SYS_PSRT 0x16
449 /*-----------------------------------------------------------------------
450 * PSRT - SDRAM Mode Register 10-10
451 *-----------------------------------------------------------------------
454 /* SDRAM initialization values for 8-column chips
456 #define CONFIG_SYS_OR2_8COL (CONFIG_SYS_MIN_AM_MASK |\
458 ORxS_ROWST_PBI0_A9 |\
461 #define CONFIG_SYS_PSDMR_8COL (PSDMR_SDAM_A13_IS_A5 |\
462 PSDMR_BSMA_A14_A16 |\
463 PSDMR_SDA10_PBI0_A10 |\
471 /* SDRAM initialization values for 9-column chips
473 #define CONFIG_SYS_OR2_9COL (CONFIG_SYS_MIN_AM_MASK |\
475 ORxS_ROWST_PBI0_A7 |\
478 #define CONFIG_SYS_PSDMR_9COL (PSDMR_SDAM_A14_IS_A5 |\
479 PSDMR_BSMA_A13_A15 |\
480 PSDMR_SDA10_PBI0_A9 |\
488 /* SDRAM initialization values for 10-column chips
490 #define CONFIG_SYS_OR2_10COL (CONFIG_SYS_MIN_AM_MASK |\
492 ORxS_ROWST_PBI1_A4 |\
495 #define CONFIG_SYS_PSDMR_10COL (PSDMR_PBI |\
496 PSDMR_SDAM_A17_IS_A5 |\
497 PSDMR_BSMA_A13_A15 |\
498 PSDMR_SDA10_PBI1_A6 |\
507 * Init Memory Controller:
509 * Bank Bus Machine PortSz Device
510 * ---- --- ------- ------ ------
511 * 0 60x GPCM 8 bit Boot ROM
512 * 1 60x GPCM 64 bit FLASH
513 * 2 60x SDRAM 64 bit SDRAM
517 #define CONFIG_SYS_MRS_OFFS 0x00000000
519 #ifdef CONFIG_BOOT_ROM
522 #define CONFIG_SYS_BR0_PRELIM ((CONFIG_SYS_BOOTROM_BASE & BRx_BA_MSK)|\
527 #define CONFIG_SYS_OR0_PRELIM (P2SZ_TO_AM(CONFIG_SYS_BOOTROM_SIZE) |\
535 #define CONFIG_SYS_BR1_PRELIM ((CONFIG_SYS_FLASH_BASE & BRx_BA_MSK) |\
540 #define CONFIG_SYS_OR1_PRELIM (P2SZ_TO_AM(CONFIG_SYS_FLASH_SIZE) |\
546 #else /* CONFIG_BOOT_ROM */
549 #define CONFIG_SYS_BR0_PRELIM ((CONFIG_SYS_FLASH_BASE & BRx_BA_MSK) |\
554 #define CONFIG_SYS_OR0_PRELIM (P2SZ_TO_AM(CONFIG_SYS_FLASH_SIZE) |\
562 #define CONFIG_SYS_BR1_PRELIM ((CONFIG_SYS_BOOTROM_BASE & BRx_BA_MSK)|\
567 #define CONFIG_SYS_OR1_PRELIM (P2SZ_TO_AM(CONFIG_SYS_BOOTROM_SIZE) |\
573 #endif /* CONFIG_BOOT_ROM */
576 /* Bank 2 - 60x bus SDRAM
578 #ifndef CONFIG_SYS_RAMBOOT
579 #define CONFIG_SYS_BR2_PRELIM ((CONFIG_SYS_SDRAM_BASE & BRx_BA_MSK) |\
584 #define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_OR2_8COL
586 #define CONFIG_SYS_PSDMR CONFIG_SYS_PSDMR_8COL
587 #endif /* CONFIG_SYS_RAMBOOT */
589 /* Bank 3 - Dual Ported SRAM
591 #define CONFIG_SYS_BR3_PRELIM ((CONFIG_SYS_DPSRAM_BASE & BRx_BA_MSK) |\
596 #define CONFIG_SYS_OR3_PRELIM (P2SZ_TO_AM(CONFIG_SYS_DPSRAM_SIZE) |\
602 /* Bank 4 - DiskOnChip
604 #define CONFIG_SYS_BR4_PRELIM ((CONFIG_SYS_DOC_BASE & BRx_BA_MSK) |\
609 #define CONFIG_SYS_OR4_PRELIM (P2SZ_TO_AM(CONFIG_SYS_DOC_SIZE) |\
615 /* Bank 5 - FDC37C78 controller
617 #define CONFIG_SYS_BR5_PRELIM ((CONFIG_SYS_FDC37C78_BASE & BRx_BA_MSK) |\
622 #define CONFIG_SYS_OR5_PRELIM (P2SZ_TO_AM(CONFIG_SYS_FDC37C78_SIZE) |\
627 /* Bank 6 - Board control registers
629 #define CONFIG_SYS_BR6_PRELIM ((CONFIG_SYS_BCRS_BASE & BRx_BA_MSK) |\
634 #define CONFIG_SYS_OR6_PRELIM (P2SZ_TO_AM(CONFIG_SYS_BCRS_SIZE) |\
638 /* Bank 7 - VME Extended Access Range
640 #define CONFIG_SYS_BR7_PRELIM ((CONFIG_SYS_VMEEAR_BASE & BRx_BA_MSK) |\
645 #define CONFIG_SYS_OR7_PRELIM (P2SZ_TO_AM(CONFIG_SYS_VMEEAR_SIZE) |\
651 /* Bank 8 - VME Standard Access Range
653 #define CONFIG_SYS_BR8_PRELIM ((CONFIG_SYS_VMESAR_BASE & BRx_BA_MSK) |\
658 #define CONFIG_SYS_OR8_PRELIM (P2SZ_TO_AM(CONFIG_SYS_VMESAR_SIZE) |\
664 /* Bank 9 - VME Short I/O Access Range
666 #define CONFIG_SYS_BR9_PRELIM ((CONFIG_SYS_VMESIOAR_BASE & BRx_BA_MSK) |\
671 #define CONFIG_SYS_OR9_PRELIM (P2SZ_TO_AM(CONFIG_SYS_VMESIOAR_SIZE) |\
677 #endif /* __CONFIG_H */