include/configs/CPU86.h

   1 /*
   2  * (C) Copyright 2001-2005
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 /*
   9  * board/config.h - configuration options, board specific
  10  */
  11
  12 #ifndef __CONFIG_H
  13 #define __CONFIG_H
  14
  15 /*
  16  * High Level Configuration Options
  17  * (easy to change)
  18  */
  19
  20 #define CONFIG_MPC8260          1       /* This is an MPC8260 CPU               */
  21 #define CONFIG_CPU86            1       /* ...on a CPU86 board  */
  22 #define CONFIG_CPM2             1       /* Has a CPM2 */
  23
  24 #ifdef CONFIG_BOOT_ROM
  25 #define CONFIG_SYS_TEXT_BASE    0xFF800000
  26 #else
  27 #define CONFIG_SYS_TEXT_BASE    0xFF000000
  28 #endif
  29
  30 /*
  31  * select serial console configuration
  32  *
  33  * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
  34  * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
  35  * for SCC).
  36  *
  37  * if CONFIG_CONS_NONE is defined, then the serial console routines must
  38  * defined elsewhere (for example, on the cogent platform, there are serial
  39  * ports on the motherboard which are used for the serial console - see
  40  * cogent/cma101/serial.[ch]).
  41  */
  42 #undef  CONFIG_CONS_ON_SMC              /* define if console on SMC */
  43 #define CONFIG_CONS_ON_SCC              /* define if console on SCC */
  44 #undef  CONFIG_CONS_NONE                /* define if console on something else*/
  45 #define CONFIG_CONS_INDEX       1       /* which serial channel for console */
  46
  47 #if defined(CONFIG_CONS_NONE) || defined(CONFIG_CONS_USE_EXTC)
  48 #define CONFIG_BAUDRATE         230400
  49 #else
  50 #define CONFIG_BAUDRATE         9600
  51 #endif
  52
  53 /*
  54  * select ethernet configuration
  55  *
  56  * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
  57  * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
  58  * for FCC)
  59  *
  60  * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
  61  * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset.
  62  */
  63 #undef  CONFIG_ETHER_ON_SCC             /* define if ether on SCC       */
  64 #define CONFIG_ETHER_ON_FCC             /* define if ether on FCC       */
  65 #undef  CONFIG_ETHER_NONE               /* define if ether on something else */
  66 #define CONFIG_ETHER_INDEX      1       /* which SCC/FCC channel for ethernet */
  67
  68 #if defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 1)
  69
  70 /*
  71  * - Rx-CLK is CLK11
  72  * - Tx-CLK is CLK12
  73  * - RAM for BD/Buffers is on the 60x Bus (see 28-13)
  74  * - Enable Full Duplex in FSMR
  75  */
  76 # define CONFIG_SYS_CMXFCR_MASK1        (CMXFCR_FC1|CMXFCR_RF1CS_MSK|CMXFCR_TF1CS_MSK)
  77 # define CONFIG_SYS_CMXFCR_VALUE1       (CMXFCR_RF1CS_CLK11|CMXFCR_TF1CS_CLK12)
  78 # define CONFIG_SYS_CPMFCR_RAMTYPE      0
  79 # define CONFIG_SYS_FCC_PSMR            (FCC_PSMR_FDE|FCC_PSMR_LPB)
  80
  81 #elif defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 2)
  82
  83 /*
  84  * - Rx-CLK is CLK13
  85  * - Tx-CLK is CLK14
  86  * - RAM for BD/Buffers is on the 60x Bus (see 28-13)
  87  * - Enable Full Duplex in FSMR
  88  */
  89 # define CONFIG_SYS_CMXFCR_MASK2        (CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK)
  90 # define CONFIG_SYS_CMXFCR_VALUE2       (CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14)
  91 # define CONFIG_SYS_CPMFCR_RAMTYPE      0
  92 # define CONFIG_SYS_FCC_PSMR            (FCC_PSMR_FDE|FCC_PSMR_LPB)
  93
  94 #endif /* CONFIG_ETHER_ON_FCC, CONFIG_ETHER_INDEX */
  95
  96 /* system clock rate (CLKIN) - equal to the 60x and local bus speed */
  97 #define CONFIG_8260_CLKIN       64000000        /* in Hz */
  98
  99 #define CONFIG_BOOTDELAY        5       /* autoboot after 5 seconds     */
 100
 101 #define CONFIG_PREBOOT                                                          \
 102         "echo; "                                                                \
 103         "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS; "   \
 104         "echo"
 105
 106 #undef  CONFIG_BOOTARGS
 107 #define CONFIG_BOOTCOMMAND                                                      \
 108         "bootp; "                                                               \
 109         "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} "     \
 110         "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; "   \
 111         "bootm"
 112
 113 /*-----------------------------------------------------------------------
 114  * I2C/EEPROM/RTC configuration
 115  */
 116 #define CONFIG_SYS_I2C
 117 #define CONFIG_SYS_I2C_SOFT                     /* I2C bit-banged */
 118 #define CONFIG_SYS_I2C_SOFT_SPEED       50000
 119 #define CONFIG_SYS_I2C_SOFT_SLAVE       0xFE
 120
 121 /*
 122  * Software (bit-bang) I2C driver configuration
 123  */
 124 #define I2C_PORT        3               /* Port A=0, B=1, C=2, D=3 */
 125 #define I2C_ACTIVE      (iop->pdir |=  0x00010000)
 126 #define I2C_TRISTATE    (iop->pdir &= ~0x00010000)
 127 #define I2C_READ        ((iop->pdat & 0x00010000) != 0)
 128 #define I2C_SDA(bit)    if(bit) iop->pdat |=  0x00010000; \
 129                         else    iop->pdat &= ~0x00010000
 130 #define I2C_SCL(bit)    if(bit) iop->pdat |=  0x00020000; \
 131                         else    iop->pdat &= ~0x00020000
 132 #define I2C_DELAY       udelay(5)       /* 1/4 I2C clock duration */
 133
 134 #define CONFIG_RTC_PCF8563
 135 #define CONFIG_SYS_I2C_RTC_ADDR 0x51
 136
 137 #undef  CONFIG_WATCHDOG                 /* watchdog disabled            */
 138
 139 /*-----------------------------------------------------------------------
 140  * Miscellaneous configuration options
 141  */
 142
 143 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download  */
 144 #undef  CONFIG_SYS_LOADS_BAUD_CHANGE            /* don't allow baudrate change  */
 145
 146 /*
 147  * BOOTP options
 148  */
 149 #define CONFIG_BOOTP_SUBNETMASK
 150 #define CONFIG_BOOTP_GATEWAY
 151 #define CONFIG_BOOTP_HOSTNAME
 152 #define CONFIG_BOOTP_BOOTPATH
 153 #define CONFIG_BOOTP_BOOTFILESIZE
 154
 155
 156 /*
 157  * Command line configuration.
 158  */
 159 #include <config_cmd_default.h>
 160
 161 #define CONFIG_CMD_BEDBUG
 162 #define CONFIG_CMD_DATE
 163 #define CONFIG_CMD_DHCP
 164 #define CONFIG_CMD_EEPROM
 165 #define CONFIG_CMD_I2C
 166 #define CONFIG_CMD_NFS
 167 #define CONFIG_CMD_SNTP
 168
 169
 170 /*
 171  * Miscellaneous configurable options
 172  */
 173 #define CONFIG_SYS_LONGHELP                     /* undef to save memory         */
 174 #define CONFIG_SYS_PROMPT       "=> "           /* Monitor Command Prompt       */
 175 #if defined(CONFIG_CMD_KGDB)
 176 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size      */
 177 #else
 178 #define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size      */
 179 #endif
 180 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
 181 #define CONFIG_SYS_MAXARGS      16              /* max number of command args   */
 182 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size    */
 183
 184 #define CONFIG_SYS_MEMTEST_START        0x0400000       /* memtest works on     */
 185 #define CONFIG_SYS_MEMTEST_END  0x0C00000       /* 4 ... 12 MB in DRAM  */
 186
 187 #define CONFIG_SYS_LOAD_ADDR    0x100000        /* default load address */
 188
 189 #define CONFIG_SYS_HZ           1000            /* decrementer freq: 1 ms ticks */
 190
 191 #define CONFIG_SYS_RESET_ADDRESS 0xFFF00100     /* "bad" address                */
 192
 193 /*
 194  * For booting Linux, the board info and command line data
 195  * have to be in the first 8 MB of memory, since this is
 196  * the maximum mapped by the Linux kernel during initialization.
 197  */
 198 #define CONFIG_SYS_BOOTMAPSZ            (8 << 20) /* Initial Memory map for Linux */
 199
 200 /*-----------------------------------------------------------------------
 201  * Flash configuration
 202  */
 203
 204 #define CONFIG_SYS_BOOTROM_BASE 0xFF800000
 205 #define CONFIG_SYS_BOOTROM_SIZE 0x00080000
 206 #define CONFIG_SYS_FLASH_BASE           0xFF000000
 207 #define CONFIG_SYS_FLASH_SIZE           0x00800000
 208
 209 /*-----------------------------------------------------------------------
 210  * FLASH organization
 211  */
 212 #define CONFIG_SYS_MAX_FLASH_BANKS      2       /* max num of memory banks      */
 213 #define CONFIG_SYS_MAX_FLASH_SECT       128     /* max num of sects on one chip */
 214
 215 #define CONFIG_SYS_FLASH_ERASE_TOUT     240000  /* Flash Erase Timeout (in ms)  */
 216 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (in ms)  */
 217
 218 /*-----------------------------------------------------------------------
 219  * Other areas to be mapped
 220  */
 221
 222 /* CS3: Dual ported SRAM */
 223 #define CONFIG_SYS_DPSRAM_BASE          0x40000000
 224 #define CONFIG_SYS_DPSRAM_SIZE          0x00020000
 225
 226 /* CS4: DiskOnChip */
 227 #define CONFIG_SYS_DOC_BASE             0xF4000000
 228 #define CONFIG_SYS_DOC_SIZE             0x00100000
 229
 230 /* CS5: FDC37C78 controller */
 231 #define CONFIG_SYS_FDC37C78_BASE        0xF1000000
 232 #define CONFIG_SYS_FDC37C78_SIZE        0x00100000
 233
 234 /* CS6: Board configuration registers */
 235 #define CONFIG_SYS_BCRS_BASE            0xF2000000
 236 #define CONFIG_SYS_BCRS_SIZE            0x00010000
 237
 238 /* CS7: VME Extended Access Range */
 239 #define CONFIG_SYS_VMEEAR_BASE          0x80000000
 240 #define CONFIG_SYS_VMEEAR_SIZE          0x01000000
 241
 242 /* CS8: VME Standard Access Range */
 243 #define CONFIG_SYS_VMESAR_BASE          0xFE000000
 244 #define CONFIG_SYS_VMESAR_SIZE          0x01000000
 245
 246 /* CS9: VME Short I/O Access Range */
 247 #define CONFIG_SYS_VMESIOAR_BASE        0xFD000000
 248 #define CONFIG_SYS_VMESIOAR_SIZE        0x01000000
 249
 250 /*-----------------------------------------------------------------------
 251  * Hard Reset Configuration Words
 252  *
 253  * if you change bits in the HRCW, you must also change the CONFIG_SYS_*
 254  * defines for the various registers affected by the HRCW e.g. changing
 255  * HRCW_DPPCxx requires you to also change CONFIG_SYS_SIUMCR.
 256  */
 257 #if defined(CONFIG_BOOT_ROM)
 258 #define CONFIG_SYS_HRCW_MASTER          (HRCW_CIP | HRCW_ISB100 | HRCW_BMS | \
 259                                  HRCW_BPS01 | HRCW_CS10PC01)
 260 #else
 261 #define CONFIG_SYS_HRCW_MASTER          (HRCW_CIP | HRCW_ISB100 | HRCW_BMS | HRCW_CS10PC01)
 262 #endif
 263
 264 /* no slaves so just fill with zeros */
 265 #define CONFIG_SYS_HRCW_SLAVE1          0
 266 #define CONFIG_SYS_HRCW_SLAVE2          0
 267 #define CONFIG_SYS_HRCW_SLAVE3          0
 268 #define CONFIG_SYS_HRCW_SLAVE4          0
 269 #define CONFIG_SYS_HRCW_SLAVE5          0
 270 #define CONFIG_SYS_HRCW_SLAVE6          0
 271 #define CONFIG_SYS_HRCW_SLAVE7          0
 272
 273 /*-----------------------------------------------------------------------
 274  * Internal Memory Mapped Register
 275  */
 276 #define CONFIG_SYS_IMMR         0xF0000000
 277
 278 /*-----------------------------------------------------------------------
 279  * Definitions for initial stack pointer and data area (in DPRAM)
 280  */
 281 #define CONFIG_SYS_INIT_RAM_ADDR        CONFIG_SYS_IMMR
 282 #define CONFIG_SYS_INIT_RAM_SIZE        0x4000  /* Size of used area in DPRAM    */
 283 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 284 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 285
 286 /*-----------------------------------------------------------------------
 287  * Start addresses for the final memory configuration
 288  * (Set up by the startup code)
 289  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 290  *
 291  * 60x SDRAM is mapped at CONFIG_SYS_SDRAM_BASE.
 292  */
 293 #define CONFIG_SYS_SDRAM_BASE           0x00000000
 294 #define CONFIG_SYS_SDRAM_MAX_SIZE       0x08000000      /* max. 128 MB          */
 295 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
 296 #define CONFIG_SYS_MONITOR_LEN          (256 << 10)     /* Reserve 256 kB for Monitor */
 297 #define CONFIG_SYS_MALLOC_LEN           (128 << 10)     /* Reserve 128 kB for malloc()*/
 298
 299 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
 300 # define CONFIG_SYS_RAMBOOT
 301 #endif
 302
 303 #if 0
 304 /* environment is in Flash */
 305 #define CONFIG_ENV_IS_IN_FLASH  1
 306 #ifdef CONFIG_BOOT_ROM
 307 # define CONFIG_ENV_ADDR                (CONFIG_SYS_FLASH_BASE+0x70000)
 308 # define CONFIG_ENV_SIZE                0x10000
 309 # define CONFIG_ENV_SECT_SIZE   0x10000
 310 #endif
 311 #else
 312 /* environment is in EEPROM */
 313 #define CONFIG_ENV_IS_IN_EEPROM 1
 314 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x58    /* EEPROM X24C16                */
 315 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  1
 316 /* mask of address bits that overflow into the "EEPROM chip address"    */
 317 #define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW     0x07
 318 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS       4
 319 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   10      /* and takes up to 10 msec */
 320 #define CONFIG_ENV_OFFSET               512
 321 #define CONFIG_ENV_SIZE         (2048 - 512)
 322 #endif
 323
 324 /*-----------------------------------------------------------------------
 325  * Cache Configuration
 326  */
 327 #define CONFIG_SYS_CACHELINE_SIZE      32      /* For MPC8260 CPU              */
 328 #if defined(CONFIG_CMD_KGDB)
 329 # define CONFIG_SYS_CACHELINE_SHIFT     5       /* log base 2 of the above value */
 330 #endif
 331
 332 /*-----------------------------------------------------------------------
 333  * HIDx - Hardware Implementation-dependent Registers                    2-11
 334  *-----------------------------------------------------------------------
 335  * HID0 also contains cache control - initially enable both caches and
 336  * invalidate contents, then the final state leaves only the instruction
 337  * cache enabled. Note that Power-On and Hard reset invalidate the caches,
 338  * but Soft reset does not.
 339  *
 340  * HID1 has only read-only information - nothing to set.
 341  */
 342 #define CONFIG_SYS_HID0_INIT   (HID0_ICE|HID0_DCE|HID0_ICFI|\
 343                          HID0_DCI|HID0_IFEM|HID0_ABE)
 344 #define CONFIG_SYS_HID0_FINAL  (HID0_IFEM|HID0_ABE)
 345 #define CONFIG_SYS_HID2        0
 346
 347 /*-----------------------------------------------------------------------
 348  * RMR - Reset Mode Register                                     5-5
 349  *-----------------------------------------------------------------------
 350  * turn on Checkstop Reset Enable
 351  */
 352 #define CONFIG_SYS_RMR         RMR_CSRE
 353
 354 /*-----------------------------------------------------------------------
 355  * BCR - Bus Configuration                                       4-25
 356  *-----------------------------------------------------------------------
 357  */
 358 #define BCR_APD01       0x10000000
 359 #define CONFIG_SYS_BCR          (BCR_APD01|BCR_ETM|BCR_LETM)    /* 8260 mode */
 360
 361 /*-----------------------------------------------------------------------
 362  * SIUMCR - SIU Module Configuration                             4-31
 363  *-----------------------------------------------------------------------
 364  */
 365 #define CONFIG_SYS_SIUMCR      (SIUMCR_BBD|SIUMCR_DPPC00|SIUMCR_APPC10|\
 366                          SIUMCR_CS10PC01|SIUMCR_BCTLC10)
 367
 368 /*-----------------------------------------------------------------------
 369  * SYPCR - System Protection Control                             4-35
 370  * SYPCR can only be written once after reset!
 371  *-----------------------------------------------------------------------
 372  * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
 373  */
 374 #if defined(CONFIG_WATCHDOG)
 375 #define CONFIG_SYS_SYPCR       (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
 376                          SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE)
 377 #else
 378 #define CONFIG_SYS_SYPCR       (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
 379                          SYPCR_SWRI|SYPCR_SWP)
 380 #endif /* CONFIG_WATCHDOG */
 381
 382 /*-----------------------------------------------------------------------
 383  * TMCNTSC - Time Counter Status and Control                     4-40
 384  *-----------------------------------------------------------------------
 385  * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
 386  * and enable Time Counter
 387  */
 388 #define CONFIG_SYS_TMCNTSC     (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
 389
 390 /*-----------------------------------------------------------------------
 391  * PISCR - Periodic Interrupt Status and Control                 4-42
 392  *-----------------------------------------------------------------------
 393  * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
 394  * Periodic timer
 395  */
 396 #define CONFIG_SYS_PISCR       (PISCR_PS|PISCR_PTF|PISCR_PTE)
 397
 398 /*-----------------------------------------------------------------------
 399  * SCCR - System Clock Control                                   9-8
 400  *-----------------------------------------------------------------------
 401  * Ensure DFBRG is Divide by 16
 402  */
 403 #define CONFIG_SYS_SCCR        SCCR_DFBRG01
 404
 405 /*-----------------------------------------------------------------------
 406  * RCCR - RISC Controller Configuration                         13-7
 407  *-----------------------------------------------------------------------
 408  */
 409 #define CONFIG_SYS_RCCR        0
 410
 411 #define CONFIG_SYS_MIN_AM_MASK  0xC0000000
 412 /*-----------------------------------------------------------------------
 413  * MPTPR - Memory Refresh Timer Prescaler Register              10-18
 414  *-----------------------------------------------------------------------
 415  */
 416 #define CONFIG_SYS_MPTPR       0x1F00
 417
 418 /*-----------------------------------------------------------------------
 419  * PSRT - Refresh Timer Register                                10-16
 420  *-----------------------------------------------------------------------
 421  */
 422 #define CONFIG_SYS_PSRT        0x0f
 423
 424 /*-----------------------------------------------------------------------
 425  * PSRT - SDRAM Mode Register                                   10-10
 426  *-----------------------------------------------------------------------
 427  */
 428
 429         /* SDRAM initialization values for 8-column chips
 430          */
 431 #define CONFIG_SYS_OR2_8COL     (CONFIG_SYS_MIN_AM_MASK         |\
 432                          ORxS_BPD_4                     |\
 433                          ORxS_ROWST_PBI0_A9             |\
 434                          ORxS_NUMR_12)
 435
 436 #define CONFIG_SYS_PSDMR_8COL   (PSDMR_SDAM_A13_IS_A5           |\
 437                          PSDMR_BSMA_A14_A16             |\
 438                          PSDMR_SDA10_PBI0_A10           |\
 439                          PSDMR_RFRC_7_CLK               |\
 440                          PSDMR_PRETOACT_2W              |\
 441                          PSDMR_ACTTORW_1W               |\
 442                          PSDMR_LDOTOPRE_1C              |\
 443                          PSDMR_WRC_1C                   |\
 444                          PSDMR_CL_2)
 445
 446         /* SDRAM initialization values for 9-column chips
 447          */
 448 #define CONFIG_SYS_OR2_9COL     (CONFIG_SYS_MIN_AM_MASK         |\
 449                          ORxS_BPD_4                     |\
 450                          ORxS_ROWST_PBI0_A7             |\
 451                          ORxS_NUMR_13)
 452
 453 #define CONFIG_SYS_PSDMR_9COL   (PSDMR_SDAM_A14_IS_A5           |\
 454                          PSDMR_BSMA_A13_A15             |\
 455                          PSDMR_SDA10_PBI0_A9            |\
 456                          PSDMR_RFRC_7_CLK               |\
 457                          PSDMR_PRETOACT_2W              |\
 458                          PSDMR_ACTTORW_1W               |\
 459                          PSDMR_LDOTOPRE_1C              |\
 460                          PSDMR_WRC_1C                   |\
 461                          PSDMR_CL_2)
 462
 463 /*
 464  * Init Memory Controller:
 465  *
 466  * Bank Bus     Machine PortSz  Device
 467  * ---- ---     ------- ------  ------
 468  *  0   60x     GPCM    8  bit  Boot ROM
 469  *  1   60x     GPCM    64 bit  FLASH
 470  *  2   60x     SDRAM   64 bit  SDRAM
 471  *
 472  */
 473
 474 #define CONFIG_SYS_MRS_OFFS     0x00000000
 475
 476 #ifdef CONFIG_BOOT_ROM
 477 /* Bank 0 - Boot ROM
 478  */
 479 #define CONFIG_SYS_BR0_PRELIM  ((CONFIG_SYS_BOOTROM_BASE & BRx_BA_MSK)|\
 480                          BRx_PS_8                       |\
 481                          BRx_MS_GPCM_P                  |\
 482                          BRx_V)
 483
 484 #define CONFIG_SYS_OR0_PRELIM  (P2SZ_TO_AM(CONFIG_SYS_BOOTROM_SIZE)   |\
 485                          ORxG_CSNT                      |\
 486                          ORxG_ACS_DIV1                  |\
 487                          ORxG_SCY_3_CLK                 |\
 488                          ORxU_EHTR_8IDLE)
 489
 490 /* Bank 1 - FLASH
 491  */
 492 #define CONFIG_SYS_BR1_PRELIM  ((CONFIG_SYS_FLASH_BASE & BRx_BA_MSK)  |\
 493                          BRx_PS_64                      |\
 494                          BRx_MS_GPCM_P                  |\
 495                          BRx_V)
 496
 497 #define CONFIG_SYS_OR1_PRELIM  (P2SZ_TO_AM(CONFIG_SYS_FLASH_SIZE)     |\
 498                          ORxG_CSNT                      |\
 499                          ORxG_ACS_DIV1                  |\
 500                          ORxG_SCY_3_CLK                 |\
 501                          ORxU_EHTR_8IDLE)
 502
 503 #else /* CONFIG_BOOT_ROM */
 504 /* Bank 0 - FLASH
 505  */
 506 #define CONFIG_SYS_BR0_PRELIM  ((CONFIG_SYS_FLASH_BASE & BRx_BA_MSK)  |\
 507                          BRx_PS_64                      |\
 508                          BRx_MS_GPCM_P                  |\
 509                          BRx_V)
 510
 511 #define CONFIG_SYS_OR0_PRELIM  (P2SZ_TO_AM(CONFIG_SYS_FLASH_SIZE)     |\
 512                          ORxG_CSNT                      |\
 513                          ORxG_ACS_DIV1                  |\
 514                          ORxG_SCY_3_CLK                 |\
 515                          ORxU_EHTR_8IDLE)
 516
 517 /* Bank 1 - Boot ROM
 518  */
 519 #define CONFIG_SYS_BR1_PRELIM  ((CONFIG_SYS_BOOTROM_BASE & BRx_BA_MSK)|\
 520                          BRx_PS_8                       |\
 521                          BRx_MS_GPCM_P                  |\
 522                          BRx_V)
 523
 524 #define CONFIG_SYS_OR1_PRELIM  (P2SZ_TO_AM(CONFIG_SYS_BOOTROM_SIZE)   |\
 525                          ORxG_CSNT                      |\
 526                          ORxG_ACS_DIV1                  |\
 527                          ORxG_SCY_3_CLK                 |\
 528                          ORxU_EHTR_8IDLE)
 529
 530 #endif /* CONFIG_BOOT_ROM */
 531
 532
 533 /* Bank 2 - 60x bus SDRAM
 534  */
 535 #ifndef CONFIG_SYS_RAMBOOT
 536 #define CONFIG_SYS_BR2_PRELIM  ((CONFIG_SYS_SDRAM_BASE & BRx_BA_MSK)  |\
 537                          BRx_PS_64                      |\
 538                          BRx_MS_SDRAM_P                 |\
 539                          BRx_V)
 540
 541 #define CONFIG_SYS_OR2_PRELIM    CONFIG_SYS_OR2_9COL
 542
 543 #define CONFIG_SYS_PSDMR         CONFIG_SYS_PSDMR_9COL
 544 #endif /* CONFIG_SYS_RAMBOOT */
 545
 546 /* Bank 3 - Dual Ported SRAM
 547  */
 548 #define CONFIG_SYS_BR3_PRELIM  ((CONFIG_SYS_DPSRAM_BASE & BRx_BA_MSK) |\
 549                          BRx_PS_16                      |\
 550                          BRx_MS_GPCM_P                  |\
 551                          BRx_V)
 552
 553 #define CONFIG_SYS_OR3_PRELIM  (P2SZ_TO_AM(CONFIG_SYS_DPSRAM_SIZE)    |\
 554                          ORxG_CSNT                      |\
 555                          ORxG_ACS_DIV1                  |\
 556                          ORxG_SCY_5_CLK                 |\
 557                          ORxG_SETA)
 558
 559 /* Bank 4 - DiskOnChip
 560  */
 561 #define CONFIG_SYS_BR4_PRELIM  ((CONFIG_SYS_DOC_BASE & BRx_BA_MSK)    |\
 562                          BRx_PS_8                       |\
 563                          BRx_MS_GPCM_P                  |\
 564                          BRx_V)
 565
 566 #define CONFIG_SYS_OR4_PRELIM  (P2SZ_TO_AM(CONFIG_SYS_DOC_SIZE)       |\
 567                          ORxG_ACS_DIV2                  |\
 568                          ORxG_SCY_5_CLK                 |\
 569                          ORxU_EHTR_8IDLE)
 570
 571 /* Bank 5 - FDC37C78 controller
 572  */
 573 #define CONFIG_SYS_BR5_PRELIM  ((CONFIG_SYS_FDC37C78_BASE & BRx_BA_MSK) |\
 574                          BRx_PS_8                         |\
 575                          BRx_MS_GPCM_P                    |\
 576                          BRx_V)
 577
 578 #define CONFIG_SYS_OR5_PRELIM  (P2SZ_TO_AM(CONFIG_SYS_FDC37C78_SIZE)    |\
 579                          ORxG_ACS_DIV2                    |\
 580                          ORxG_SCY_8_CLK                   |\
 581                          ORxU_EHTR_8IDLE)
 582
 583 /* Bank 6 - Board control registers
 584  */
 585 #define CONFIG_SYS_BR6_PRELIM  ((CONFIG_SYS_BCRS_BASE & BRx_BA_MSK)   |\
 586                          BRx_PS_8                       |\
 587                          BRx_MS_GPCM_P                  |\
 588                          BRx_V)
 589
 590 #define CONFIG_SYS_OR6_PRELIM  (P2SZ_TO_AM(CONFIG_SYS_BCRS_SIZE)      |\
 591                          ORxG_CSNT                      |\
 592                          ORxG_SCY_5_CLK)
 593
 594 /* Bank 7 - VME Extended Access Range
 595  */
 596 #define CONFIG_SYS_BR7_PRELIM  ((CONFIG_SYS_VMEEAR_BASE & BRx_BA_MSK) |\
 597                          BRx_PS_32                      |\
 598                          BRx_MS_GPCM_P                  |\
 599                          BRx_V)
 600
 601 #define CONFIG_SYS_OR7_PRELIM  (P2SZ_TO_AM(CONFIG_SYS_VMEEAR_SIZE)    |\
 602                          ORxG_CSNT                      |\
 603                          ORxG_ACS_DIV1                  |\
 604                          ORxG_SCY_5_CLK                 |\
 605                          ORxG_SETA)
 606
 607 /* Bank 8 - VME Standard Access Range
 608  */
 609 #define CONFIG_SYS_BR8_PRELIM  ((CONFIG_SYS_VMESAR_BASE & BRx_BA_MSK) |\
 610                          BRx_PS_16                      |\
 611                          BRx_MS_GPCM_P                  |\
 612                          BRx_V)
 613
 614 #define CONFIG_SYS_OR8_PRELIM  (P2SZ_TO_AM(CONFIG_SYS_VMESAR_SIZE)    |\
 615                          ORxG_CSNT                      |\
 616                          ORxG_ACS_DIV1                  |\
 617                          ORxG_SCY_5_CLK                 |\
 618                          ORxG_SETA)
 619
 620 /* Bank 9 - VME Short I/O Access Range
 621  */
 622 #define CONFIG_SYS_BR9_PRELIM  ((CONFIG_SYS_VMESIOAR_BASE & BRx_BA_MSK) |\
 623                          BRx_PS_16                        |\
 624                          BRx_MS_GPCM_P                    |\
 625                          BRx_V)
 626
 627 #define CONFIG_SYS_OR9_PRELIM  (P2SZ_TO_AM(CONFIG_SYS_VMESIOAR_SIZE)    |\
 628                          ORxG_CSNT                        |\
 629                          ORxG_ACS_DIV1                    |\
 630                          ORxG_SCY_5_CLK                   |\
 631                          ORxG_SETA)
 632
 633 #endif  /* __CONFIG_H */