include/configs/CPU86.h

   1 /*
   2  * (C) Copyright 2001-2005
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 /*
   9  * board/config.h - configuration options, board specific
  10  */
  11
  12 #ifndef __CONFIG_H
  13 #define __CONFIG_H
  14
  15 /*
  16  * High Level Configuration Options
  17  * (easy to change)
  18  */
  19
  20 #define CONFIG_CPU86            1       /* ...on a CPU86 board  */
  21 #define CONFIG_CPM2             1       /* Has a CPM2 */
  22
  23 #ifdef CONFIG_BOOT_ROM
  24 #define CONFIG_SYS_TEXT_BASE    0xFF800000
  25 #else
  26 #define CONFIG_SYS_TEXT_BASE    0xFF000000
  27 #endif
  28
  29 /*
  30  * select serial console configuration
  31  *
  32  * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
  33  * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
  34  * for SCC).
  35  *
  36  * if CONFIG_CONS_NONE is defined, then the serial console routines must
  37  * defined elsewhere (for example, on the cogent platform, there are serial
  38  * ports on the motherboard which are used for the serial console - see
  39  * cogent/cma101/serial.[ch]).
  40  */
  41 #undef  CONFIG_CONS_ON_SMC              /* define if console on SMC */
  42 #define CONFIG_CONS_ON_SCC              /* define if console on SCC */
  43 #undef  CONFIG_CONS_NONE                /* define if console on something else*/
  44 #define CONFIG_CONS_INDEX       1       /* which serial channel for console */
  45
  46 #if defined(CONFIG_CONS_NONE) || defined(CONFIG_CONS_USE_EXTC)
  47 #define CONFIG_BAUDRATE         230400
  48 #else
  49 #define CONFIG_BAUDRATE         9600
  50 #endif
  51
  52 /*
  53  * select ethernet configuration
  54  *
  55  * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
  56  * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
  57  * for FCC)
  58  *
  59  * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
  60  * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset.
  61  */
  62 #undef  CONFIG_ETHER_ON_SCC             /* define if ether on SCC       */
  63 #define CONFIG_ETHER_ON_FCC             /* define if ether on FCC       */
  64 #undef  CONFIG_ETHER_NONE               /* define if ether on something else */
  65 #define CONFIG_ETHER_INDEX      1       /* which SCC/FCC channel for ethernet */
  66
  67 #if defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 1)
  68
  69 /*
  70  * - Rx-CLK is CLK11
  71  * - Tx-CLK is CLK12
  72  * - RAM for BD/Buffers is on the 60x Bus (see 28-13)
  73  * - Enable Full Duplex in FSMR
  74  */
  75 # define CONFIG_SYS_CMXFCR_MASK1        (CMXFCR_FC1|CMXFCR_RF1CS_MSK|CMXFCR_TF1CS_MSK)
  76 # define CONFIG_SYS_CMXFCR_VALUE1       (CMXFCR_RF1CS_CLK11|CMXFCR_TF1CS_CLK12)
  77 # define CONFIG_SYS_CPMFCR_RAMTYPE      0
  78 # define CONFIG_SYS_FCC_PSMR            (FCC_PSMR_FDE|FCC_PSMR_LPB)
  79
  80 #elif defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 2)
  81
  82 /*
  83  * - Rx-CLK is CLK13
  84  * - Tx-CLK is CLK14
  85  * - RAM for BD/Buffers is on the 60x Bus (see 28-13)
  86  * - Enable Full Duplex in FSMR
  87  */
  88 # define CONFIG_SYS_CMXFCR_MASK2        (CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK)
  89 # define CONFIG_SYS_CMXFCR_VALUE2       (CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14)
  90 # define CONFIG_SYS_CPMFCR_RAMTYPE      0
  91 # define CONFIG_SYS_FCC_PSMR            (FCC_PSMR_FDE|FCC_PSMR_LPB)
  92
  93 #endif /* CONFIG_ETHER_ON_FCC, CONFIG_ETHER_INDEX */
  94
  95 /* system clock rate (CLKIN) - equal to the 60x and local bus speed */
  96 #define CONFIG_8260_CLKIN       64000000        /* in Hz */
  97
  98 #define CONFIG_BOOTDELAY        5       /* autoboot after 5 seconds     */
  99
 100 #define CONFIG_PREBOOT                                                          \
 101         "echo; "                                                                \
 102         "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS; "   \
 103         "echo"
 104
 105 #undef  CONFIG_BOOTARGS
 106 #define CONFIG_BOOTCOMMAND                                                      \
 107         "bootp; "                                                               \
 108         "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} "     \
 109         "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; "   \
 110         "bootm"
 111
 112 /*-----------------------------------------------------------------------
 113  * I2C/EEPROM/RTC configuration
 114  */
 115 #define CONFIG_SYS_I2C
 116 #define CONFIG_SYS_I2C_SOFT                     /* I2C bit-banged */
 117 #define CONFIG_SYS_I2C_SOFT_SPEED       50000
 118 #define CONFIG_SYS_I2C_SOFT_SLAVE       0xFE
 119
 120 /*
 121  * Software (bit-bang) I2C driver configuration
 122  */
 123 #define I2C_PORT        3               /* Port A=0, B=1, C=2, D=3 */
 124 #define I2C_ACTIVE      (iop->pdir |=  0x00010000)
 125 #define I2C_TRISTATE    (iop->pdir &= ~0x00010000)
 126 #define I2C_READ        ((iop->pdat & 0x00010000) != 0)
 127 #define I2C_SDA(bit)    if(bit) iop->pdat |=  0x00010000; \
 128                         else    iop->pdat &= ~0x00010000
 129 #define I2C_SCL(bit)    if(bit) iop->pdat |=  0x00020000; \
 130                         else    iop->pdat &= ~0x00020000
 131 #define I2C_DELAY       udelay(5)       /* 1/4 I2C clock duration */
 132
 133 #define CONFIG_RTC_PCF8563
 134 #define CONFIG_SYS_I2C_RTC_ADDR 0x51
 135
 136 #undef  CONFIG_WATCHDOG                 /* watchdog disabled            */
 137
 138 /*-----------------------------------------------------------------------
 139  * Miscellaneous configuration options
 140  */
 141
 142 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download  */
 143 #undef  CONFIG_SYS_LOADS_BAUD_CHANGE            /* don't allow baudrate change  */
 144
 145 /*
 146  * BOOTP options
 147  */
 148 #define CONFIG_BOOTP_SUBNETMASK
 149 #define CONFIG_BOOTP_GATEWAY
 150 #define CONFIG_BOOTP_HOSTNAME
 151 #define CONFIG_BOOTP_BOOTPATH
 152 #define CONFIG_BOOTP_BOOTFILESIZE
 153
 154
 155 /*
 156  * Command line configuration.
 157  */
 158 #include <config_cmd_default.h>
 159
 160 #define CONFIG_CMD_BEDBUG
 161 #define CONFIG_CMD_DATE
 162 #define CONFIG_CMD_DHCP
 163 #define CONFIG_CMD_EEPROM
 164 #define CONFIG_CMD_I2C
 165 #define CONFIG_CMD_NFS
 166 #define CONFIG_CMD_SNTP
 167
 168
 169 /*
 170  * Miscellaneous configurable options
 171  */
 172 #define CONFIG_SYS_LONGHELP                     /* undef to save memory         */
 173 #if defined(CONFIG_CMD_KGDB)
 174 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size      */
 175 #else
 176 #define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size      */
 177 #endif
 178 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
 179 #define CONFIG_SYS_MAXARGS      16              /* max number of command args   */
 180 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size    */
 181
 182 #define CONFIG_SYS_MEMTEST_START        0x0400000       /* memtest works on     */
 183 #define CONFIG_SYS_MEMTEST_END  0x0C00000       /* 4 ... 12 MB in DRAM  */
 184
 185 #define CONFIG_SYS_LOAD_ADDR    0x100000        /* default load address */
 186
 187 #define CONFIG_SYS_RESET_ADDRESS 0xFFF00100     /* "bad" address                */
 188
 189 /*
 190  * For booting Linux, the board info and command line data
 191  * have to be in the first 8 MB of memory, since this is
 192  * the maximum mapped by the Linux kernel during initialization.
 193  */
 194 #define CONFIG_SYS_BOOTMAPSZ            (8 << 20) /* Initial Memory map for Linux */
 195
 196 /*-----------------------------------------------------------------------
 197  * Flash configuration
 198  */
 199
 200 #define CONFIG_SYS_BOOTROM_BASE 0xFF800000
 201 #define CONFIG_SYS_BOOTROM_SIZE 0x00080000
 202 #define CONFIG_SYS_FLASH_BASE           0xFF000000
 203 #define CONFIG_SYS_FLASH_SIZE           0x00800000
 204
 205 /*-----------------------------------------------------------------------
 206  * FLASH organization
 207  */
 208 #define CONFIG_SYS_MAX_FLASH_BANKS      2       /* max num of memory banks      */
 209 #define CONFIG_SYS_MAX_FLASH_SECT       128     /* max num of sects on one chip */
 210
 211 #define CONFIG_SYS_FLASH_ERASE_TOUT     240000  /* Flash Erase Timeout (in ms)  */
 212 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (in ms)  */
 213
 214 /*-----------------------------------------------------------------------
 215  * Other areas to be mapped
 216  */
 217
 218 /* CS3: Dual ported SRAM */
 219 #define CONFIG_SYS_DPSRAM_BASE          0x40000000
 220 #define CONFIG_SYS_DPSRAM_SIZE          0x00020000
 221
 222 /* CS4: DiskOnChip */
 223 #define CONFIG_SYS_DOC_BASE             0xF4000000
 224 #define CONFIG_SYS_DOC_SIZE             0x00100000
 225
 226 /* CS5: FDC37C78 controller */
 227 #define CONFIG_SYS_FDC37C78_BASE        0xF1000000
 228 #define CONFIG_SYS_FDC37C78_SIZE        0x00100000
 229
 230 /* CS6: Board configuration registers */
 231 #define CONFIG_SYS_BCRS_BASE            0xF2000000
 232 #define CONFIG_SYS_BCRS_SIZE            0x00010000
 233
 234 /* CS7: VME Extended Access Range */
 235 #define CONFIG_SYS_VMEEAR_BASE          0x80000000
 236 #define CONFIG_SYS_VMEEAR_SIZE          0x01000000
 237
 238 /* CS8: VME Standard Access Range */
 239 #define CONFIG_SYS_VMESAR_BASE          0xFE000000
 240 #define CONFIG_SYS_VMESAR_SIZE          0x01000000
 241
 242 /* CS9: VME Short I/O Access Range */
 243 #define CONFIG_SYS_VMESIOAR_BASE        0xFD000000
 244 #define CONFIG_SYS_VMESIOAR_SIZE        0x01000000
 245
 246 /*-----------------------------------------------------------------------
 247  * Hard Reset Configuration Words
 248  *
 249  * if you change bits in the HRCW, you must also change the CONFIG_SYS_*
 250  * defines for the various registers affected by the HRCW e.g. changing
 251  * HRCW_DPPCxx requires you to also change CONFIG_SYS_SIUMCR.
 252  */
 253 #if defined(CONFIG_BOOT_ROM)
 254 #define CONFIG_SYS_HRCW_MASTER          (HRCW_CIP | HRCW_ISB100 | HRCW_BMS | \
 255                                  HRCW_BPS01 | HRCW_CS10PC01)
 256 #else
 257 #define CONFIG_SYS_HRCW_MASTER          (HRCW_CIP | HRCW_ISB100 | HRCW_BMS | HRCW_CS10PC01)
 258 #endif
 259
 260 /* no slaves so just fill with zeros */
 261 #define CONFIG_SYS_HRCW_SLAVE1          0
 262 #define CONFIG_SYS_HRCW_SLAVE2          0
 263 #define CONFIG_SYS_HRCW_SLAVE3          0
 264 #define CONFIG_SYS_HRCW_SLAVE4          0
 265 #define CONFIG_SYS_HRCW_SLAVE5          0
 266 #define CONFIG_SYS_HRCW_SLAVE6          0
 267 #define CONFIG_SYS_HRCW_SLAVE7          0
 268
 269 /*-----------------------------------------------------------------------
 270  * Internal Memory Mapped Register
 271  */
 272 #define CONFIG_SYS_IMMR         0xF0000000
 273
 274 /*-----------------------------------------------------------------------
 275  * Definitions for initial stack pointer and data area (in DPRAM)
 276  */
 277 #define CONFIG_SYS_INIT_RAM_ADDR        CONFIG_SYS_IMMR
 278 #define CONFIG_SYS_INIT_RAM_SIZE        0x4000  /* Size of used area in DPRAM    */
 279 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 280 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 281
 282 /*-----------------------------------------------------------------------
 283  * Start addresses for the final memory configuration
 284  * (Set up by the startup code)
 285  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 286  *
 287  * 60x SDRAM is mapped at CONFIG_SYS_SDRAM_BASE.
 288  */
 289 #define CONFIG_SYS_SDRAM_BASE           0x00000000
 290 #define CONFIG_SYS_SDRAM_MAX_SIZE       0x08000000      /* max. 128 MB          */
 291 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
 292 #define CONFIG_SYS_MONITOR_LEN          (256 << 10)     /* Reserve 256 kB for Monitor */
 293 #define CONFIG_SYS_MALLOC_LEN           (128 << 10)     /* Reserve 128 kB for malloc()*/
 294
 295 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
 296 # define CONFIG_SYS_RAMBOOT
 297 #endif
 298
 299 #if 0
 300 /* environment is in Flash */
 301 #define CONFIG_ENV_IS_IN_FLASH  1
 302 #ifdef CONFIG_BOOT_ROM
 303 # define CONFIG_ENV_ADDR                (CONFIG_SYS_FLASH_BASE+0x70000)
 304 # define CONFIG_ENV_SIZE                0x10000
 305 # define CONFIG_ENV_SECT_SIZE   0x10000
 306 #endif
 307 #else
 308 /* environment is in EEPROM */
 309 #define CONFIG_ENV_IS_IN_EEPROM 1
 310 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x58    /* EEPROM X24C16                */
 311 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  1
 312 /* mask of address bits that overflow into the "EEPROM chip address"    */
 313 #define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW     0x07
 314 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS       4
 315 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   10      /* and takes up to 10 msec */
 316 #define CONFIG_ENV_OFFSET               512
 317 #define CONFIG_ENV_SIZE         (2048 - 512)
 318 #endif
 319
 320 /*-----------------------------------------------------------------------
 321  * Cache Configuration
 322  */
 323 #define CONFIG_SYS_CACHELINE_SIZE      32      /* For MPC8260 CPU              */
 324 #if defined(CONFIG_CMD_KGDB)
 325 # define CONFIG_SYS_CACHELINE_SHIFT     5       /* log base 2 of the above value */
 326 #endif
 327
 328 /*-----------------------------------------------------------------------
 329  * HIDx - Hardware Implementation-dependent Registers                    2-11
 330  *-----------------------------------------------------------------------
 331  * HID0 also contains cache control - initially enable both caches and
 332  * invalidate contents, then the final state leaves only the instruction
 333  * cache enabled. Note that Power-On and Hard reset invalidate the caches,
 334  * but Soft reset does not.
 335  *
 336  * HID1 has only read-only information - nothing to set.
 337  */
 338 #define CONFIG_SYS_HID0_INIT   (HID0_ICE|HID0_DCE|HID0_ICFI|\
 339                          HID0_DCI|HID0_IFEM|HID0_ABE)
 340 #define CONFIG_SYS_HID0_FINAL  (HID0_IFEM|HID0_ABE)
 341 #define CONFIG_SYS_HID2        0
 342
 343 /*-----------------------------------------------------------------------
 344  * RMR - Reset Mode Register                                     5-5
 345  *-----------------------------------------------------------------------
 346  * turn on Checkstop Reset Enable
 347  */
 348 #define CONFIG_SYS_RMR         RMR_CSRE
 349
 350 /*-----------------------------------------------------------------------
 351  * BCR - Bus Configuration                                       4-25
 352  *-----------------------------------------------------------------------
 353  */
 354 #define BCR_APD01       0x10000000
 355 #define CONFIG_SYS_BCR          (BCR_APD01|BCR_ETM|BCR_LETM)    /* 8260 mode */
 356
 357 /*-----------------------------------------------------------------------
 358  * SIUMCR - SIU Module Configuration                             4-31
 359  *-----------------------------------------------------------------------
 360  */
 361 #define CONFIG_SYS_SIUMCR      (SIUMCR_BBD|SIUMCR_DPPC00|SIUMCR_APPC10|\
 362                          SIUMCR_CS10PC01|SIUMCR_BCTLC10)
 363
 364 /*-----------------------------------------------------------------------
 365  * SYPCR - System Protection Control                             4-35
 366  * SYPCR can only be written once after reset!
 367  *-----------------------------------------------------------------------
 368  * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
 369  */
 370 #if defined(CONFIG_WATCHDOG)
 371 #define CONFIG_SYS_SYPCR       (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
 372                          SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE)
 373 #else
 374 #define CONFIG_SYS_SYPCR       (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
 375                          SYPCR_SWRI|SYPCR_SWP)
 376 #endif /* CONFIG_WATCHDOG */
 377
 378 /*-----------------------------------------------------------------------
 379  * TMCNTSC - Time Counter Status and Control                     4-40
 380  *-----------------------------------------------------------------------
 381  * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
 382  * and enable Time Counter
 383  */
 384 #define CONFIG_SYS_TMCNTSC     (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
 385
 386 /*-----------------------------------------------------------------------
 387  * PISCR - Periodic Interrupt Status and Control                 4-42
 388  *-----------------------------------------------------------------------
 389  * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
 390  * Periodic timer
 391  */
 392 #define CONFIG_SYS_PISCR       (PISCR_PS|PISCR_PTF|PISCR_PTE)
 393
 394 /*-----------------------------------------------------------------------
 395  * SCCR - System Clock Control                                   9-8
 396  *-----------------------------------------------------------------------
 397  * Ensure DFBRG is Divide by 16
 398  */
 399 #define CONFIG_SYS_SCCR        SCCR_DFBRG01
 400
 401 /*-----------------------------------------------------------------------
 402  * RCCR - RISC Controller Configuration                         13-7
 403  *-----------------------------------------------------------------------
 404  */
 405 #define CONFIG_SYS_RCCR        0
 406
 407 #define CONFIG_SYS_MIN_AM_MASK  0xC0000000
 408 /*-----------------------------------------------------------------------
 409  * MPTPR - Memory Refresh Timer Prescaler Register              10-18
 410  *-----------------------------------------------------------------------
 411  */
 412 #define CONFIG_SYS_MPTPR       0x1F00
 413
 414 /*-----------------------------------------------------------------------
 415  * PSRT - Refresh Timer Register                                10-16
 416  *-----------------------------------------------------------------------
 417  */
 418 #define CONFIG_SYS_PSRT        0x0f
 419
 420 /*-----------------------------------------------------------------------
 421  * PSRT - SDRAM Mode Register                                   10-10
 422  *-----------------------------------------------------------------------
 423  */
 424
 425         /* SDRAM initialization values for 8-column chips
 426          */
 427 #define CONFIG_SYS_OR2_8COL     (CONFIG_SYS_MIN_AM_MASK         |\
 428                          ORxS_BPD_4                     |\
 429                          ORxS_ROWST_PBI0_A9             |\
 430                          ORxS_NUMR_12)
 431
 432 #define CONFIG_SYS_PSDMR_8COL   (PSDMR_SDAM_A13_IS_A5           |\
 433                          PSDMR_BSMA_A14_A16             |\
 434                          PSDMR_SDA10_PBI0_A10           |\
 435                          PSDMR_RFRC_7_CLK               |\
 436                          PSDMR_PRETOACT_2W              |\
 437                          PSDMR_ACTTORW_1W               |\
 438                          PSDMR_LDOTOPRE_1C              |\
 439                          PSDMR_WRC_1C                   |\
 440                          PSDMR_CL_2)
 441
 442         /* SDRAM initialization values for 9-column chips
 443          */
 444 #define CONFIG_SYS_OR2_9COL     (CONFIG_SYS_MIN_AM_MASK         |\
 445                          ORxS_BPD_4                     |\
 446                          ORxS_ROWST_PBI0_A7             |\
 447                          ORxS_NUMR_13)
 448
 449 #define CONFIG_SYS_PSDMR_9COL   (PSDMR_SDAM_A14_IS_A5           |\
 450                          PSDMR_BSMA_A13_A15             |\
 451                          PSDMR_SDA10_PBI0_A9            |\
 452                          PSDMR_RFRC_7_CLK               |\
 453                          PSDMR_PRETOACT_2W              |\
 454                          PSDMR_ACTTORW_1W               |\
 455                          PSDMR_LDOTOPRE_1C              |\
 456                          PSDMR_WRC_1C                   |\
 457                          PSDMR_CL_2)
 458
 459 /*
 460  * Init Memory Controller:
 461  *
 462  * Bank Bus     Machine PortSz  Device
 463  * ---- ---     ------- ------  ------
 464  *  0   60x     GPCM    8  bit  Boot ROM
 465  *  1   60x     GPCM    64 bit  FLASH
 466  *  2   60x     SDRAM   64 bit  SDRAM
 467  *
 468  */
 469
 470 #define CONFIG_SYS_MRS_OFFS     0x00000000
 471
 472 #ifdef CONFIG_BOOT_ROM
 473 /* Bank 0 - Boot ROM
 474  */
 475 #define CONFIG_SYS_BR0_PRELIM  ((CONFIG_SYS_BOOTROM_BASE & BRx_BA_MSK)|\
 476                          BRx_PS_8                       |\
 477                          BRx_MS_GPCM_P                  |\
 478                          BRx_V)
 479
 480 #define CONFIG_SYS_OR0_PRELIM  (P2SZ_TO_AM(CONFIG_SYS_BOOTROM_SIZE)   |\
 481                          ORxG_CSNT                      |\
 482                          ORxG_ACS_DIV1                  |\
 483                          ORxG_SCY_3_CLK                 |\
 484                          ORxU_EHTR_8IDLE)
 485
 486 /* Bank 1 - FLASH
 487  */
 488 #define CONFIG_SYS_BR1_PRELIM  ((CONFIG_SYS_FLASH_BASE & BRx_BA_MSK)  |\
 489                          BRx_PS_64                      |\
 490                          BRx_MS_GPCM_P                  |\
 491                          BRx_V)
 492
 493 #define CONFIG_SYS_OR1_PRELIM  (P2SZ_TO_AM(CONFIG_SYS_FLASH_SIZE)     |\
 494                          ORxG_CSNT                      |\
 495                          ORxG_ACS_DIV1                  |\
 496                          ORxG_SCY_3_CLK                 |\
 497                          ORxU_EHTR_8IDLE)
 498
 499 #else /* CONFIG_BOOT_ROM */
 500 /* Bank 0 - FLASH
 501  */
 502 #define CONFIG_SYS_BR0_PRELIM  ((CONFIG_SYS_FLASH_BASE & BRx_BA_MSK)  |\
 503                          BRx_PS_64                      |\
 504                          BRx_MS_GPCM_P                  |\
 505                          BRx_V)
 506
 507 #define CONFIG_SYS_OR0_PRELIM  (P2SZ_TO_AM(CONFIG_SYS_FLASH_SIZE)     |\
 508                          ORxG_CSNT                      |\
 509                          ORxG_ACS_DIV1                  |\
 510                          ORxG_SCY_3_CLK                 |\
 511                          ORxU_EHTR_8IDLE)
 512
 513 /* Bank 1 - Boot ROM
 514  */
 515 #define CONFIG_SYS_BR1_PRELIM  ((CONFIG_SYS_BOOTROM_BASE & BRx_BA_MSK)|\
 516                          BRx_PS_8                       |\
 517                          BRx_MS_GPCM_P                  |\
 518                          BRx_V)
 519
 520 #define CONFIG_SYS_OR1_PRELIM  (P2SZ_TO_AM(CONFIG_SYS_BOOTROM_SIZE)   |\
 521                          ORxG_CSNT                      |\
 522                          ORxG_ACS_DIV1                  |\
 523                          ORxG_SCY_3_CLK                 |\
 524                          ORxU_EHTR_8IDLE)
 525
 526 #endif /* CONFIG_BOOT_ROM */
 527
 528
 529 /* Bank 2 - 60x bus SDRAM
 530  */
 531 #ifndef CONFIG_SYS_RAMBOOT
 532 #define CONFIG_SYS_BR2_PRELIM  ((CONFIG_SYS_SDRAM_BASE & BRx_BA_MSK)  |\
 533                          BRx_PS_64                      |\
 534                          BRx_MS_SDRAM_P                 |\
 535                          BRx_V)
 536
 537 #define CONFIG_SYS_OR2_PRELIM    CONFIG_SYS_OR2_9COL
 538
 539 #define CONFIG_SYS_PSDMR         CONFIG_SYS_PSDMR_9COL
 540 #endif /* CONFIG_SYS_RAMBOOT */
 541
 542 /* Bank 3 - Dual Ported SRAM
 543  */
 544 #define CONFIG_SYS_BR3_PRELIM  ((CONFIG_SYS_DPSRAM_BASE & BRx_BA_MSK) |\
 545                          BRx_PS_16                      |\
 546                          BRx_MS_GPCM_P                  |\
 547                          BRx_V)
 548
 549 #define CONFIG_SYS_OR3_PRELIM  (P2SZ_TO_AM(CONFIG_SYS_DPSRAM_SIZE)    |\
 550                          ORxG_CSNT                      |\
 551                          ORxG_ACS_DIV1                  |\
 552                          ORxG_SCY_5_CLK                 |\
 553                          ORxG_SETA)
 554
 555 /* Bank 4 - DiskOnChip
 556  */
 557 #define CONFIG_SYS_BR4_PRELIM  ((CONFIG_SYS_DOC_BASE & BRx_BA_MSK)    |\
 558                          BRx_PS_8                       |\
 559                          BRx_MS_GPCM_P                  |\
 560                          BRx_V)
 561
 562 #define CONFIG_SYS_OR4_PRELIM  (P2SZ_TO_AM(CONFIG_SYS_DOC_SIZE)       |\
 563                          ORxG_ACS_DIV2                  |\
 564                          ORxG_SCY_5_CLK                 |\
 565                          ORxU_EHTR_8IDLE)
 566
 567 /* Bank 5 - FDC37C78 controller
 568  */
 569 #define CONFIG_SYS_BR5_PRELIM  ((CONFIG_SYS_FDC37C78_BASE & BRx_BA_MSK) |\
 570                          BRx_PS_8                         |\
 571                          BRx_MS_GPCM_P                    |\
 572                          BRx_V)
 573
 574 #define CONFIG_SYS_OR5_PRELIM  (P2SZ_TO_AM(CONFIG_SYS_FDC37C78_SIZE)    |\
 575                          ORxG_ACS_DIV2                    |\
 576                          ORxG_SCY_8_CLK                   |\
 577                          ORxU_EHTR_8IDLE)
 578
 579 /* Bank 6 - Board control registers
 580  */
 581 #define CONFIG_SYS_BR6_PRELIM  ((CONFIG_SYS_BCRS_BASE & BRx_BA_MSK)   |\
 582                          BRx_PS_8                       |\
 583                          BRx_MS_GPCM_P                  |\
 584                          BRx_V)
 585
 586 #define CONFIG_SYS_OR6_PRELIM  (P2SZ_TO_AM(CONFIG_SYS_BCRS_SIZE)      |\
 587                          ORxG_CSNT                      |\
 588                          ORxG_SCY_5_CLK)
 589
 590 /* Bank 7 - VME Extended Access Range
 591  */
 592 #define CONFIG_SYS_BR7_PRELIM  ((CONFIG_SYS_VMEEAR_BASE & BRx_BA_MSK) |\
 593                          BRx_PS_32                      |\
 594                          BRx_MS_GPCM_P                  |\
 595                          BRx_V)
 596
 597 #define CONFIG_SYS_OR7_PRELIM  (P2SZ_TO_AM(CONFIG_SYS_VMEEAR_SIZE)    |\
 598                          ORxG_CSNT                      |\
 599                          ORxG_ACS_DIV1                  |\
 600                          ORxG_SCY_5_CLK                 |\
 601                          ORxG_SETA)
 602
 603 /* Bank 8 - VME Standard Access Range
 604  */
 605 #define CONFIG_SYS_BR8_PRELIM  ((CONFIG_SYS_VMESAR_BASE & BRx_BA_MSK) |\
 606                          BRx_PS_16                      |\
 607                          BRx_MS_GPCM_P                  |\
 608                          BRx_V)
 609
 610 #define CONFIG_SYS_OR8_PRELIM  (P2SZ_TO_AM(CONFIG_SYS_VMESAR_SIZE)    |\
 611                          ORxG_CSNT                      |\
 612                          ORxG_ACS_DIV1                  |\
 613                          ORxG_SCY_5_CLK                 |\
 614                          ORxG_SETA)
 615
 616 /* Bank 9 - VME Short I/O Access Range
 617  */
 618 #define CONFIG_SYS_BR9_PRELIM  ((CONFIG_SYS_VMESIOAR_BASE & BRx_BA_MSK) |\
 619                          BRx_PS_16                        |\
 620                          BRx_MS_GPCM_P                    |\
 621                          BRx_V)
 622
 623 #define CONFIG_SYS_OR9_PRELIM  (P2SZ_TO_AM(CONFIG_SYS_VMESIOAR_SIZE)    |\
 624                          ORxG_CSNT                        |\
 625                          ORxG_ACS_DIV1                    |\
 626                          ORxG_SCY_5_CLK                   |\
 627                          ORxG_SETA)
 628
 629 #endif  /* __CONFIG_H */