2 * (C) Copyright 2001-2004
3 * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 * board/config.h - configuration options, board specific
32 * High Level Configuration Options
36 #define CONFIG_405GP 1 /* This is a PPC405 CPU */
37 #define CONFIG_4xx 1 /* ...member of PPC4xx family */
38 #define CONFIG_CPCI405 1 /* ...on a CPCI405 board */
39 #define CONFIG_CPCI405_VER2 1 /* ...version 2 */
40 #undef CONFIG_CPCI405_6U /* enable this for 6U boards */
42 #define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */
43 #define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */
45 #define CONFIG_SYS_CLK_FREQ 33330000 /* external frequency to pll */
47 #define CONFIG_BAUDRATE 9600
48 #define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */
50 #undef CONFIG_BOOTARGS
51 #undef CONFIG_BOOTCOMMAND
53 #define CONFIG_PREBOOT /* enable preboot variable */
55 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
56 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
58 #define CONFIG_PPC4xx_EMAC
59 #define CONFIG_MII 1 /* MII PHY management */
60 #define CONFIG_PHY_ADDR 0 /* PHY address */
61 #define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */
62 #define CONFIG_RESET_PHY_R 1 /* use reset_phy() to disable phy sleep mode */
64 #define CONFIG_NET_MULTI 1
65 #undef CONFIG_HAS_ETH1
67 #define CONFIG_RTC_M48T35A 1 /* ST Electronics M48 timekeeper */
72 #define CONFIG_BOOTP_SUBNETMASK
73 #define CONFIG_BOOTP_GATEWAY
74 #define CONFIG_BOOTP_HOSTNAME
75 #define CONFIG_BOOTP_BOOTPATH
76 #define CONFIG_BOOTP_DNS
77 #define CONFIG_BOOTP_DNS2
78 #define CONFIG_BOOTP_SEND_HOSTNAME
82 * Command line configuration.
84 #include <config_cmd_default.h>
86 #define CONFIG_CMD_DHCP
87 #define CONFIG_CMD_PCI
88 #define CONFIG_CMD_IRQ
89 #define CONFIG_CMD_IDE
90 #define CONFIG_CMD_FAT
91 #define CONFIG_CMD_ELF
92 #define CONFIG_CMD_DATE
93 #define CONFIG_CMD_I2C
94 #define CONFIG_CMD_MII
95 #define CONFIG_CMD_PING
96 #define CONFIG_CMD_BSP
97 #define CONFIG_CMD_EEPROM
99 #define CONFIG_MAC_PARTITION
100 #define CONFIG_DOS_PARTITION
102 #define CONFIG_SUPPORT_VFAT
104 #undef CONFIG_WATCHDOG /* watchdog disabled */
106 #define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
109 * Miscellaneous configurable options
111 #define CONFIG_SYS_LONGHELP /* undef to save memory */
112 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
114 #undef CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
115 #ifdef CONFIG_SYS_HUSH_PARSER
116 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
119 #if defined(CONFIG_CMD_KGDB)
120 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
122 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
124 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
125 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
126 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
128 #define CONFIG_SYS_DEVICE_NULLDEV 1 /* include nulldev device */
130 #define CONFIG_SYS_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/
132 #define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */
134 #define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
135 #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
137 #undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */
138 #define CONFIG_SYS_BASE_BAUD 691200
140 /* The following table includes the supported baudrates */
141 #define CONFIG_SYS_BAUDRATE_TABLE \
142 { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \
143 57600, 115200, 230400, 460800, 921600 }
145 #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
146 #define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */
148 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
150 #define CONFIG_CMDLINE_EDITING /* add command line history */
152 #define CONFIG_LOOPW 1 /* enable loopw command */
154 #define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
156 #define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
158 #define CONFIG_AUTOBOOT_KEYED 1
159 #define CONFIG_AUTOBOOT_PROMPT \
160 "Press SPACE to abort autoboot in %d seconds\n", bootdelay
161 #undef CONFIG_AUTOBOOT_DELAY_STR
162 #define CONFIG_AUTOBOOT_STOP_STR " "
164 #define CONFIG_SYS_RX_ETH_BUFFER 16 /* use 16 rx buffer on 405 emac */
166 /*-----------------------------------------------------------------------
168 *-----------------------------------------------------------------------
170 #define PCI_HOST_ADAPTER 0 /* configure as pci adapter */
171 #define PCI_HOST_FORCE 1 /* configure as pci host */
172 #define PCI_HOST_AUTO 2 /* detected via arbiter enable */
174 #define CONFIG_PCI /* include pci support */
175 #define CONFIG_PCI_HOST PCI_HOST_AUTO /* select pci host function */
176 #define CONFIG_PCI_PNP /* do pci plug-and-play */
177 /* resource configuration */
179 #define CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */
181 #define CONFIG_PCI_CONFIG_HOST_BRIDGE 1 /* don't skip host bridge config*/
183 #define CONFIG_PCI_BOOTDELAY 0 /* enable pci bootdelay variable*/
185 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */
186 #define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0405 /* PCI Device ID: CPCI-405 */
187 #define CONFIG_SYS_PCI_SUBSYS_DEVICEID2 0x0406 /* PCI Device ID: CPCI-405-A */
188 #define CONFIG_SYS_PCI_CLASSCODE 0x0b20 /* PCI Class Code: Processor/PPC*/
189 #define CONFIG_SYS_PCI_PTM1LA (bd->bi_memstart) /* point to sdram */
190 #define CONFIG_SYS_PCI_PTM1MS (~(bd->bi_memsize - 1) | 1) /* memsize, enable hard-wired to 1 */
191 #define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
192 #define CONFIG_SYS_PCI_PTM2LA 0xffc00000 /* point to flash */
193 #define CONFIG_SYS_PCI_PTM2MS 0xffc00001 /* 4MB, enable */
194 #define CONFIG_SYS_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */
196 #define CONFIG_PCI_4xx_PTM_OVERWRITE 1 /* overwrite PTMx settings by env */
198 /*-----------------------------------------------------------------------
200 *-----------------------------------------------------------------------
202 #undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */
203 #undef CONFIG_IDE_LED /* no led for ide supported */
204 #define CONFIG_IDE_RESET 1 /* reset for ide supported */
206 #define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE busses */
207 #define CONFIG_SYS_IDE_MAXDEVICE (CONFIG_SYS_IDE_MAXBUS*1) /* max. 1 drives per IDE bus */
209 #define CONFIG_SYS_ATA_BASE_ADDR 0xF0100000
210 #define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
212 #define CONFIG_SYS_ATA_DATA_OFFSET 0x0000 /* Offset for data I/O */
213 #define CONFIG_SYS_ATA_REG_OFFSET 0x0000 /* Offset for normal register accesses */
214 #define CONFIG_SYS_ATA_ALT_OFFSET 0x0000 /* Offset for alternate registers */
216 /*-----------------------------------------------------------------------
217 * Start addresses for the final memory configuration
218 * (Set up by the startup code)
219 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
221 #define CONFIG_SYS_SDRAM_BASE 0x00000000
222 #define CONFIG_SYS_FLASH_BASE 0xFFFC0000
223 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
224 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */
225 #define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */
227 #define CONFIG_PRAM 0 /* use pram variable to overwrite */
230 * For booting Linux, the board info and command line data
231 * have to be in the first 8 MB of memory, since this is
232 * the maximum mapped by the Linux kernel during initialization.
234 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
236 #define CONFIG_OF_LIBFDT
237 #define CONFIG_OF_BOARD_SETUP
239 /*-----------------------------------------------------------------------
242 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
243 #define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
245 #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
246 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
248 #define CONFIG_SYS_FLASH_WORD_SIZE unsigned short /* flash word size (width) */
249 #define CONFIG_SYS_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */
250 #define CONFIG_SYS_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */
252 * The following defines are added for buggy IOP480 byte interface.
253 * All other boards should use the standard values (CPCI405 etc.)
255 #define CONFIG_SYS_FLASH_READ0 0x0000 /* 0 is standard */
256 #define CONFIG_SYS_FLASH_READ1 0x0001 /* 1 is standard */
257 #define CONFIG_SYS_FLASH_READ2 0x0002 /* 2 is standard */
259 #define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
261 #if 0 /* Use NVRAM for environment variables */
262 /*-----------------------------------------------------------------------
265 #define CONFIG_ENV_IS_IN_NVRAM 1 /* use NVRAM for environment vars */
266 #define CONFIG_ENV_SIZE 0x0ff8 /* Size of Environment vars */
267 #define CONFIG_ENV_ADDR \
268 (CONFIG_SYS_NVRAM_BASE_ADDR+CONFIG_SYS_NVRAM_SIZE-(CONFIG_ENV_SIZE+8)) /* Env */
270 #else /* Use EEPROM for environment variables */
272 #define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */
273 #define CONFIG_ENV_OFFSET 0x000 /* environment starts at the beginning of the EEPROM */
274 #define CONFIG_ENV_SIZE 0x800 /* 2048 bytes may be used for env vars*/
275 /* total size of a CAT24WC16 is 2048 bytes */
278 #define CONFIG_SYS_NVRAM_BASE_ADDR 0xf0200000 /* NVRAM base address */
279 #define CONFIG_SYS_NVRAM_SIZE (32*1024) /* NVRAM size */
280 #define CONFIG_SYS_VXWORKS_MAC_PTR (CONFIG_SYS_NVRAM_BASE_ADDR+0x6900) /* VxWorks eth-addr*/
282 /*-----------------------------------------------------------------------
283 * I2C EEPROM (CAT24WC16) for environment
285 #define CONFIG_HARD_I2C /* I2c with hardware support */
286 #define CONFIG_PPC4XX_I2C /* use PPC4xx driver */
287 #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
288 #define CONFIG_SYS_I2C_SLAVE 0x7F
290 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */
291 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
292 /* mask of address bits that overflow into the "EEPROM chip address" */
293 #define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07
294 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */
295 /* 16 byte page write mode using*/
296 /* last 4 bits of the address */
297 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
300 * Init Memory Controller:
302 * BR0/1 and OR0/1 (FLASH)
305 #define FLASH_BASE0_PRELIM 0xFF800000 /* FLASH bank #0 */
306 #define FLASH_BASE1_PRELIM 0xFFC00000 /* FLASH bank #1 */
308 /*-----------------------------------------------------------------------
309 * External Bus Controller (EBC) Setup
312 /* Memory Bank 0 (Flash Bank 0) initialization */
313 #define CONFIG_SYS_EBC_PB0AP 0x92015480
314 #define CONFIG_SYS_EBC_PB0CR 0xFFC5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
316 /* Memory Bank 1 (Flash Bank 1) initialization */
317 #define CONFIG_SYS_EBC_PB1AP 0x92015480
318 #define CONFIG_SYS_EBC_PB1CR 0xFF85A000 /* BAS=0xFF8,BS=4MB,BU=R/W,BW=16bit */
320 /* Memory Bank 2 (CAN0, 1) initialization */
321 #define CONFIG_SYS_EBC_PB2AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
322 #define CONFIG_SYS_EBC_PB2CR 0xF0018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */
323 #define CONFIG_SYS_LED_ADDR 0xF0000380
325 /* Memory Bank 3 (CompactFlash IDE) initialization */
326 #define CONFIG_SYS_EBC_PB3AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
327 #define CONFIG_SYS_EBC_PB3CR 0xF011A000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */
329 /* Memory Bank 4 (NVRAM/RTC) initialization */
330 /*#define CONFIG_SYS_EBC_PB4AP 0x01805280 / * TWT=3,WBN=1,WBF=1,TH=1,SOR=1 */
331 #define CONFIG_SYS_EBC_PB4AP 0x01805680 /* TWT=3,WBN=1,WBF=1,TH=3,SOR=1 */
332 #define CONFIG_SYS_EBC_PB4CR 0xF0218000 /* BAS=0xF02,BS=1MB,BU=R/W,BW=8bit */
334 /* Memory Bank 5 (optional Quart) initialization */
335 #define CONFIG_SYS_EBC_PB5AP 0x04005B80 /* TWT=8,WBN=1,WBF=1,TH=5,RE=1,SOR=1*/
336 #define CONFIG_SYS_EBC_PB5CR 0xF0318000 /* BAS=0xF03,BS=1MB,BU=R/W,BW=8bit */
338 /* Memory Bank 6 (FPGA internal) initialization */
339 #define CONFIG_SYS_EBC_PB6AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
340 #define CONFIG_SYS_EBC_PB6CR 0xF041A000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */
341 #define CONFIG_SYS_FPGA_BASE_ADDR 0xF0400000
343 /*-----------------------------------------------------------------------
346 /* FPGA internal regs */
347 #define CONFIG_SYS_FPGA_MODE 0x00
348 #define CONFIG_SYS_FPGA_STATUS 0x02
349 #define CONFIG_SYS_FPGA_TS 0x04
350 #define CONFIG_SYS_FPGA_TS_LOW 0x06
351 #define CONFIG_SYS_FPGA_TS_CAP0 0x10
352 #define CONFIG_SYS_FPGA_TS_CAP0_LOW 0x12
353 #define CONFIG_SYS_FPGA_TS_CAP1 0x14
354 #define CONFIG_SYS_FPGA_TS_CAP1_LOW 0x16
355 #define CONFIG_SYS_FPGA_TS_CAP2 0x18
356 #define CONFIG_SYS_FPGA_TS_CAP2_LOW 0x1a
357 #define CONFIG_SYS_FPGA_TS_CAP3 0x1c
358 #define CONFIG_SYS_FPGA_TS_CAP3_LOW 0x1e
361 #define CONFIG_SYS_FPGA_MODE_CF_RESET 0x0001
362 #define CONFIG_SYS_FPGA_MODE_DUART_RESET 0x0002
363 #define CONFIG_SYS_FPGA_MODE_ENABLE_OUTPUT 0x0004 /* only set on CPCI-405 Ver 3 */
364 #define CONFIG_SYS_FPGA_MODE_TS_IRQ_ENABLE 0x0100
365 #define CONFIG_SYS_FPGA_MODE_TS_IRQ_CLEAR 0x1000
366 #define CONFIG_SYS_FPGA_MODE_TS_CLEAR 0x2000
368 /* FPGA Status Reg */
369 #define CONFIG_SYS_FPGA_STATUS_DIP0 0x0001
370 #define CONFIG_SYS_FPGA_STATUS_DIP1 0x0002
371 #define CONFIG_SYS_FPGA_STATUS_DIP2 0x0004
372 #define CONFIG_SYS_FPGA_STATUS_FLASH 0x0008
373 #define CONFIG_SYS_FPGA_STATUS_TS_IRQ 0x1000
375 #define CONFIG_SYS_FPGA_SPARTAN2 1 /* using Xilinx Spartan 2 now */
376 #define CONFIG_SYS_FPGA_MAX_SIZE 32*1024 /* 32kByte is enough for XC2S15 */
378 /* FPGA program pin configuration */
379 #define CONFIG_SYS_FPGA_PRG 0x04000000 /* FPGA program pin (ppc output) */
380 #define CONFIG_SYS_FPGA_CLK 0x02000000 /* FPGA clk pin (ppc output) */
381 #define CONFIG_SYS_FPGA_DATA 0x01000000 /* FPGA data pin (ppc output) */
382 #define CONFIG_SYS_FPGA_INIT 0x00010000 /* FPGA init pin (ppc input) */
383 #define CONFIG_SYS_FPGA_DONE 0x00008000 /* FPGA done pin (ppc input) */
385 /*-----------------------------------------------------------------------
386 * Definitions for initial stack pointer and data area (in data cache)
388 #define CONFIG_SYS_INIT_DCACHE_CS 7 /* use cs # 7 for data cache memory */
390 #define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 /* use data cache */
391 #define CONFIG_SYS_INIT_RAM_END 0x2000 /* End of used area in RAM */
392 #define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
393 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
394 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
398 * Internal Definitions
402 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
403 #define BOOTFLAG_WARM 0x02 /* Software reboot */
405 #endif /* __CONFIG_H */