2 * (C) Copyright 2001-2004
3 * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
5 * SPDX-License-Identifier: GPL-2.0+
9 * board/config.h - configuration options, board specific
16 * High Level Configuration Options
20 #define CONFIG_405GP 1 /* This is a PPC405 CPU */
21 #define CONFIG_CPCI405 1 /* ...on a CPCI405 board */
22 #define CONFIG_CPCI405_VER2 1 /* ...version 2 */
23 #undef CONFIG_CPCI405_6U /* enable this for 6U boards */
25 #define CONFIG_SYS_TEXT_BASE 0xFFFC0000
26 #define CONFIG_DISPLAY_BOARDINFO
28 #define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */
29 #define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */
31 #define CONFIG_SYS_CLK_FREQ 33330000 /* external frequency to pll */
33 #define CONFIG_BAUDRATE 9600
34 #define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */
36 #undef CONFIG_BOOTARGS
37 #undef CONFIG_BOOTCOMMAND
39 #define CONFIG_PREBOOT /* enable preboot variable */
41 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
42 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
44 #define CONFIG_PPC4xx_EMAC
45 #define CONFIG_MII 1 /* MII PHY management */
46 #define CONFIG_PHY_ADDR 0 /* PHY address */
47 #define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */
48 #define CONFIG_RESET_PHY_R 1 /* use reset_phy() to disable phy sleep mode */
50 #undef CONFIG_HAS_ETH1
52 #define CONFIG_RTC_M48T35A 1 /* ST Electronics M48 timekeeper */
57 #define CONFIG_BOOTP_SUBNETMASK
58 #define CONFIG_BOOTP_GATEWAY
59 #define CONFIG_BOOTP_HOSTNAME
60 #define CONFIG_BOOTP_BOOTPATH
61 #define CONFIG_BOOTP_DNS
62 #define CONFIG_BOOTP_DNS2
63 #define CONFIG_BOOTP_SEND_HOSTNAME
67 * Command line configuration.
69 #define CONFIG_CMD_PCI
70 #define CONFIG_CMD_IRQ
71 #define CONFIG_CMD_IDE
72 #define CONFIG_CMD_FAT
73 #define CONFIG_CMD_DATE
74 #define CONFIG_CMD_MII
75 #define CONFIG_CMD_BSP
76 #define CONFIG_CMD_EEPROM
78 #define CONFIG_MAC_PARTITION
79 #define CONFIG_DOS_PARTITION
81 #define CONFIG_SUPPORT_VFAT
83 #undef CONFIG_WATCHDOG /* watchdog disabled */
85 #define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
88 * Miscellaneous configurable options
90 #undef CONFIG_SYS_LONGHELP /* undef to save memory */
93 #if defined(CONFIG_CMD_KGDB)
94 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
96 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
98 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
99 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
100 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
102 #define CONFIG_SYS_DEVICE_NULLDEV 1 /* include nulldev device */
104 #define CONFIG_SYS_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/
106 #define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */
108 #define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
109 #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
111 #define CONFIG_CONS_INDEX 1 /* Use UART0 */
112 #define CONFIG_SYS_NS16550_SERIAL
113 #define CONFIG_SYS_NS16550_REG_SIZE 1
114 #define CONFIG_SYS_NS16550_CLK get_serial_clock()
116 #undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */
117 #define CONFIG_SYS_BASE_BAUD 691200
119 /* The following table includes the supported baudrates */
120 #define CONFIG_SYS_BAUDRATE_TABLE \
121 { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \
122 57600, 115200, 230400, 460800, 921600 }
124 #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
125 #define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */
127 #define CONFIG_CMDLINE_EDITING /* add command line history */
129 #define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
131 #define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
133 #define CONFIG_SYS_RX_ETH_BUFFER 16 /* use 16 rx buffer on 405 emac */
135 /*-----------------------------------------------------------------------
137 *-----------------------------------------------------------------------
139 #define PCI_HOST_ADAPTER 0 /* configure as pci adapter */
140 #define PCI_HOST_FORCE 1 /* configure as pci host */
141 #define PCI_HOST_AUTO 2 /* detected via arbiter enable */
143 #define CONFIG_PCI /* include pci support */
144 #define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
145 #define CONFIG_PCI_HOST PCI_HOST_AUTO /* select pci host function */
146 #define CONFIG_PCI_PNP /* do pci plug-and-play */
147 /* resource configuration */
149 #define CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */
151 #define CONFIG_PCI_CONFIG_HOST_BRIDGE 1 /* don't skip host bridge config*/
153 #define CONFIG_PCI_BOOTDELAY 0 /* enable pci bootdelay variable*/
155 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */
156 #define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0405 /* PCI Device ID: CPCI-405 */
157 #define CONFIG_SYS_PCI_SUBSYS_DEVICEID2 0x0406 /* PCI Device ID: CPCI-405-A */
158 #define CONFIG_SYS_PCI_CLASSCODE 0x0b20 /* PCI Class Code: Processor/PPC*/
159 #define CONFIG_SYS_PCI_PTM1LA (bd->bi_memstart) /* point to sdram */
160 #define CONFIG_SYS_PCI_PTM1MS (~(bd->bi_memsize - 1) | 1) /* memsize, enable hard-wired to 1 */
161 #define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
162 #define CONFIG_SYS_PCI_PTM2LA 0xffc00000 /* point to flash */
163 #define CONFIG_SYS_PCI_PTM2MS 0xffc00001 /* 4MB, enable */
164 #define CONFIG_SYS_PCI_PTM2PCI (bd->bi_memsize) /* host use this pci address */
166 #define CONFIG_PCI_4xx_PTM_OVERWRITE 1 /* overwrite PTMx settings by env */
168 /*-----------------------------------------------------------------------
170 *-----------------------------------------------------------------------
172 #undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */
173 #undef CONFIG_IDE_LED /* no led for ide supported */
174 #define CONFIG_IDE_RESET 1 /* reset for ide supported */
176 #define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE busses */
177 #define CONFIG_SYS_IDE_MAXDEVICE (CONFIG_SYS_IDE_MAXBUS*1) /* max. 1 drives per IDE bus */
179 #define CONFIG_SYS_ATA_BASE_ADDR 0xF0100000
180 #define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
182 #define CONFIG_SYS_ATA_DATA_OFFSET 0x0000 /* Offset for data I/O */
183 #define CONFIG_SYS_ATA_REG_OFFSET 0x0000 /* Offset for normal register accesses */
184 #define CONFIG_SYS_ATA_ALT_OFFSET 0x0000 /* Offset for alternate registers */
186 /*-----------------------------------------------------------------------
187 * Start addresses for the final memory configuration
188 * (Set up by the startup code)
189 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
191 #define CONFIG_SYS_SDRAM_BASE 0x00000000
192 #define CONFIG_SYS_FLASH_BASE 0xFFFC0000
193 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
194 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */
195 #define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */
197 #define CONFIG_PRAM 0 /* use pram variable to overwrite */
200 * For booting Linux, the board info and command line data
201 * have to be in the first 8 MB of memory, since this is
202 * the maximum mapped by the Linux kernel during initialization.
204 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
206 /*-----------------------------------------------------------------------
209 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
210 #define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
212 #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
213 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
215 #define CONFIG_SYS_FLASH_WORD_SIZE unsigned short /* flash word size (width) */
216 #define CONFIG_SYS_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */
217 #define CONFIG_SYS_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */
219 * The following defines are added for buggy IOP480 byte interface.
220 * All other boards should use the standard values (CPCI405 etc.)
222 #define CONFIG_SYS_FLASH_READ0 0x0000 /* 0 is standard */
223 #define CONFIG_SYS_FLASH_READ1 0x0001 /* 1 is standard */
224 #define CONFIG_SYS_FLASH_READ2 0x0002 /* 2 is standard */
226 #define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
228 #if 0 /* Use NVRAM for environment variables */
229 /*-----------------------------------------------------------------------
232 #define CONFIG_ENV_IS_IN_NVRAM 1 /* use NVRAM for environment vars */
233 #define CONFIG_ENV_SIZE 0x0ff8 /* Size of Environment vars */
234 #define CONFIG_ENV_ADDR \
235 (CONFIG_SYS_NVRAM_BASE_ADDR+CONFIG_SYS_NVRAM_SIZE-(CONFIG_ENV_SIZE+8)) /* Env */
237 #else /* Use EEPROM for environment variables */
239 #define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */
240 #define CONFIG_ENV_OFFSET 0x000 /* environment starts at the beginning of the EEPROM */
241 #define CONFIG_ENV_SIZE 0x800 /* 2048 bytes may be used for env vars*/
242 /* total size of a CAT24WC16 is 2048 bytes */
245 #define CONFIG_SYS_NVRAM_BASE_ADDR 0xf0200000 /* NVRAM base address */
246 #define CONFIG_SYS_NVRAM_SIZE (32*1024) /* NVRAM size */
247 #define CONFIG_SYS_VXWORKS_MAC_PTR (CONFIG_SYS_NVRAM_BASE_ADDR+0x6900) /* VxWorks eth-addr*/
249 /*-----------------------------------------------------------------------
250 * I2C EEPROM (CAT24WC16) for environment
252 #define CONFIG_SYS_I2C
253 #define CONFIG_SYS_I2C_PPC4XX
254 #define CONFIG_SYS_I2C_PPC4XX_CH0
255 #define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000
256 #define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F
258 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */
259 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
260 /* mask of address bits that overflow into the "EEPROM chip address" */
261 #define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07
262 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */
263 /* 16 byte page write mode using*/
264 /* last 4 bits of the address */
265 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
268 * Init Memory Controller:
270 * BR0/1 and OR0/1 (FLASH)
273 #define FLASH_BASE0_PRELIM 0xFF800000 /* FLASH bank #0 */
274 #define FLASH_BASE1_PRELIM 0xFFC00000 /* FLASH bank #1 */
276 /*-----------------------------------------------------------------------
277 * External Bus Controller (EBC) Setup
280 /* Memory Bank 0 (Flash Bank 0) initialization */
281 #define CONFIG_SYS_EBC_PB0AP 0x92015480
282 #define CONFIG_SYS_EBC_PB0CR 0xFFC5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
284 /* Memory Bank 1 (Flash Bank 1) initialization */
285 #define CONFIG_SYS_EBC_PB1AP 0x92015480
286 #define CONFIG_SYS_EBC_PB1CR 0xFF85A000 /* BAS=0xFF8,BS=4MB,BU=R/W,BW=16bit */
288 /* Memory Bank 2 (CAN0, 1) initialization */
289 #define CONFIG_SYS_EBC_PB2AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
290 #define CONFIG_SYS_EBC_PB2CR 0xF0018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */
291 #define CONFIG_SYS_LED_ADDR 0xF0000380
293 /* Memory Bank 3 (CompactFlash IDE) initialization */
294 #define CONFIG_SYS_EBC_PB3AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
295 #define CONFIG_SYS_EBC_PB3CR 0xF011A000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */
297 /* Memory Bank 4 (NVRAM/RTC) initialization */
298 /*#define CONFIG_SYS_EBC_PB4AP 0x01805280 / * TWT=3,WBN=1,WBF=1,TH=1,SOR=1 */
299 #define CONFIG_SYS_EBC_PB4AP 0x01805680 /* TWT=3,WBN=1,WBF=1,TH=3,SOR=1 */
300 #define CONFIG_SYS_EBC_PB4CR 0xF0218000 /* BAS=0xF02,BS=1MB,BU=R/W,BW=8bit */
302 /* Memory Bank 5 (optional Quart) initialization */
303 #define CONFIG_SYS_EBC_PB5AP 0x04005B80 /* TWT=8,WBN=1,WBF=1,TH=5,RE=1,SOR=1*/
304 #define CONFIG_SYS_EBC_PB5CR 0xF0318000 /* BAS=0xF03,BS=1MB,BU=R/W,BW=8bit */
306 /* Memory Bank 6 (FPGA internal) initialization */
307 #define CONFIG_SYS_EBC_PB6AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
308 #define CONFIG_SYS_EBC_PB6CR 0xF041A000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */
309 #define CONFIG_SYS_FPGA_BASE_ADDR 0xF0400000
311 /*-----------------------------------------------------------------------
314 /* FPGA internal regs */
315 #define CONFIG_SYS_FPGA_MODE 0x00
316 #define CONFIG_SYS_FPGA_STATUS 0x02
317 #define CONFIG_SYS_FPGA_TS 0x04
318 #define CONFIG_SYS_FPGA_TS_LOW 0x06
319 #define CONFIG_SYS_FPGA_TS_CAP0 0x10
320 #define CONFIG_SYS_FPGA_TS_CAP0_LOW 0x12
321 #define CONFIG_SYS_FPGA_TS_CAP1 0x14
322 #define CONFIG_SYS_FPGA_TS_CAP1_LOW 0x16
323 #define CONFIG_SYS_FPGA_TS_CAP2 0x18
324 #define CONFIG_SYS_FPGA_TS_CAP2_LOW 0x1a
325 #define CONFIG_SYS_FPGA_TS_CAP3 0x1c
326 #define CONFIG_SYS_FPGA_TS_CAP3_LOW 0x1e
329 #define CONFIG_SYS_FPGA_MODE_CF_RESET 0x0001
330 #define CONFIG_SYS_FPGA_MODE_DUART_RESET 0x0002
331 #define CONFIG_SYS_FPGA_MODE_ENABLE_OUTPUT 0x0004 /* only set on CPCI-405 Ver 3 */
332 #define CONFIG_SYS_FPGA_MODE_TS_IRQ_ENABLE 0x0100
333 #define CONFIG_SYS_FPGA_MODE_TS_IRQ_CLEAR 0x1000
334 #define CONFIG_SYS_FPGA_MODE_TS_CLEAR 0x2000
336 /* FPGA Status Reg */
337 #define CONFIG_SYS_FPGA_STATUS_DIP0 0x0001
338 #define CONFIG_SYS_FPGA_STATUS_DIP1 0x0002
339 #define CONFIG_SYS_FPGA_STATUS_DIP2 0x0004
340 #define CONFIG_SYS_FPGA_STATUS_FLASH 0x0008
341 #define CONFIG_SYS_FPGA_STATUS_TS_IRQ 0x1000
343 #define CONFIG_SYS_FPGA_SPARTAN2 1 /* using Xilinx Spartan 2 now */
344 #define CONFIG_SYS_FPGA_MAX_SIZE 32*1024 /* 32kByte is enough for XC2S15 */
346 /* FPGA program pin configuration */
347 #define CONFIG_SYS_FPGA_PRG 0x04000000 /* FPGA program pin (ppc output) */
348 #define CONFIG_SYS_FPGA_CLK 0x02000000 /* FPGA clk pin (ppc output) */
349 #define CONFIG_SYS_FPGA_DATA 0x01000000 /* FPGA data pin (ppc output) */
350 #define CONFIG_SYS_FPGA_INIT 0x00010000 /* FPGA init pin (ppc input) */
351 #define CONFIG_SYS_FPGA_DONE 0x00008000 /* FPGA done pin (ppc input) */
353 /*-----------------------------------------------------------------------
354 * Definitions for initial stack pointer and data area (in data cache)
356 #define CONFIG_SYS_INIT_DCACHE_CS 7 /* use cs # 7 for data cache memory */
358 #define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 /* use data cache */
359 #define CONFIG_SYS_INIT_RAM_SIZE 0x2000 /* Size of used area in RAM */
360 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
361 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
363 #endif /* __CONFIG_H */