2 * ueberarbeitet durch Christoph Seyfert
4 * (C) Copyright 2004-2005 DENX Software Engineering,
5 * Wolfgang Grandegger <wg@denx.de>
9 * http://www.dave-tech.it
10 * http://www.wawnet.biz
11 * mailto:info@wawnet.biz
13 * Credits: Stefan Roese, Wolfgang Denk
15 * This program is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License as
17 * published by the Free Software Foundation; either version 2 of
18 * the License, or (at your option) any later version.
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
25 * You should have received a copy of the GNU General Public License
26 * along with this program; if not, write to the Free Software
27 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
32 * board/config.h - configuration options, board specific
38 #define CONFIG_PPCHAMELEON_MODULE_BA 0 /* Basic Model */
39 #define CONFIG_PPCHAMELEON_MODULE_ME 1 /* Medium Model */
40 #define CONFIG_PPCHAMELEON_MODULE_HI 2 /* High-End Model */
41 #ifndef CONFIG_PPCHAMELEON_MODULE_MODEL
42 #define CONFIG_PPCHAMELEON_MODULE_MODEL CONFIG_PPCHAMELEON_MODULE_BA
45 /* Only one of the following two symbols must be defined (default is 25 MHz)
46 * CONFIG_PPCHAMELEON_CLK_25
47 * CONFIG_PPCHAMELEON_CLK_33
49 #if (!defined(CONFIG_PPCHAMELEON_CLK_25) && !defined(CONFIG_PPCHAMELEON_CLK_33))
50 #define CONFIG_PPCHAMELEON_CLK_25
53 #if (defined(CONFIG_PPCHAMELEON_CLK_25) && defined(CONFIG_PPCHAMELEON_CLK_33))
54 #error "* Two external frequencies (SysClk) are defined! *"
57 #undef CONFIG_PPCHAMELEON_SMI712
62 #undef __DEBUG_START_FROM_SRAM__
63 #define __DISABLE_MACHINE_EXCEPTION__
65 #ifdef __DEBUG_START_FROM_SRAM__
66 #define CFG_DUMMY_FLASH_SIZE 1024*1024*4
70 * High Level Configuration Options
74 #define CONFIG_405EP 1 /* This is a PPC405 CPU */
75 #define CONFIG_4xx 1 /* ...member of PPC4xx family */
76 #define CONFIG_PPCHAMELEONEVB 1 /* ...on a PPChameleonEVB board */
78 #define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */
79 #define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */
81 #ifdef CONFIG_PPCHAMELEON_CLK_25
82 # define CONFIG_SYS_CLK_FREQ 25000000 /* external frequency to pll */
83 #elif (defined (CONFIG_PPCHAMELEON_CLK_33))
84 #define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */
86 # error "* External frequency (SysClk) not defined! *"
89 #define CONFIG_UART1_CONSOLE 1 /* Use second UART */
90 #define CONFIG_BAUDRATE 115200
91 #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
93 #define CONFIG_VERSION_VARIABLE 1 /* add version variable */
94 #define CONFIG_IDENT_STRING "1"
96 #undef CONFIG_BOOTARGS
99 #define CONFIG_ENV_OVERWRITE /* Let the user to change the Ethernet MAC addresses */
100 #define CONFIG_ETHADDR 00:50:C2:1E:AF:FE
101 #define CONFIG_HAS_ETH1
102 #define CONFIG_ETH1ADDR 00:50:C2:1E:AF:FD
104 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
105 #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
108 #undef CONFIG_EXT_PHY
109 #define CONFIG_NET_MULTI 1
111 #define CONFIG_MII 1 /* MII PHY management */
112 #ifndef CONFIG_EXT_PHY
113 #define CONFIG_PHY_ADDR 1 /* EMAC0 PHY address */
114 #define CONFIG_PHY1_ADDR 16 /* EMAC1 PHY address */
116 #define CONFIG_PHY_ADDR 2 /* PHY address */
118 #define CONFIG_PHY_CLK_FREQ EMAC_STACR_CLK_66MHZ
120 #define CONFIG_TIMESTAMP /* Print image info with timestamp */
122 #define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
134 #define CONFIG_MAC_PARTITION
135 #define CONFIG_DOS_PARTITION
137 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
138 #include <cmd_confdefs.h>
140 #undef CONFIG_WATCHDOG /* watchdog disabled */
142 #define CONFIG_RTC_MC146818 /* DS1685 is MC146818 compatible*/
143 #define CFG_RTC_REG_BASE_ADDR 0xF0000500 /* RTC Base Address */
145 #define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
148 * Miscellaneous configurable options
150 #define CFG_LONGHELP /* undef to save memory */
151 #define CFG_PROMPT "=> " /* Monitor Command Prompt */
153 #define CFG_HUSH_PARSER /* use "hush" command parser */
154 #ifdef CFG_HUSH_PARSER
155 #define CFG_PROMPT_HUSH_PS2 "> "
158 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
159 #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
161 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
163 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
164 #define CFG_MAXARGS 16 /* max number of command args */
165 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
167 #define CFG_DEVICE_NULLDEV 1 /* include nulldev device */
169 #define CFG_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/
171 #define CFG_MEMTEST_START 0x0400000 /* memtest works on */
172 #define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
174 #undef CFG_EXT_SERIAL_CLOCK /* no external serial clock used */
175 #define CFG_IGNORE_405_UART_ERRATA_59 /* ignore ppc405gp errata #59 */
176 #define CFG_BASE_BAUD 691200
178 /* The following table includes the supported baudrates */
179 #define CFG_BAUDRATE_TABLE \
180 { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \
181 57600, 115200, 230400, 460800, 921600 }
183 #define CFG_LOAD_ADDR 0x100000 /* default load address */
184 #define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */
186 #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
188 #define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
190 /*-----------------------------------------------------------------------
192 *-----------------------------------------------------------------------
194 #define CFG_NAND0_BASE 0xFF400000
195 #define CFG_NAND1_BASE 0xFF000000
196 #define CFG_NAND_BASE_LIST { CFG_NAND0_BASE }
197 #define NAND_BIG_DELAY_US 25
199 /* For CATcenter there is only NAND on the module */
200 #define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
201 #define SECTORSIZE 512
204 #define ADDR_COLUMN 1
206 #define ADDR_COLUMN_PAGE 3
208 #define NAND_ChipID_UNKNOWN 0x00
209 #define NAND_MAX_FLOORS 1
210 #define NAND_MAX_CHIPS 1
212 #define CFG_NAND0_CE (0x80000000 >> 1) /* our CE is GPIO1 */
213 #define CFG_NAND0_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */
214 #define CFG_NAND0_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */
215 #define CFG_NAND0_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */
217 #define CFG_NAND1_CE (0x80000000 >> 14) /* our CE is GPIO14 */
218 #define CFG_NAND1_CLE (0x80000000 >> 15) /* our CLE is GPIO15 */
219 #define CFG_NAND1_ALE (0x80000000 >> 16) /* our ALE is GPIO16 */
220 #define CFG_NAND1_RDY (0x80000000 >> 31) /* our RDY is GPIO31 */
223 #define MACRO_NAND_DISABLE_CE(nandptr) do \
225 switch((unsigned long)nandptr) \
227 case CFG_NAND0_BASE: \
228 out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND0_CE); \
230 case CFG_NAND1_BASE: \
231 out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND1_CE); \
236 #define MACRO_NAND_ENABLE_CE(nandptr) do \
238 switch((unsigned long)nandptr) \
240 case CFG_NAND0_BASE: \
241 out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND0_CE); \
243 case CFG_NAND1_BASE: \
244 out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND1_CE); \
249 #define MACRO_NAND_CTL_CLRALE(nandptr) do \
251 switch((unsigned long)nandptr) \
253 case CFG_NAND0_BASE: \
254 out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND0_ALE); \
256 case CFG_NAND1_BASE: \
257 out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND1_ALE); \
262 #define MACRO_NAND_CTL_SETALE(nandptr) do \
264 switch((unsigned long)nandptr) \
266 case CFG_NAND0_BASE: \
267 out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND0_ALE); \
269 case CFG_NAND1_BASE: \
270 out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND1_ALE); \
275 #define MACRO_NAND_CTL_CLRCLE(nandptr) do \
277 switch((unsigned long)nandptr) \
279 case CFG_NAND0_BASE: \
280 out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND0_CLE); \
282 case CFG_NAND1_BASE: \
283 out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND1_CLE); \
288 #define MACRO_NAND_CTL_SETCLE(nandptr) do { \
289 switch((unsigned long)nandptr) { \
290 case CFG_NAND0_BASE: \
291 out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND0_CLE); \
293 case CFG_NAND1_BASE: \
294 out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND1_CLE); \
300 /* constant delay (see also tR in the datasheet) */
301 #define NAND_WAIT_READY(nand) do { \
305 /* use the R/B pin */
309 #define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0)
310 #define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0)
311 #define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)d; } while(0)
312 #define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)adr))
314 /*-----------------------------------------------------------------------
316 *-----------------------------------------------------------------------
318 #if 0 /* No PCI on CATcenter */
319 #define PCI_HOST_ADAPTER 0 /* configure as pci adapter */
320 #define PCI_HOST_FORCE 1 /* configure as pci host */
321 #define PCI_HOST_AUTO 2 /* detected via arbiter enable */
323 #define CONFIG_PCI /* include pci support */
324 #define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */
325 #undef CONFIG_PCI_PNP /* do pci plug-and-play */
326 /* resource configuration */
328 #define CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */
330 #define CFG_PCI_SUBSYS_VENDORID 0x1014 /* PCI Vendor ID: IBM */
331 #define CFG_PCI_SUBSYS_DEVICEID 0x0000 /* PCI Device ID: --- */
332 #define CFG_PCI_CLASSCODE 0x0b20 /* PCI Class Code: Processor/PPC*/
334 #define CFG_PCI_PTM1LA 0x00000000 /* point to sdram */
335 #define CFG_PCI_PTM1MS 0xfc000001 /* 64MB, enable hard-wired to 1 */
336 #define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
337 #define CFG_PCI_PTM2LA 0xffc00000 /* point to flash */
338 #define CFG_PCI_PTM2MS 0xffc00001 /* 4MB, enable */
339 #define CFG_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */
342 /*-----------------------------------------------------------------------
343 * Start addresses for the final memory configuration
344 * (Set up by the startup code)
345 * Please note that CFG_SDRAM_BASE _must_ start at 0
347 #define CFG_SDRAM_BASE 0x00000000
348 #define CFG_FLASH_BASE 0xFFFC0000
349 #define CFG_MONITOR_BASE CFG_FLASH_BASE
350 #define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */
351 #define CFG_MALLOC_LEN (256 * 1024) /* Reserve 256 kB for malloc() */
354 * For booting Linux, the board info and command line data
355 * have to be in the first 8 MB of memory, since this is
356 * the maximum mapped by the Linux kernel during initialization.
358 #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
359 /*-----------------------------------------------------------------------
362 #define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
363 #define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
365 #define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
366 #define CFG_FLASH_WRITE_TOUT 1000 /* Timeout for Flash Write (in ms) */
368 #define CFG_FLASH_WORD_SIZE unsigned short /* flash word size (width) */
369 #define CFG_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */
370 #define CFG_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */
372 * The following defines are added for buggy IOP480 byte interface.
373 * All other boards should use the standard values (CPCI405 etc.)
375 #define CFG_FLASH_READ0 0x0000 /* 0 is standard */
376 #define CFG_FLASH_READ1 0x0001 /* 1 is standard */
377 #define CFG_FLASH_READ2 0x0002 /* 2 is standard */
379 #define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
381 /*-----------------------------------------------------------------------
382 * Environment Variable setup
384 #define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
385 #define CFG_ENV_ADDR 0xFFFF8000 /* environment starts at the first small sector */
386 #define CFG_ENV_SECT_SIZE 0x2000 /* 8196 bytes may be used for env vars*/
387 #define CFG_ENV_ADDR_REDUND 0xFFFFA000
388 #define CFG_ENV_SIZE_REDUND 0x2000
390 #define CFG_NVRAM_BASE_ADDR 0xF0000500 /* NVRAM base address */
391 #define CFG_NVRAM_SIZE 242 /* NVRAM size */
393 /*-----------------------------------------------------------------------
394 * I2C EEPROM (CAT24WC16) for environment
396 #define CONFIG_HARD_I2C /* I2c with hardware support */
397 #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
398 #define CFG_I2C_SLAVE 0x7F
400 #define CFG_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */
401 #define CFG_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
402 /* mask of address bits that overflow into the "EEPROM chip address" */
403 /*#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x07*/
404 #define CFG_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */
405 /* 16 byte page write mode using*/
406 /* last 4 bits of the address */
407 #define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
408 #define CFG_EEPROM_PAGE_WRITE_ENABLE
410 /*-----------------------------------------------------------------------
411 * Cache Configuration
413 #define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */
414 /* have only 8kB, 16kB is save here */
415 #define CFG_CACHELINE_SIZE 32 /* ... */
416 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
417 #define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
421 * Init Memory Controller:
423 * BR0/1 and OR0/1 (FLASH)
426 #define FLASH_BASE0_PRELIM 0xFFC00000 /* FLASH bank #0 */
428 /*-----------------------------------------------------------------------
429 * External Bus Controller (EBC) Setup
432 /* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization */
433 #define CFG_EBC_PB0AP 0x92015480
434 #define CFG_EBC_PB0CR 0xFFC5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
436 /* Memory Bank 1 (External SRAM) initialization */
437 /* Since this must replace NOR Flash, we use the same settings for CS0 */
438 #define CFG_EBC_PB1AP 0x92015480
439 #define CFG_EBC_PB1CR 0xFF85A000 /* BAS=0xFF8,BS=4MB,BU=R/W,BW=8bit */
441 /* Memory Bank 2 (Flash Bank 1, NAND-FLASH) initialization */
442 #define CFG_EBC_PB2AP 0x92015480
443 #define CFG_EBC_PB2CR 0xFF458000 /* BAS=0xFF4,BS=4MB,BU=R/W,BW=8bit */
445 /* Memory Bank 3 (Flash Bank 2, NAND-FLASH) initialization */
446 #define CFG_EBC_PB3AP 0x92015480
447 #define CFG_EBC_PB3CR 0xFF058000 /* BAS=0xFF0,BS=4MB,BU=R/W,BW=8bit */
449 #ifdef CONFIG_PPCHAMELEON_SMI712
451 * Video console (graphic: SMI LynxEM)
454 #define CONFIG_CFB_CONSOLE
455 #define CONFIG_VIDEO_SMI_LYNXEM
456 #define CONFIG_VIDEO_LOGO
457 /*#define CONFIG_VIDEO_BMP_LOGO*/
458 #define CONFIG_CONSOLE_EXTRA_INFO
459 #define CONFIG_VGA_AS_SINGLE_DEVICE
460 /* This is the base address (on 405EP-side) used to generate I/O accesses on PCI bus */
461 #define CFG_ISA_IO 0xE8000000
462 /* see also drivers/videomodes.c */
463 #define CFG_DEFAULT_VIDEO_MODE 0x303
466 /*-----------------------------------------------------------------------
469 /* FPGA internal regs */
470 #define CFG_FPGA_MODE 0x00
471 #define CFG_FPGA_STATUS 0x02
472 #define CFG_FPGA_TS 0x04
473 #define CFG_FPGA_TS_LOW 0x06
474 #define CFG_FPGA_TS_CAP0 0x10
475 #define CFG_FPGA_TS_CAP0_LOW 0x12
476 #define CFG_FPGA_TS_CAP1 0x14
477 #define CFG_FPGA_TS_CAP1_LOW 0x16
478 #define CFG_FPGA_TS_CAP2 0x18
479 #define CFG_FPGA_TS_CAP2_LOW 0x1a
480 #define CFG_FPGA_TS_CAP3 0x1c
481 #define CFG_FPGA_TS_CAP3_LOW 0x1e
484 #define CFG_FPGA_MODE_CF_RESET 0x0001
485 #define CFG_FPGA_MODE_TS_IRQ_ENABLE 0x0100
486 #define CFG_FPGA_MODE_TS_IRQ_CLEAR 0x1000
487 #define CFG_FPGA_MODE_TS_CLEAR 0x2000
489 /* FPGA Status Reg */
490 #define CFG_FPGA_STATUS_DIP0 0x0001
491 #define CFG_FPGA_STATUS_DIP1 0x0002
492 #define CFG_FPGA_STATUS_DIP2 0x0004
493 #define CFG_FPGA_STATUS_FLASH 0x0008
494 #define CFG_FPGA_STATUS_TS_IRQ 0x1000
496 #define CFG_FPGA_SPARTAN2 1 /* using Xilinx Spartan 2 now */
497 #define CFG_FPGA_MAX_SIZE 128*1024 /* 128kByte is enough for XC2S50E*/
499 /* FPGA program pin configuration */
500 #define CFG_FPGA_PRG 0x04000000 /* FPGA program pin (ppc output) */
501 #define CFG_FPGA_CLK 0x02000000 /* FPGA clk pin (ppc output) */
502 #define CFG_FPGA_DATA 0x01000000 /* FPGA data pin (ppc output) */
503 #define CFG_FPGA_INIT 0x00010000 /* FPGA init pin (ppc input) */
504 #define CFG_FPGA_DONE 0x00008000 /* FPGA done pin (ppc input) */
506 /*-----------------------------------------------------------------------
507 * Definitions for initial stack pointer and data area (in data cache)
509 /* use on chip memory ( OCM ) for temperary stack until sdram is tested */
510 #define CFG_TEMP_STACK_OCM 1
512 /* On Chip Memory location */
513 #define CFG_OCM_DATA_ADDR 0xF8000000
514 #define CFG_OCM_DATA_SIZE 0x1000
515 #define CFG_INIT_RAM_ADDR CFG_OCM_DATA_ADDR /* inside of SDRAM */
516 #define CFG_INIT_RAM_END CFG_OCM_DATA_SIZE /* End of used area in RAM */
518 #define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
519 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
520 #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
522 /*-----------------------------------------------------------------------
523 * Definitions for GPIO setup (PPC405EP specific)
525 * GPIO0[0] - External Bus Controller BLAST output
526 * GPIO0[1-9] - Instruction trace outputs -> GPIO
527 * GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs
528 * GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs -> GPIO
529 * GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs
530 * GPIO0[24-27] - UART0 control signal inputs/outputs
531 * GPIO0[28-29] - UART1 data signal input/output
532 * GPIO0[30] - EMAC0 input
533 * GPIO0[31] - EMAC1 reject packet as output
535 #define CFG_GPIO0_OSRH 0x40000550
536 #define CFG_GPIO0_OSRL 0x00000110
537 #define CFG_GPIO0_ISR1H 0x00000000
538 /*#define CFG_GPIO0_ISR1L 0x15555445*/
539 #define CFG_GPIO0_ISR1L 0x15555444
540 #define CFG_GPIO0_TSRH 0x00000000
541 #define CFG_GPIO0_TSRL 0x00000000
542 #define CFG_GPIO0_TCR 0xF7FF8014
545 * Internal Definitions
549 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
550 #define BOOTFLAG_WARM 0x02 /* Software reboot */
553 #define CONFIG_NO_SERIAL_EEPROM
555 /*--------------------------------------------------------------------*/
557 #ifdef CONFIG_NO_SERIAL_EEPROM
560 !-----------------------------------------------------------------------
561 ! Defines for entry options.
562 ! Note: Because the 405EP SDRAM controller does not support ECC, ECC DIMMs that
563 ! are plugged in the board will be utilized as non-ECC DIMMs.
564 !-----------------------------------------------------------------------
566 #undef AUTO_MEMORY_CONFIG
567 #define DIMM_READ_ADDR 0xAB
568 #define DIMM_WRITE_ADDR 0xAA
570 #define CPC0_PLLMR0 (CNTRL_DCR_BASE+0x0) /* PLL mode 0 register */
571 #define CPC0_BOOT (CNTRL_DCR_BASE+0x1) /* Chip Clock Status register */
572 #define CPC0_CR1 (CNTRL_DCR_BASE+0x2) /* Chip Control 1 register */
573 #define CPC0_EPRCSR (CNTRL_DCR_BASE+0x3) /* EMAC PHY Rcv Clk Src register */
574 #define CPC0_PLLMR1 (CNTRL_DCR_BASE+0x4) /* PLL mode 1 register */
575 #define CPC0_UCR (CNTRL_DCR_BASE+0x5) /* UART Control register */
576 #define CPC0_SRR (CNTRL_DCR_BASE+0x6) /* Soft Reset register */
577 #define CPC0_JTAGID (CNTRL_DCR_BASE+0x7) /* JTAG ID register */
578 #define CPC0_SPARE (CNTRL_DCR_BASE+0x8) /* Spare DCR */
579 #define CPC0_PCI (CNTRL_DCR_BASE+0x9) /* PCI Control register */
581 /* Defines for CPC0_PLLMR1 Register fields */
582 #define PLL_ACTIVE 0x80000000
583 #define CPC0_PLLMR1_SSCS 0x80000000
584 #define PLL_RESET 0x40000000
585 #define CPC0_PLLMR1_PLLR 0x40000000
586 /* Feedback multiplier */
587 #define PLL_FBKDIV 0x00F00000
588 #define CPC0_PLLMR1_FBDV 0x00F00000
589 #define PLL_FBKDIV_16 0x00000000
590 #define PLL_FBKDIV_1 0x00100000
591 #define PLL_FBKDIV_2 0x00200000
592 #define PLL_FBKDIV_3 0x00300000
593 #define PLL_FBKDIV_4 0x00400000
594 #define PLL_FBKDIV_5 0x00500000
595 #define PLL_FBKDIV_6 0x00600000
596 #define PLL_FBKDIV_7 0x00700000
597 #define PLL_FBKDIV_8 0x00800000
598 #define PLL_FBKDIV_9 0x00900000
599 #define PLL_FBKDIV_10 0x00A00000
600 #define PLL_FBKDIV_11 0x00B00000
601 #define PLL_FBKDIV_12 0x00C00000
602 #define PLL_FBKDIV_13 0x00D00000
603 #define PLL_FBKDIV_14 0x00E00000
604 #define PLL_FBKDIV_15 0x00F00000
605 /* Forward A divisor */
606 #define PLL_FWDDIVA 0x00070000
607 #define CPC0_PLLMR1_FWDVA 0x00070000
608 #define PLL_FWDDIVA_8 0x00000000
609 #define PLL_FWDDIVA_7 0x00010000
610 #define PLL_FWDDIVA_6 0x00020000
611 #define PLL_FWDDIVA_5 0x00030000
612 #define PLL_FWDDIVA_4 0x00040000
613 #define PLL_FWDDIVA_3 0x00050000
614 #define PLL_FWDDIVA_2 0x00060000
615 #define PLL_FWDDIVA_1 0x00070000
616 /* Forward B divisor */
617 #define PLL_FWDDIVB 0x00007000
618 #define CPC0_PLLMR1_FWDVB 0x00007000
619 #define PLL_FWDDIVB_8 0x00000000
620 #define PLL_FWDDIVB_7 0x00001000
621 #define PLL_FWDDIVB_6 0x00002000
622 #define PLL_FWDDIVB_5 0x00003000
623 #define PLL_FWDDIVB_4 0x00004000
624 #define PLL_FWDDIVB_3 0x00005000
625 #define PLL_FWDDIVB_2 0x00006000
626 #define PLL_FWDDIVB_1 0x00007000
628 #define PLL_TUNE_MASK 0x000003FF
629 #define PLL_TUNE_2_M_3 0x00000133 /* 2 <= M <= 3 */
630 #define PLL_TUNE_4_M_6 0x00000134 /* 3 < M <= 6 */
631 #define PLL_TUNE_7_M_10 0x00000138 /* 6 < M <= 10 */
632 #define PLL_TUNE_11_M_14 0x0000013C /* 10 < M <= 14 */
633 #define PLL_TUNE_15_M_40 0x0000023E /* 14 < M <= 40 */
634 #define PLL_TUNE_VCO_LOW 0x00000000 /* 500MHz <= VCO <= 800MHz */
635 #define PLL_TUNE_VCO_HI 0x00000080 /* 800MHz < VCO <= 1000MHz */
637 /* Defines for CPC0_PLLMR0 Register fields */
639 #define PLL_CPUDIV 0x00300000
640 #define CPC0_PLLMR0_CCDV 0x00300000
641 #define PLL_CPUDIV_1 0x00000000
642 #define PLL_CPUDIV_2 0x00100000
643 #define PLL_CPUDIV_3 0x00200000
644 #define PLL_CPUDIV_4 0x00300000
646 #define PLL_PLBDIV 0x00030000
647 #define CPC0_PLLMR0_CBDV 0x00030000
648 #define PLL_PLBDIV_1 0x00000000
649 #define PLL_PLBDIV_2 0x00010000
650 #define PLL_PLBDIV_3 0x00020000
651 #define PLL_PLBDIV_4 0x00030000
653 #define PLL_OPBDIV 0x00003000
654 #define CPC0_PLLMR0_OPDV 0x00003000
655 #define PLL_OPBDIV_1 0x00000000
656 #define PLL_OPBDIV_2 0x00001000
657 #define PLL_OPBDIV_3 0x00002000
658 #define PLL_OPBDIV_4 0x00003000
660 #define PLL_EXTBUSDIV 0x00000300
661 #define CPC0_PLLMR0_EPDV 0x00000300
662 #define PLL_EXTBUSDIV_2 0x00000000
663 #define PLL_EXTBUSDIV_3 0x00000100
664 #define PLL_EXTBUSDIV_4 0x00000200
665 #define PLL_EXTBUSDIV_5 0x00000300
667 #define PLL_MALDIV 0x00000030
668 #define CPC0_PLLMR0_MPDV 0x00000030
669 #define PLL_MALDIV_1 0x00000000
670 #define PLL_MALDIV_2 0x00000010
671 #define PLL_MALDIV_3 0x00000020
672 #define PLL_MALDIV_4 0x00000030
674 #define PLL_PCIDIV 0x00000003
675 #define CPC0_PLLMR0_PPFD 0x00000003
676 #define PLL_PCIDIV_1 0x00000000
677 #define PLL_PCIDIV_2 0x00000001
678 #define PLL_PCIDIV_3 0x00000002
679 #define PLL_PCIDIV_4 0x00000003
681 #ifdef CONFIG_PPCHAMELEON_CLK_25
682 /* CPU - PLB/SDRAM - EBC - OPB - PCI (assuming a 25.0 MHz input clock to the 405EP) */
683 #define PPCHAMELEON_PLLMR0_133_133_33_66_33 (PLL_CPUDIV_1 | PLL_PLBDIV_1 | \
684 PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 | \
685 PLL_MALDIV_1 | PLL_PCIDIV_4)
686 #define PPCHAMELEON_PLLMR1_133_133_33_66_33 (PLL_FBKDIV_8 | \
687 PLL_FWDDIVA_6 | PLL_FWDDIVB_4 | \
688 PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
690 #define PPCHAMELEON_PLLMR0_200_100_50_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \
691 PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 | \
692 PLL_MALDIV_1 | PLL_PCIDIV_4)
693 #define PPCHAMELEON_PLLMR1_200_100_50_33 (PLL_FBKDIV_8 | \
694 PLL_FWDDIVA_4 | PLL_FWDDIVB_4 | \
695 PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
697 #define PPCHAMELEON_PLLMR0_266_133_33_66_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \
698 PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 | \
699 PLL_MALDIV_1 | PLL_PCIDIV_4)
700 #define PPCHAMELEON_PLLMR1_266_133_33_66_33 (PLL_FBKDIV_8 | \
701 PLL_FWDDIVA_3 | PLL_FWDDIVB_4 | \
702 PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
704 #define PPCHAMELEON_PLLMR0_333_111_37_55_55 (PLL_CPUDIV_1 | PLL_PLBDIV_3 | \
705 PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 | \
706 PLL_MALDIV_1 | PLL_PCIDIV_2)
707 #define PPCHAMELEON_PLLMR1_333_111_37_55_55 (PLL_FBKDIV_10 | \
708 PLL_FWDDIVA_3 | PLL_FWDDIVB_4 | \
709 PLL_TUNE_15_M_40 | PLL_TUNE_VCO_HI)
711 #elif (defined (CONFIG_PPCHAMELEON_CLK_33))
713 /* CPU - PLB/SDRAM - EBC - OPB - PCI (assuming a 33.3MHz input clock to the 405EP) */
714 #define PPCHAMELEON_PLLMR0_133_133_33_66_33 (PLL_CPUDIV_1 | PLL_PLBDIV_1 | \
715 PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 | \
716 PLL_MALDIV_1 | PLL_PCIDIV_4)
717 #define PPCHAMELEON_PLLMR1_133_133_33_66_33 (PLL_FBKDIV_4 | \
718 PLL_FWDDIVA_6 | PLL_FWDDIVB_6 | \
719 PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
721 #define PPCHAMELEON_PLLMR0_200_100_50_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \
722 PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 | \
723 PLL_MALDIV_1 | PLL_PCIDIV_4)
724 #define PPCHAMELEON_PLLMR1_200_100_50_33 (PLL_FBKDIV_6 | \
725 PLL_FWDDIVA_4 | PLL_FWDDIVB_4 | \
726 PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
728 #define PPCHAMELEON_PLLMR0_266_133_33_66_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \
729 PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 | \
730 PLL_MALDIV_1 | PLL_PCIDIV_4)
731 #define PPCHAMELEON_PLLMR1_266_133_33_66_33 (PLL_FBKDIV_8 | \
732 PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \
733 PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
735 #define PPCHAMELEON_PLLMR0_333_111_37_55_55 (PLL_CPUDIV_1 | PLL_PLBDIV_3 | \
736 PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 | \
737 PLL_MALDIV_1 | PLL_PCIDIV_2)
738 #define PPCHAMELEON_PLLMR1_333_111_37_55_55 (PLL_FBKDIV_10 | \
739 PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \
740 PLL_TUNE_15_M_40 | PLL_TUNE_VCO_HI)
743 #error "* External frequency (SysClk) not defined! *"
746 #if (CONFIG_PPCHAMELEON_MODULE_MODEL == CONFIG_PPCHAMELEON_MODULE_HI)
748 #define PLLMR0_DEFAULT PPCHAMELEON_PLLMR0_333_111_37_55_55
749 #define PLLMR1_DEFAULT PPCHAMELEON_PLLMR1_333_111_37_55_55
750 #define CFG_OPB_FREQ 55555555
752 #elif (CONFIG_PPCHAMELEON_MODULE_MODEL == CONFIG_PPCHAMELEON_MODULE_ME)
753 #define PLLMR0_DEFAULT PPCHAMELEON_PLLMR0_266_133_33_66_33
754 #define PLLMR1_DEFAULT PPCHAMELEON_PLLMR1_266_133_33_66_33
755 #define CFG_OPB_FREQ 66666666
757 /* Model BA (default) */
758 #define PLLMR0_DEFAULT PPCHAMELEON_PLLMR0_133_133_33_66_33
759 #define PLLMR1_DEFAULT PPCHAMELEON_PLLMR1_133_133_33_66_33
760 #define CFG_OPB_FREQ 66666666
763 #endif /* CONFIG_NO_SERIAL_EEPROM */
765 #define CONFIG_JFFS2_NAND 1 /* jffs2 on nand support */
766 #define NAND_CACHE_PAGES 16 /* size of nand cache in 512 bytes pages */
772 /* No command line, one static partition */
773 #undef CONFIG_JFFS2_CMDLINE
774 #define CONFIG_JFFS2_DEV "nand"
775 #define CONFIG_JFFS2_PART_SIZE 0x00200000
776 #define CONFIG_JFFS2_PART_OFFSET 0x00000000
778 /* mtdparts command line support
780 * Note: fake mtd_id used, no linux mtd map file
783 #define CONFIG_JFFS2_CMDLINE
784 #define MTDIDS_DEFAULT "nand0=catcenter"
785 #define MTDPARTS_DEFAULT "mtdparts=catcenter:2m(nand)"
788 #endif /* __CONFIG_H */