Merge branch 'master' of git://git.denx.de/u-boot-arm
[platform/kernel/u-boot.git] / include / configs / CATcenter.h
1 /*
2  * ueberarbeitet durch Christoph Seyfert
3  *
4  * (C) Copyright 2004-2005 DENX Software Engineering,
5  *     Wolfgang Grandegger <wg@denx.de>
6  * (C) Copyright 2003
7  *     DAVE Srl
8  *
9  * http://www.dave-tech.it
10  * http://www.wawnet.biz
11  * mailto:info@wawnet.biz
12  *
13  * Credits: Stefan Roese, Wolfgang Denk
14  *
15  * SPDX-License-Identifier:     GPL-2.0+ 
16  */
17
18 /*
19  * board/config.h - configuration options, board specific
20  */
21
22 #ifndef __CONFIG_H
23 #define __CONFIG_H
24
25 #define CONFIG_PPCHAMELEON_MODULE_BA    0       /* Basic    Model */
26 #define CONFIG_PPCHAMELEON_MODULE_ME    1       /* Medium   Model */
27 #define CONFIG_PPCHAMELEON_MODULE_HI    2       /* High-End Model */
28 #ifndef CONFIG_PPCHAMELEON_MODULE_MODEL
29 #define CONFIG_PPCHAMELEON_MODULE_MODEL CONFIG_PPCHAMELEON_MODULE_BA
30 #endif
31
32 /* Only one of the following two symbols must be defined (default is 25 MHz)
33  * CONFIG_PPCHAMELEON_CLK_25
34  * CONFIG_PPCHAMELEON_CLK_33
35  */
36 #if (!defined(CONFIG_PPCHAMELEON_CLK_25) && !defined(CONFIG_PPCHAMELEON_CLK_33))
37 #define CONFIG_PPCHAMELEON_CLK_25
38 #endif
39
40 #if (defined(CONFIG_PPCHAMELEON_CLK_25) && defined(CONFIG_PPCHAMELEON_CLK_33))
41 #error "* Two external frequencies (SysClk) are defined! *"
42 #endif
43
44 #undef CONFIG_PPCHAMELEON_SMI712
45
46 /*
47  * Debug stuff
48  */
49 #undef  __DEBUG_START_FROM_SRAM__
50 #define __DISABLE_MACHINE_EXCEPTION__
51
52 #ifdef __DEBUG_START_FROM_SRAM__
53 #define CONFIG_SYS_DUMMY_FLASH_SIZE             1024*1024*4
54 #endif
55
56 /*
57  * High Level Configuration Options
58  * (easy to change)
59  */
60
61 #define CONFIG_405EP            1       /* This is a PPC405 CPU         */
62 #define CONFIG_4xx              1       /* ...member of PPC4xx family   */
63 #define CONFIG_PPCHAMELEONEVB   1       /* ...on a PPChameleonEVB board */
64
65 #define CONFIG_SYS_TEXT_BASE    0xFFFB0000      /* Reserve 320 kB for Monitor */
66 #define CONFIG_SYS_LDSCRIPT     "board/dave/PPChameleonEVB/u-boot.lds"
67
68 #define CONFIG_BOARD_EARLY_INIT_F 1     /* call board_early_init_f()    */
69 #define CONFIG_MISC_INIT_R      1       /* call misc_init_r()           */
70
71 #ifdef CONFIG_PPCHAMELEON_CLK_25
72 # define CONFIG_SYS_CLK_FREQ    25000000 /* external frequency to pll   */
73 #elif (defined (CONFIG_PPCHAMELEON_CLK_33))
74 #define CONFIG_SYS_CLK_FREQ     33333333 /* external frequency to pll   */
75 #else
76 # error "* External frequency (SysClk) not defined! *"
77 #endif
78
79 #define CONFIG_CONS_INDEX       2       /* Use UART1                    */
80 #define CONFIG_SYS_NS16550
81 #define CONFIG_SYS_NS16550_SERIAL
82 #define CONFIG_SYS_NS16550_REG_SIZE     1
83 #define CONFIG_SYS_NS16550_CLK          get_serial_clock()
84 #define CONFIG_BAUDRATE         115200
85 #define CONFIG_BOOTDELAY        5       /* autoboot after 5 seconds     */
86
87 #define CONFIG_VERSION_VARIABLE 1       /* add version variable         */
88 #define CONFIG_IDENT_STRING     "1"
89
90 #undef  CONFIG_BOOTARGS
91
92 /* Ethernet stuff */
93 #define CONFIG_ENV_OVERWRITE /* Let the user to change the Ethernet MAC addresses */
94 #define CONFIG_ETHADDR  00:50:C2:1E:AF:FE
95 #define CONFIG_HAS_ETH1
96 #define CONFIG_ETH1ADDR 00:50:C2:1E:AF:FD
97
98 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download  */
99 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change        */
100
101
102 #define CONFIG_PPC4xx_EMAC
103 #undef CONFIG_EXT_PHY
104
105 #define CONFIG_MII              1       /* MII PHY management           */
106 #ifndef  CONFIG_EXT_PHY
107 #define CONFIG_PHY_ADDR         1       /* EMAC0 PHY address            */
108 #define CONFIG_PHY1_ADDR        16      /* EMAC1 PHY address            */
109 #else
110 #define CONFIG_PHY_ADDR         2       /* PHY address                  */
111 #endif
112 #define CONFIG_PHY_CLK_FREQ     EMAC_STACR_CLK_66MHZ
113
114 #define CONFIG_TIMESTAMP                /* Print image info with timestamp */
115
116
117 /*
118  * BOOTP options
119  */
120 #define CONFIG_BOOTP_BOOTFILESIZE
121 #define CONFIG_BOOTP_BOOTPATH
122 #define CONFIG_BOOTP_GATEWAY
123 #define CONFIG_BOOTP_HOSTNAME
124
125
126 /*
127  * Command line configuration.
128  */
129 #include <config_cmd_default.h>
130
131 #define CONFIG_CMD_DHCP
132 #define CONFIG_CMD_ELF
133 #define CONFIG_CMD_EEPROM
134 #define CONFIG_CMD_I2C
135 #define CONFIG_CMD_IRQ
136 #define CONFIG_CMD_JFFS2
137 #define CONFIG_CMD_MII
138 #define CONFIG_CMD_NAND
139 #define CONFIG_CMD_NFS
140 #define CONFIG_CMD_SNTP
141
142
143 #define CONFIG_MAC_PARTITION
144 #define CONFIG_DOS_PARTITION
145
146 #undef  CONFIG_WATCHDOG                 /* watchdog disabled            */
147
148 #define CONFIG_RTC_MC146818             /* DS1685 is MC146818 compatible*/
149 #define CONFIG_SYS_RTC_REG_BASE_ADDR     0xF0000500 /* RTC Base Address         */
150
151 #define CONFIG_SDRAM_BANK0      1       /* init onboard SDRAM bank 0    */
152
153 /*
154  * Miscellaneous configurable options
155  */
156 #define CONFIG_SYS_LONGHELP                     /* undef to save memory         */
157 #define CONFIG_SYS_PROMPT               "=> "   /* Monitor Command Prompt       */
158
159 #define CONFIG_SYS_HUSH_PARSER                  /* use "hush" command parser    */
160
161 #if defined(CONFIG_CMD_KGDB)
162 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size      */
163 #else
164 #define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size      */
165 #endif
166 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
167 #define CONFIG_SYS_MAXARGS      16              /* max number of command args   */
168 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size    */
169
170 #define CONFIG_SYS_DEVICE_NULLDEV       1       /* include nulldev device       */
171
172 #define CONFIG_SYS_CONSOLE_INFO_QUIET   1       /* don't print console @ startup*/
173
174 #define CONFIG_SYS_MEMTEST_START        0x0400000       /* memtest works on     */
175 #define CONFIG_SYS_MEMTEST_END          0x0C00000       /* 4 ... 12 MB in DRAM  */
176
177 #undef  CONFIG_SYS_EXT_SERIAL_CLOCK             /* no external serial clock used */
178 #define CONFIG_SYS_BASE_BAUD            691200
179
180 /* The following table includes the supported baudrates */
181 #define CONFIG_SYS_BAUDRATE_TABLE       \
182         { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400,     \
183          57600, 115200, 230400, 460800, 921600 }
184
185 #define CONFIG_SYS_LOAD_ADDR    0x100000        /* default load address */
186 #define CONFIG_SYS_EXTBDINFO    1               /* To use extended board_into (bd_t) */
187
188 #define CONFIG_SYS_HZ           1000            /* decrementer freq: 1 ms ticks */
189
190 #define CONFIG_ZERO_BOOTDELAY_CHECK     /* check for keypress on bootdelay==0 */
191
192 /*-----------------------------------------------------------------------
193  * NAND-FLASH stuff
194  *-----------------------------------------------------------------------
195  */
196 #define CONFIG_SYS_NAND0_BASE 0xFF400000
197 #define CONFIG_SYS_NAND1_BASE 0xFF000000
198 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND0_BASE }
199 #define NAND_BIG_DELAY_US       25
200
201 /* For CATcenter there is only NAND on the module */
202 #define CONFIG_SYS_MAX_NAND_DEVICE      1       /* Max number of NAND devices           */
203 #define NAND_NO_RB
204
205 #define CONFIG_SYS_NAND0_CE  (0x80000000 >> 1)   /* our CE is GPIO1 */
206 #define CONFIG_SYS_NAND0_CLE (0x80000000 >> 2)   /* our CLE is GPIO2 */
207 #define CONFIG_SYS_NAND0_ALE (0x80000000 >> 3)   /* our ALE is GPIO3 */
208 #define CONFIG_SYS_NAND0_RDY (0x80000000 >> 4)   /* our RDY is GPIO4 */
209
210 #define CONFIG_SYS_NAND1_CE  (0x80000000 >> 14)  /* our CE is GPIO14 */
211 #define CONFIG_SYS_NAND1_CLE (0x80000000 >> 15)  /* our CLE is GPIO15 */
212 #define CONFIG_SYS_NAND1_ALE (0x80000000 >> 16)  /* our ALE is GPIO16 */
213 #define CONFIG_SYS_NAND1_RDY (0x80000000 >> 31)  /* our RDY is GPIO31 */
214
215
216 #define MACRO_NAND_DISABLE_CE(nandptr) do \
217 { \
218         switch((unsigned long)nandptr) \
219         { \
220             case CONFIG_SYS_NAND0_BASE: \
221                 out32(GPIO0_OR, in32(GPIO0_OR) | CONFIG_SYS_NAND0_CE); \
222                 break; \
223             case CONFIG_SYS_NAND1_BASE: \
224                 out32(GPIO0_OR, in32(GPIO0_OR) | CONFIG_SYS_NAND1_CE); \
225                 break; \
226         } \
227 } while(0)
228
229 #define MACRO_NAND_ENABLE_CE(nandptr) do \
230 { \
231         switch((unsigned long)nandptr) \
232         { \
233             case CONFIG_SYS_NAND0_BASE: \
234                 out32(GPIO0_OR, in32(GPIO0_OR) & ~CONFIG_SYS_NAND0_CE); \
235                 break; \
236             case CONFIG_SYS_NAND1_BASE: \
237                 out32(GPIO0_OR, in32(GPIO0_OR) & ~CONFIG_SYS_NAND1_CE); \
238                 break; \
239         } \
240 } while(0)
241
242 #define MACRO_NAND_CTL_CLRALE(nandptr) do \
243 { \
244         switch((unsigned long)nandptr) \
245         { \
246             case CONFIG_SYS_NAND0_BASE: \
247                 out32(GPIO0_OR, in32(GPIO0_OR) & ~CONFIG_SYS_NAND0_ALE); \
248                 break; \
249             case CONFIG_SYS_NAND1_BASE: \
250                 out32(GPIO0_OR, in32(GPIO0_OR) & ~CONFIG_SYS_NAND1_ALE); \
251                 break; \
252         } \
253 } while(0)
254
255 #define MACRO_NAND_CTL_SETALE(nandptr) do \
256 { \
257         switch((unsigned long)nandptr) \
258         { \
259             case CONFIG_SYS_NAND0_BASE: \
260                 out32(GPIO0_OR, in32(GPIO0_OR) | CONFIG_SYS_NAND0_ALE); \
261                 break; \
262             case CONFIG_SYS_NAND1_BASE: \
263                 out32(GPIO0_OR, in32(GPIO0_OR) | CONFIG_SYS_NAND1_ALE); \
264                 break; \
265         } \
266 } while(0)
267
268 #define MACRO_NAND_CTL_CLRCLE(nandptr) do \
269 { \
270         switch((unsigned long)nandptr) \
271         { \
272             case CONFIG_SYS_NAND0_BASE: \
273                 out32(GPIO0_OR, in32(GPIO0_OR) & ~CONFIG_SYS_NAND0_CLE); \
274                 break; \
275             case CONFIG_SYS_NAND1_BASE: \
276                 out32(GPIO0_OR, in32(GPIO0_OR) & ~CONFIG_SYS_NAND1_CLE); \
277                 break; \
278         } \
279 } while(0)
280
281 #define MACRO_NAND_CTL_SETCLE(nandptr) do { \
282         switch((unsigned long)nandptr) { \
283         case CONFIG_SYS_NAND0_BASE: \
284                 out32(GPIO0_OR, in32(GPIO0_OR) | CONFIG_SYS_NAND0_CLE); \
285                 break; \
286         case CONFIG_SYS_NAND1_BASE: \
287                 out32(GPIO0_OR, in32(GPIO0_OR) | CONFIG_SYS_NAND1_CLE); \
288                 break; \
289         } \
290 } while(0)
291
292 #ifdef NAND_NO_RB
293 /* constant delay (see also tR in the datasheet) */
294 #define NAND_WAIT_READY(nand) do { \
295         udelay(12); \
296 } while (0)
297 #else
298 /* use the R/B pin */
299 /* TBD */
300 #endif
301
302 #define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0)
303 #define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0)
304 #define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)d; } while(0)
305 #define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)adr))
306
307 /*-----------------------------------------------------------------------
308  * PCI stuff
309  *-----------------------------------------------------------------------
310  */
311 #if 0   /* No PCI on CATcenter */
312 #define PCI_HOST_ADAPTER 0              /* configure as pci adapter     */
313 #define PCI_HOST_FORCE  1               /* configure as pci host        */
314 #define PCI_HOST_AUTO   2               /* detected via arbiter enable  */
315
316 #define CONFIG_PCI                      /* include pci support          */
317 #define CONFIG_PCI_INDIRECT_BRIDGE      /* indirect PCI bridge support */
318 #define CONFIG_PCI_HOST PCI_HOST_FORCE   /* select pci host function     */
319 #undef  CONFIG_PCI_PNP                  /* do pci plug-and-play         */
320                                         /* resource configuration       */
321
322 #define CONFIG_PCI_SCAN_SHOW            /* print pci devices @ startup  */
323
324 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1014   /* PCI Vendor ID: IBM   */
325 #define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0000   /* PCI Device ID: ---   */
326 #define CONFIG_SYS_PCI_CLASSCODE        0x0b20  /* PCI Class Code: Processor/PPC*/
327
328 #define CONFIG_SYS_PCI_PTM1LA   0x00000000      /* point to sdram               */
329 #define CONFIG_SYS_PCI_PTM1MS   0xfc000001      /* 64MB, enable hard-wired to 1 */
330 #define CONFIG_SYS_PCI_PTM1PCI 0x00000000       /* Host: use this pci address   */
331 #define CONFIG_SYS_PCI_PTM2LA   0xffc00000      /* point to flash               */
332 #define CONFIG_SYS_PCI_PTM2MS   0xffc00001      /* 4MB, enable                  */
333 #define CONFIG_SYS_PCI_PTM2PCI 0x04000000       /* Host: use this pci address   */
334 #endif  /* No PCI */
335
336 /*-----------------------------------------------------------------------
337  * Start addresses for the final memory configuration
338  * (Set up by the startup code)
339  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
340  */
341 #define CONFIG_SYS_SDRAM_BASE           0x00000000
342 #define CONFIG_SYS_FLASH_BASE           0xFFFC0000
343 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
344 #define CONFIG_SYS_MONITOR_LEN          (256 * 1024)    /* Reserve 256 kB for Monitor   */
345 #define CONFIG_SYS_MALLOC_LEN           (256 * 1024)    /* Reserve 256 kB for malloc()  */
346
347 /*
348  * For booting Linux, the board info and command line data
349  * have to be in the first 8 MB of memory, since this is
350  * the maximum mapped by the Linux kernel during initialization.
351  */
352 #define CONFIG_SYS_BOOTMAPSZ            (8 << 20)       /* Initial Memory map for Linux */
353 /*-----------------------------------------------------------------------
354  * FLASH organization
355  */
356 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* max number of memory banks           */
357 #define CONFIG_SYS_MAX_FLASH_SECT       256     /* max number of sectors on one chip    */
358
359 #define CONFIG_SYS_FLASH_ERASE_TOUT     120000  /* Timeout for Flash Erase (in ms)      */
360 #define CONFIG_SYS_FLASH_WRITE_TOUT     1000    /* Timeout for Flash Write (in ms)      */
361
362 #define CONFIG_SYS_FLASH_WORD_SIZE      unsigned short  /* flash word size (width)      */
363 #define CONFIG_SYS_FLASH_ADDR0          0x5555  /* 1st address for flash config cycles  */
364 #define CONFIG_SYS_FLASH_ADDR1          0x2AAA  /* 2nd address for flash config cycles  */
365 /*
366  * The following defines are added for buggy IOP480 byte interface.
367  * All other boards should use the standard values (CPCI405 etc.)
368  */
369 #define CONFIG_SYS_FLASH_READ0          0x0000  /* 0 is standard                        */
370 #define CONFIG_SYS_FLASH_READ1          0x0001  /* 1 is standard                        */
371 #define CONFIG_SYS_FLASH_READ2          0x0002  /* 2 is standard                        */
372
373 #define CONFIG_SYS_FLASH_EMPTY_INFO             /* print 'E' for empty sector on flinfo */
374
375 /*-----------------------------------------------------------------------
376  * Environment Variable setup
377  */
378 #define CONFIG_ENV_IS_IN_FLASH  1       /* use FLASH for environment vars */
379 #define CONFIG_ENV_ADDR         0xFFFF8000      /* environment starts at the first small sector */
380 #define CONFIG_ENV_SECT_SIZE    0x2000  /* 8196 bytes may be used for env vars*/
381 #define CONFIG_ENV_ADDR_REDUND  0xFFFFA000
382 #define CONFIG_ENV_SIZE_REDUND  0x2000
383
384 #define CONFIG_SYS_USE_PPCENV                   /* Environment embedded in sect .ppcenv */
385
386 #define CONFIG_SYS_NVRAM_BASE_ADDR      0xF0000500              /* NVRAM base address   */
387 #define CONFIG_SYS_NVRAM_SIZE           242                     /* NVRAM size           */
388
389 /*-----------------------------------------------------------------------
390  * I2C EEPROM (CAT24WC16) for environment
391  */
392 #define CONFIG_SYS_I2C
393 #define CONFIG_SYS_I2C_PPC4XX
394 #define CONFIG_SYS_I2C_PPC4XX_CH0
395 #define CONFIG_SYS_I2C_PPC4XX_SPEED_0           400000
396 #define CONFIG_SYS_I2C_PPC4XX_SLAVE_0           0x7F
397
398 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x50    /* EEPROM CAT28WC08             */
399 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1        /* Bytes of address             */
400 /* mask of address bits that overflow into the "EEPROM chip address"    */
401 /*#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW   0x07*/
402 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4     /* The Catalyst CAT24WC08 has   */
403                                         /* 16 byte page write mode using*/
404                                         /* last 4 bits of the address   */
405 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   10   /* and takes up to 10 msec */
406
407 /*
408  * Init Memory Controller:
409  *
410  * BR0/1 and OR0/1 (FLASH)
411  */
412
413 #define FLASH_BASE0_PRELIM      0xFFC00000      /* FLASH bank #0        */
414
415 /*-----------------------------------------------------------------------
416  * External Bus Controller (EBC) Setup
417  */
418
419 /* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization                       */
420 #define CONFIG_SYS_EBC_PB0AP            0x92015480
421 #define CONFIG_SYS_EBC_PB0CR            0xFFC5A000  /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
422
423 /* Memory Bank 1 (External SRAM) initialization                                 */
424 /* Since this must replace NOR Flash, we use the same settings for CS0          */
425 #define CONFIG_SYS_EBC_PB1AP            0x92015480
426 #define CONFIG_SYS_EBC_PB1CR            0xFF85A000  /* BAS=0xFF8,BS=4MB,BU=R/W,BW=8bit  */
427
428 /* Memory Bank 2 (Flash Bank 1, NAND-FLASH) initialization                      */
429 #define CONFIG_SYS_EBC_PB2AP            0x92015480
430 #define CONFIG_SYS_EBC_PB2CR            0xFF458000  /* BAS=0xFF4,BS=4MB,BU=R/W,BW=8bit  */
431
432 /* Memory Bank 3 (Flash Bank 2, NAND-FLASH) initialization                      */
433 #define CONFIG_SYS_EBC_PB3AP            0x92015480
434 #define CONFIG_SYS_EBC_PB3CR            0xFF058000  /* BAS=0xFF0,BS=4MB,BU=R/W,BW=8bit  */
435
436 #ifdef CONFIG_PPCHAMELEON_SMI712
437 /*
438  * Video console (graphic: SMI LynxEM)
439  */
440 #define CONFIG_VIDEO
441 #define CONFIG_CFB_CONSOLE
442 #define CONFIG_VIDEO_SMI_LYNXEM
443 #define CONFIG_VIDEO_LOGO
444 /*#define CONFIG_VIDEO_BMP_LOGO*/
445 #define CONFIG_CONSOLE_EXTRA_INFO
446 #define CONFIG_VGA_AS_SINGLE_DEVICE
447 /* This is the base address (on 405EP-side) used to generate I/O accesses on PCI bus */
448 #define CONFIG_SYS_ISA_IO 0xE8000000
449 /* see also drivers/video/videomodes.c */
450 #define CONFIG_SYS_DEFAULT_VIDEO_MODE 0x303
451 #endif
452
453 /*-----------------------------------------------------------------------
454  * FPGA stuff
455  */
456 /* FPGA internal regs */
457 #define CONFIG_SYS_FPGA_MODE            0x00
458 #define CONFIG_SYS_FPGA_STATUS          0x02
459 #define CONFIG_SYS_FPGA_TS              0x04
460 #define CONFIG_SYS_FPGA_TS_LOW          0x06
461 #define CONFIG_SYS_FPGA_TS_CAP0 0x10
462 #define CONFIG_SYS_FPGA_TS_CAP0_LOW     0x12
463 #define CONFIG_SYS_FPGA_TS_CAP1 0x14
464 #define CONFIG_SYS_FPGA_TS_CAP1_LOW     0x16
465 #define CONFIG_SYS_FPGA_TS_CAP2 0x18
466 #define CONFIG_SYS_FPGA_TS_CAP2_LOW     0x1a
467 #define CONFIG_SYS_FPGA_TS_CAP3 0x1c
468 #define CONFIG_SYS_FPGA_TS_CAP3_LOW     0x1e
469
470 /* FPGA Mode Reg */
471 #define CONFIG_SYS_FPGA_MODE_CF_RESET   0x0001
472 #define CONFIG_SYS_FPGA_MODE_TS_IRQ_ENABLE 0x0100
473 #define CONFIG_SYS_FPGA_MODE_TS_IRQ_CLEAR  0x1000
474 #define CONFIG_SYS_FPGA_MODE_TS_CLEAR   0x2000
475
476 /* FPGA Status Reg */
477 #define CONFIG_SYS_FPGA_STATUS_DIP0     0x0001
478 #define CONFIG_SYS_FPGA_STATUS_DIP1     0x0002
479 #define CONFIG_SYS_FPGA_STATUS_DIP2     0x0004
480 #define CONFIG_SYS_FPGA_STATUS_FLASH    0x0008
481 #define CONFIG_SYS_FPGA_STATUS_TS_IRQ   0x1000
482
483 #define CONFIG_SYS_FPGA_SPARTAN2        1               /* using Xilinx Spartan 2 now   */
484 #define CONFIG_SYS_FPGA_MAX_SIZE        128*1024        /* 128kByte is enough for XC2S50E*/
485
486 /* FPGA program pin configuration */
487 #define CONFIG_SYS_FPGA_PRG             0x04000000      /* FPGA program pin (ppc output) */
488 #define CONFIG_SYS_FPGA_CLK             0x02000000      /* FPGA clk pin (ppc output)    */
489 #define CONFIG_SYS_FPGA_DATA            0x01000000      /* FPGA data pin (ppc output)   */
490 #define CONFIG_SYS_FPGA_INIT            0x00010000      /* FPGA init pin (ppc input)    */
491 #define CONFIG_SYS_FPGA_DONE            0x00008000      /* FPGA done pin (ppc input)    */
492
493 /*-----------------------------------------------------------------------
494  * Definitions for initial stack pointer and data area (in data cache)
495  */
496 /* use on chip memory ( OCM ) for temperary stack until sdram is tested */
497 #define CONFIG_SYS_TEMP_STACK_OCM       1
498
499 /* On Chip Memory location */
500 #define CONFIG_SYS_OCM_DATA_ADDR        0xF8000000
501 #define CONFIG_SYS_OCM_DATA_SIZE        0x1000
502 #define CONFIG_SYS_INIT_RAM_ADDR        CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM             */
503 #define CONFIG_SYS_INIT_RAM_SIZE        CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM    */
504
505 #define CONFIG_SYS_GBL_DATA_OFFSET    (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
506 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
507
508 /*-----------------------------------------------------------------------
509  * Definitions for GPIO setup (PPC405EP specific)
510  *
511  * GPIO0[0]     - External Bus Controller BLAST output
512  * GPIO0[1-9]   - Instruction trace outputs -> GPIO
513  * GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs
514  * GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs -> GPIO
515  * GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs
516  * GPIO0[24-27] - UART0 control signal inputs/outputs
517  * GPIO0[28-29] - UART1 data signal input/output
518  * GPIO0[30]    - EMAC0 input
519  * GPIO0[31]    - EMAC1 reject packet as output
520  */
521 #define CONFIG_SYS_GPIO0_OSRL           0x40000550
522 #define CONFIG_SYS_GPIO0_OSRH           0x00000110
523 #define CONFIG_SYS_GPIO0_ISR1L          0x00000000
524 /*#define CONFIG_SYS_GPIO0_ISR1H        0x15555445*/
525 #define CONFIG_SYS_GPIO0_ISR1H          0x15555444
526 #define CONFIG_SYS_GPIO0_TSRL           0x00000000
527 #define CONFIG_SYS_GPIO0_TSRH           0x00000000
528 #define CONFIG_SYS_GPIO0_TCR            0xF7FF8014
529
530 #define CONFIG_NO_SERIAL_EEPROM
531
532 /*--------------------------------------------------------------------*/
533
534 #ifdef CONFIG_NO_SERIAL_EEPROM
535
536 /*
537 !-----------------------------------------------------------------------
538 ! Defines for entry options.
539 ! Note: Because the 405EP SDRAM controller does not support ECC, ECC DIMMs that
540 !       are plugged in the board will be utilized as non-ECC DIMMs.
541 !-----------------------------------------------------------------------
542 */
543 #undef          AUTO_MEMORY_CONFIG
544 #define         DIMM_READ_ADDR 0xAB
545 #define         DIMM_WRITE_ADDR 0xAA
546
547 /* Defines for CPC0_PLLMR1 Register fields */
548 #define PLL_ACTIVE              0x80000000
549 #define CPC0_PLLMR1_SSCS        0x80000000
550 #define PLL_RESET               0x40000000
551 #define CPC0_PLLMR1_PLLR        0x40000000
552     /* Feedback multiplier */
553 #define PLL_FBKDIV              0x00F00000
554 #define CPC0_PLLMR1_FBDV        0x00F00000
555 #define PLL_FBKDIV_16           0x00000000
556 #define PLL_FBKDIV_1            0x00100000
557 #define PLL_FBKDIV_2            0x00200000
558 #define PLL_FBKDIV_3            0x00300000
559 #define PLL_FBKDIV_4            0x00400000
560 #define PLL_FBKDIV_5            0x00500000
561 #define PLL_FBKDIV_6            0x00600000
562 #define PLL_FBKDIV_7            0x00700000
563 #define PLL_FBKDIV_8            0x00800000
564 #define PLL_FBKDIV_9            0x00900000
565 #define PLL_FBKDIV_10           0x00A00000
566 #define PLL_FBKDIV_11           0x00B00000
567 #define PLL_FBKDIV_12           0x00C00000
568 #define PLL_FBKDIV_13           0x00D00000
569 #define PLL_FBKDIV_14           0x00E00000
570 #define PLL_FBKDIV_15           0x00F00000
571     /* Forward A divisor */
572 #define PLL_FWDDIVA             0x00070000
573 #define CPC0_PLLMR1_FWDVA       0x00070000
574 #define PLL_FWDDIVA_8           0x00000000
575 #define PLL_FWDDIVA_7           0x00010000
576 #define PLL_FWDDIVA_6           0x00020000
577 #define PLL_FWDDIVA_5           0x00030000
578 #define PLL_FWDDIVA_4           0x00040000
579 #define PLL_FWDDIVA_3           0x00050000
580 #define PLL_FWDDIVA_2           0x00060000
581 #define PLL_FWDDIVA_1           0x00070000
582     /* Forward B divisor */
583 #define PLL_FWDDIVB             0x00007000
584 #define CPC0_PLLMR1_FWDVB       0x00007000
585 #define PLL_FWDDIVB_8           0x00000000
586 #define PLL_FWDDIVB_7           0x00001000
587 #define PLL_FWDDIVB_6           0x00002000
588 #define PLL_FWDDIVB_5           0x00003000
589 #define PLL_FWDDIVB_4           0x00004000
590 #define PLL_FWDDIVB_3           0x00005000
591 #define PLL_FWDDIVB_2           0x00006000
592 #define PLL_FWDDIVB_1           0x00007000
593     /* PLL tune bits */
594 #define PLL_TUNE_MASK           0x000003FF
595 #define PLL_TUNE_2_M_3          0x00000133      /*  2 <= M <= 3                 */
596 #define PLL_TUNE_4_M_6          0x00000134      /*  3 <  M <= 6                 */
597 #define PLL_TUNE_7_M_10         0x00000138      /*  6 <  M <= 10                */
598 #define PLL_TUNE_11_M_14        0x0000013C      /* 10 <  M <= 14                */
599 #define PLL_TUNE_15_M_40        0x0000023E      /* 14 <  M <= 40                */
600 #define PLL_TUNE_VCO_LOW        0x00000000      /* 500MHz <= VCO <=  800MHz     */
601 #define PLL_TUNE_VCO_HI         0x00000080      /* 800MHz <  VCO <= 1000MHz     */
602
603 /* Defines for CPC0_PLLMR0 Register fields */
604     /* CPU divisor */
605 #define PLL_CPUDIV              0x00300000
606 #define CPC0_PLLMR0_CCDV        0x00300000
607 #define PLL_CPUDIV_1            0x00000000
608 #define PLL_CPUDIV_2            0x00100000
609 #define PLL_CPUDIV_3            0x00200000
610 #define PLL_CPUDIV_4            0x00300000
611     /* PLB divisor */
612 #define PLL_PLBDIV              0x00030000
613 #define CPC0_PLLMR0_CBDV        0x00030000
614 #define PLL_PLBDIV_1            0x00000000
615 #define PLL_PLBDIV_2            0x00010000
616 #define PLL_PLBDIV_3            0x00020000
617 #define PLL_PLBDIV_4            0x00030000
618     /* OPB divisor */
619 #define PLL_OPBDIV              0x00003000
620 #define CPC0_PLLMR0_OPDV        0x00003000
621 #define PLL_OPBDIV_1            0x00000000
622 #define PLL_OPBDIV_2            0x00001000
623 #define PLL_OPBDIV_3            0x00002000
624 #define PLL_OPBDIV_4            0x00003000
625     /* EBC divisor */
626 #define PLL_EXTBUSDIV           0x00000300
627 #define CPC0_PLLMR0_EPDV        0x00000300
628 #define PLL_EXTBUSDIV_2         0x00000000
629 #define PLL_EXTBUSDIV_3         0x00000100
630 #define PLL_EXTBUSDIV_4         0x00000200
631 #define PLL_EXTBUSDIV_5         0x00000300
632     /* MAL divisor */
633 #define PLL_MALDIV              0x00000030
634 #define CPC0_PLLMR0_MPDV        0x00000030
635 #define PLL_MALDIV_1            0x00000000
636 #define PLL_MALDIV_2            0x00000010
637 #define PLL_MALDIV_3            0x00000020
638 #define PLL_MALDIV_4            0x00000030
639     /* PCI divisor */
640 #define PLL_PCIDIV              0x00000003
641 #define CPC0_PLLMR0_PPFD        0x00000003
642 #define PLL_PCIDIV_1            0x00000000
643 #define PLL_PCIDIV_2            0x00000001
644 #define PLL_PCIDIV_3            0x00000002
645 #define PLL_PCIDIV_4            0x00000003
646
647 #ifdef CONFIG_PPCHAMELEON_CLK_25
648 /* CPU - PLB/SDRAM - EBC - OPB - PCI (assuming a 25.0 MHz input clock to the 405EP) */
649 #define PPCHAMELEON_PLLMR0_133_133_33_66_33      (PLL_CPUDIV_1 | PLL_PLBDIV_1 |  \
650                               PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 |  \
651                               PLL_MALDIV_1 | PLL_PCIDIV_4)
652 #define PPCHAMELEON_PLLMR1_133_133_33_66_33      (PLL_FBKDIV_8  |  \
653                               PLL_FWDDIVA_6 | PLL_FWDDIVB_4 |  \
654                               PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
655
656 #define PPCHAMELEON_PLLMR0_200_100_50_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 |  \
657                               PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 |  \
658                               PLL_MALDIV_1 | PLL_PCIDIV_4)
659 #define PPCHAMELEON_PLLMR1_200_100_50_33 (PLL_FBKDIV_8  |  \
660                               PLL_FWDDIVA_4 | PLL_FWDDIVB_4 |  \
661                               PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
662
663 #define PPCHAMELEON_PLLMR0_266_133_33_66_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 |      \
664                               PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 |  \
665                               PLL_MALDIV_1 | PLL_PCIDIV_4)
666 #define PPCHAMELEON_PLLMR1_266_133_33_66_33 (PLL_FBKDIV_8  |  \
667                               PLL_FWDDIVA_3 | PLL_FWDDIVB_4 |  \
668                               PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
669
670 #define PPCHAMELEON_PLLMR0_333_111_37_55_55 (PLL_CPUDIV_1 | PLL_PLBDIV_3 |      \
671                               PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 |  \
672                               PLL_MALDIV_1 | PLL_PCIDIV_2)
673 #define PPCHAMELEON_PLLMR1_333_111_37_55_55 (PLL_FBKDIV_10      |  \
674                               PLL_FWDDIVA_3 | PLL_FWDDIVB_4 |  \
675                               PLL_TUNE_15_M_40 | PLL_TUNE_VCO_HI)
676
677 #elif (defined (CONFIG_PPCHAMELEON_CLK_33))
678
679 /* CPU - PLB/SDRAM - EBC - OPB - PCI (assuming a 33.3MHz input clock to the 405EP) */
680 #define PPCHAMELEON_PLLMR0_133_133_33_66_33      (PLL_CPUDIV_1 | PLL_PLBDIV_1 |  \
681                                   PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 |      \
682                                   PLL_MALDIV_1 | PLL_PCIDIV_4)
683 #define PPCHAMELEON_PLLMR1_133_133_33_66_33      (PLL_FBKDIV_4  |  \
684                                   PLL_FWDDIVA_6 | PLL_FWDDIVB_6 |  \
685                                   PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
686
687 #define PPCHAMELEON_PLLMR0_200_100_50_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 |  \
688                                   PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 |      \
689                                   PLL_MALDIV_1 | PLL_PCIDIV_4)
690 #define PPCHAMELEON_PLLMR1_200_100_50_33 (PLL_FBKDIV_6  |  \
691                                   PLL_FWDDIVA_4 | PLL_FWDDIVB_4 |  \
692                                   PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
693
694 #define PPCHAMELEON_PLLMR0_266_133_33_66_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 |      \
695                                   PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 |      \
696                                   PLL_MALDIV_1 | PLL_PCIDIV_4)
697 #define PPCHAMELEON_PLLMR1_266_133_33_66_33 (PLL_FBKDIV_8  |  \
698                                   PLL_FWDDIVA_3 | PLL_FWDDIVB_3 |  \
699                                   PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
700
701 #define PPCHAMELEON_PLLMR0_333_111_37_55_55 (PLL_CPUDIV_1 | PLL_PLBDIV_3 |      \
702                                   PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 |      \
703                                   PLL_MALDIV_1 | PLL_PCIDIV_2)
704 #define PPCHAMELEON_PLLMR1_333_111_37_55_55 (PLL_FBKDIV_10      |  \
705                                   PLL_FWDDIVA_3 | PLL_FWDDIVB_3 |  \
706                                   PLL_TUNE_15_M_40 | PLL_TUNE_VCO_HI)
707
708 #else
709 #error "* External frequency (SysClk) not defined! *"
710 #endif
711
712 #if   (CONFIG_PPCHAMELEON_MODULE_MODEL == CONFIG_PPCHAMELEON_MODULE_HI)
713 /* Model HI */
714 #define PLLMR0_DEFAULT  PPCHAMELEON_PLLMR0_333_111_37_55_55
715 #define PLLMR1_DEFAULT  PPCHAMELEON_PLLMR1_333_111_37_55_55
716 #define CONFIG_SYS_OPB_FREQ     55555555
717 /* Model ME */
718 #elif (CONFIG_PPCHAMELEON_MODULE_MODEL == CONFIG_PPCHAMELEON_MODULE_ME)
719 #define PLLMR0_DEFAULT  PPCHAMELEON_PLLMR0_266_133_33_66_33
720 #define PLLMR1_DEFAULT  PPCHAMELEON_PLLMR1_266_133_33_66_33
721 #define CONFIG_SYS_OPB_FREQ     66666666
722 #else
723 /* Model BA (default) */
724 #define PLLMR0_DEFAULT  PPCHAMELEON_PLLMR0_133_133_33_66_33
725 #define PLLMR1_DEFAULT  PPCHAMELEON_PLLMR1_133_133_33_66_33
726 #define CONFIG_SYS_OPB_FREQ     66666666
727 #endif
728
729 #endif /* CONFIG_NO_SERIAL_EEPROM */
730
731 #define CONFIG_JFFS2_NAND 1                     /* jffs2 on nand support */
732 #define NAND_CACHE_PAGES 16                     /* size of nand cache in 512 bytes pages */
733
734 /*
735  * JFFS2 partitions
736  *
737  */
738 /* No command line, one static partition */
739 #undef CONFIG_CMD_MTDPARTS
740 #define CONFIG_JFFS2_DEV                "nand"
741 #define CONFIG_JFFS2_PART_SIZE          0x00200000
742 #define CONFIG_JFFS2_PART_OFFSET        0x00000000
743
744 /* mtdparts command line support
745  *
746  * Note: fake mtd_id used, no linux mtd map file
747  */
748 /*
749 #define CONFIG_CMD_MTDPARTS
750 #define MTDIDS_DEFAULT          "nand0=catcenter"
751 #define MTDPARTS_DEFAULT        "mtdparts=catcenter:2m(nand)"
752 */
753
754 #endif  /* __CONFIG_H */