include/configs/CATcenter.h

   1 /*
   2  * ueberarbeitet durch Christoph Seyfert
   3  *
   4  * (C) Copyright 2004-2005 DENX Software Engineering,
   5  *     Wolfgang Grandegger <wg@denx.de>
   6  * (C) Copyright 2003
   7  *     DAVE Srl
   8  *
   9  * http://www.dave-tech.it
  10  * http://www.wawnet.biz
  11  * mailto:info@wawnet.biz
  12  *
  13  * Credits: Stefan Roese, Wolfgang Denk
  14  *
  15  * SPDX-License-Identifier:     GPL-2.0+
  16  */
  17
  18 /*
  19  * board/config.h - configuration options, board specific
  20  */
  21
  22 #ifndef __CONFIG_H
  23 #define __CONFIG_H
  24
  25 #define CONFIG_PPCHAMELEON_MODULE_BA    0       /* Basic    Model */
  26 #define CONFIG_PPCHAMELEON_MODULE_ME    1       /* Medium   Model */
  27 #define CONFIG_PPCHAMELEON_MODULE_HI    2       /* High-End Model */
  28 #ifndef CONFIG_PPCHAMELEON_MODULE_MODEL
  29 #define CONFIG_PPCHAMELEON_MODULE_MODEL CONFIG_PPCHAMELEON_MODULE_BA
  30 #endif
  31
  32 /* Only one of the following two symbols must be defined (default is 25 MHz)
  33  * CONFIG_PPCHAMELEON_CLK_25
  34  * CONFIG_PPCHAMELEON_CLK_33
  35  */
  36 #if (!defined(CONFIG_PPCHAMELEON_CLK_25) && !defined(CONFIG_PPCHAMELEON_CLK_33))
  37 #define CONFIG_PPCHAMELEON_CLK_25
  38 #endif
  39
  40 #if (defined(CONFIG_PPCHAMELEON_CLK_25) && defined(CONFIG_PPCHAMELEON_CLK_33))
  41 #error "* Two external frequencies (SysClk) are defined! *"
  42 #endif
  43
  44 #undef CONFIG_PPCHAMELEON_SMI712
  45
  46 /*
  47  * Debug stuff
  48  */
  49 #undef  __DEBUG_START_FROM_SRAM__
  50 #define __DISABLE_MACHINE_EXCEPTION__
  51
  52 #ifdef __DEBUG_START_FROM_SRAM__
  53 #define CONFIG_SYS_DUMMY_FLASH_SIZE             1024*1024*4
  54 #endif
  55
  56 /*
  57  * High Level Configuration Options
  58  * (easy to change)
  59  */
  60
  61 #define CONFIG_405EP            1       /* This is a PPC405 CPU         */
  62 #define CONFIG_PPCHAMELEONEVB   1       /* ...on a PPChameleonEVB board */
  63
  64 #define CONFIG_SYS_TEXT_BASE    0xFFFB0000      /* Reserve 320 kB for Monitor */
  65 #define CONFIG_SYS_LDSCRIPT     "board/dave/PPChameleonEVB/u-boot.lds"
  66
  67 #define CONFIG_BOARD_EARLY_INIT_F 1     /* call board_early_init_f()    */
  68 #define CONFIG_MISC_INIT_R      1       /* call misc_init_r()           */
  69
  70 #ifdef CONFIG_PPCHAMELEON_CLK_25
  71 # define CONFIG_SYS_CLK_FREQ    25000000 /* external frequency to pll   */
  72 #elif (defined (CONFIG_PPCHAMELEON_CLK_33))
  73 #define CONFIG_SYS_CLK_FREQ     33333333 /* external frequency to pll   */
  74 #else
  75 # error "* External frequency (SysClk) not defined! *"
  76 #endif
  77
  78 #define CONFIG_CONS_INDEX       2       /* Use UART1                    */
  79 #define CONFIG_SYS_NS16550
  80 #define CONFIG_SYS_NS16550_SERIAL
  81 #define CONFIG_SYS_NS16550_REG_SIZE     1
  82 #define CONFIG_SYS_NS16550_CLK          get_serial_clock()
  83 #define CONFIG_BAUDRATE         115200
  84 #define CONFIG_BOOTDELAY        5       /* autoboot after 5 seconds     */
  85
  86 #define CONFIG_VERSION_VARIABLE 1       /* add version variable         */
  87 #define CONFIG_IDENT_STRING     "1"
  88
  89 #undef  CONFIG_BOOTARGS
  90
  91 /* Ethernet stuff */
  92 #define CONFIG_ENV_OVERWRITE /* Let the user to change the Ethernet MAC addresses */
  93 #define CONFIG_ETHADDR  00:50:C2:1E:AF:FE
  94 #define CONFIG_HAS_ETH1
  95 #define CONFIG_ETH1ADDR 00:50:C2:1E:AF:FD
  96
  97 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download  */
  98 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change        */
  99
 100
 101 #define CONFIG_PPC4xx_EMAC
 102 #undef CONFIG_EXT_PHY
 103
 104 #define CONFIG_MII              1       /* MII PHY management           */
 105 #ifndef  CONFIG_EXT_PHY
 106 #define CONFIG_PHY_ADDR         1       /* EMAC0 PHY address            */
 107 #define CONFIG_PHY1_ADDR        16      /* EMAC1 PHY address            */
 108 #else
 109 #define CONFIG_PHY_ADDR         2       /* PHY address                  */
 110 #endif
 111 #define CONFIG_PHY_CLK_FREQ     EMAC_STACR_CLK_66MHZ
 112
 113 #define CONFIG_TIMESTAMP                /* Print image info with timestamp */
 114
 115
 116 /*
 117  * BOOTP options
 118  */
 119 #define CONFIG_BOOTP_BOOTFILESIZE
 120 #define CONFIG_BOOTP_BOOTPATH
 121 #define CONFIG_BOOTP_GATEWAY
 122 #define CONFIG_BOOTP_HOSTNAME
 123
 124
 125 /*
 126  * Command line configuration.
 127  */
 128 #include <config_cmd_default.h>
 129
 130 #define CONFIG_CMD_DHCP
 131 #define CONFIG_CMD_ELF
 132 #define CONFIG_CMD_EEPROM
 133 #define CONFIG_CMD_I2C
 134 #define CONFIG_CMD_IRQ
 135 #define CONFIG_CMD_JFFS2
 136 #define CONFIG_CMD_MII
 137 #define CONFIG_CMD_NAND
 138 #define CONFIG_CMD_NFS
 139 #define CONFIG_CMD_SNTP
 140
 141
 142 #define CONFIG_MAC_PARTITION
 143 #define CONFIG_DOS_PARTITION
 144
 145 #undef  CONFIG_WATCHDOG                 /* watchdog disabled            */
 146
 147 #define CONFIG_RTC_MC146818             /* DS1685 is MC146818 compatible*/
 148 #define CONFIG_SYS_RTC_REG_BASE_ADDR     0xF0000500 /* RTC Base Address         */
 149
 150 #define CONFIG_SDRAM_BANK0      1       /* init onboard SDRAM bank 0    */
 151
 152 /*
 153  * Miscellaneous configurable options
 154  */
 155 #define CONFIG_SYS_LONGHELP                     /* undef to save memory         */
 156
 157 #define CONFIG_SYS_HUSH_PARSER                  /* use "hush" command parser    */
 158
 159 #if defined(CONFIG_CMD_KGDB)
 160 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size      */
 161 #else
 162 #define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size      */
 163 #endif
 164 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
 165 #define CONFIG_SYS_MAXARGS      16              /* max number of command args   */
 166 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size    */
 167
 168 #define CONFIG_SYS_DEVICE_NULLDEV       1       /* include nulldev device       */
 169
 170 #define CONFIG_SYS_CONSOLE_INFO_QUIET   1       /* don't print console @ startup*/
 171
 172 #define CONFIG_SYS_MEMTEST_START        0x0400000       /* memtest works on     */
 173 #define CONFIG_SYS_MEMTEST_END          0x0C00000       /* 4 ... 12 MB in DRAM  */
 174
 175 #undef  CONFIG_SYS_EXT_SERIAL_CLOCK             /* no external serial clock used */
 176 #define CONFIG_SYS_BASE_BAUD            691200
 177
 178 /* The following table includes the supported baudrates */
 179 #define CONFIG_SYS_BAUDRATE_TABLE       \
 180         { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400,     \
 181          57600, 115200, 230400, 460800, 921600 }
 182
 183 #define CONFIG_SYS_LOAD_ADDR    0x100000        /* default load address */
 184 #define CONFIG_SYS_EXTBDINFO    1               /* To use extended board_into (bd_t) */
 185
 186 #define CONFIG_ZERO_BOOTDELAY_CHECK     /* check for keypress on bootdelay==0 */
 187
 188 /*-----------------------------------------------------------------------
 189  * NAND-FLASH stuff
 190  *-----------------------------------------------------------------------
 191  */
 192 #define CONFIG_SYS_NAND0_BASE 0xFF400000
 193 #define CONFIG_SYS_NAND1_BASE 0xFF000000
 194 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND0_BASE }
 195 #define NAND_BIG_DELAY_US       25
 196
 197 /* For CATcenter there is only NAND on the module */
 198 #define CONFIG_SYS_MAX_NAND_DEVICE      1       /* Max number of NAND devices           */
 199 #define NAND_NO_RB
 200
 201 #define CONFIG_SYS_NAND0_CE  (0x80000000 >> 1)   /* our CE is GPIO1 */
 202 #define CONFIG_SYS_NAND0_CLE (0x80000000 >> 2)   /* our CLE is GPIO2 */
 203 #define CONFIG_SYS_NAND0_ALE (0x80000000 >> 3)   /* our ALE is GPIO3 */
 204 #define CONFIG_SYS_NAND0_RDY (0x80000000 >> 4)   /* our RDY is GPIO4 */
 205
 206 #define CONFIG_SYS_NAND1_CE  (0x80000000 >> 14)  /* our CE is GPIO14 */
 207 #define CONFIG_SYS_NAND1_CLE (0x80000000 >> 15)  /* our CLE is GPIO15 */
 208 #define CONFIG_SYS_NAND1_ALE (0x80000000 >> 16)  /* our ALE is GPIO16 */
 209 #define CONFIG_SYS_NAND1_RDY (0x80000000 >> 31)  /* our RDY is GPIO31 */
 210
 211
 212 #define MACRO_NAND_DISABLE_CE(nandptr) do \
 213 { \
 214         switch((unsigned long)nandptr) \
 215         { \
 216             case CONFIG_SYS_NAND0_BASE: \
 217                 out32(GPIO0_OR, in32(GPIO0_OR) | CONFIG_SYS_NAND0_CE); \
 218                 break; \
 219             case CONFIG_SYS_NAND1_BASE: \
 220                 out32(GPIO0_OR, in32(GPIO0_OR) | CONFIG_SYS_NAND1_CE); \
 221                 break; \
 222         } \
 223 } while(0)
 224
 225 #define MACRO_NAND_ENABLE_CE(nandptr) do \
 226 { \
 227         switch((unsigned long)nandptr) \
 228         { \
 229             case CONFIG_SYS_NAND0_BASE: \
 230                 out32(GPIO0_OR, in32(GPIO0_OR) & ~CONFIG_SYS_NAND0_CE); \
 231                 break; \
 232             case CONFIG_SYS_NAND1_BASE: \
 233                 out32(GPIO0_OR, in32(GPIO0_OR) & ~CONFIG_SYS_NAND1_CE); \
 234                 break; \
 235         } \
 236 } while(0)
 237
 238 #define MACRO_NAND_CTL_CLRALE(nandptr) do \
 239 { \
 240         switch((unsigned long)nandptr) \
 241         { \
 242             case CONFIG_SYS_NAND0_BASE: \
 243                 out32(GPIO0_OR, in32(GPIO0_OR) & ~CONFIG_SYS_NAND0_ALE); \
 244                 break; \
 245             case CONFIG_SYS_NAND1_BASE: \
 246                 out32(GPIO0_OR, in32(GPIO0_OR) & ~CONFIG_SYS_NAND1_ALE); \
 247                 break; \
 248         } \
 249 } while(0)
 250
 251 #define MACRO_NAND_CTL_SETALE(nandptr) do \
 252 { \
 253         switch((unsigned long)nandptr) \
 254         { \
 255             case CONFIG_SYS_NAND0_BASE: \
 256                 out32(GPIO0_OR, in32(GPIO0_OR) | CONFIG_SYS_NAND0_ALE); \
 257                 break; \
 258             case CONFIG_SYS_NAND1_BASE: \
 259                 out32(GPIO0_OR, in32(GPIO0_OR) | CONFIG_SYS_NAND1_ALE); \
 260                 break; \
 261         } \
 262 } while(0)
 263
 264 #define MACRO_NAND_CTL_CLRCLE(nandptr) do \
 265 { \
 266         switch((unsigned long)nandptr) \
 267         { \
 268             case CONFIG_SYS_NAND0_BASE: \
 269                 out32(GPIO0_OR, in32(GPIO0_OR) & ~CONFIG_SYS_NAND0_CLE); \
 270                 break; \
 271             case CONFIG_SYS_NAND1_BASE: \
 272                 out32(GPIO0_OR, in32(GPIO0_OR) & ~CONFIG_SYS_NAND1_CLE); \
 273                 break; \
 274         } \
 275 } while(0)
 276
 277 #define MACRO_NAND_CTL_SETCLE(nandptr) do { \
 278         switch((unsigned long)nandptr) { \
 279         case CONFIG_SYS_NAND0_BASE: \
 280                 out32(GPIO0_OR, in32(GPIO0_OR) | CONFIG_SYS_NAND0_CLE); \
 281                 break; \
 282         case CONFIG_SYS_NAND1_BASE: \
 283                 out32(GPIO0_OR, in32(GPIO0_OR) | CONFIG_SYS_NAND1_CLE); \
 284                 break; \
 285         } \
 286 } while(0)
 287
 288 #ifdef NAND_NO_RB
 289 /* constant delay (see also tR in the datasheet) */
 290 #define NAND_WAIT_READY(nand) do { \
 291         udelay(12); \
 292 } while (0)
 293 #else
 294 /* use the R/B pin */
 295 /* TBD */
 296 #endif
 297
 298 #define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0)
 299 #define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0)
 300 #define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)d; } while(0)
 301 #define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)adr))
 302
 303 /*-----------------------------------------------------------------------
 304  * PCI stuff
 305  *-----------------------------------------------------------------------
 306  */
 307 #if 0   /* No PCI on CATcenter */
 308 #define PCI_HOST_ADAPTER 0              /* configure as pci adapter     */
 309 #define PCI_HOST_FORCE  1               /* configure as pci host        */
 310 #define PCI_HOST_AUTO   2               /* detected via arbiter enable  */
 311
 312 #define CONFIG_PCI                      /* include pci support          */
 313 #define CONFIG_PCI_INDIRECT_BRIDGE      /* indirect PCI bridge support */
 314 #define CONFIG_PCI_HOST PCI_HOST_FORCE   /* select pci host function     */
 315 #undef  CONFIG_PCI_PNP                  /* do pci plug-and-play         */
 316                                         /* resource configuration       */
 317
 318 #define CONFIG_PCI_SCAN_SHOW            /* print pci devices @ startup  */
 319
 320 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1014   /* PCI Vendor ID: IBM   */
 321 #define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0000   /* PCI Device ID: ---   */
 322 #define CONFIG_SYS_PCI_CLASSCODE        0x0b20  /* PCI Class Code: Processor/PPC*/
 323
 324 #define CONFIG_SYS_PCI_PTM1LA   0x00000000      /* point to sdram               */
 325 #define CONFIG_SYS_PCI_PTM1MS   0xfc000001      /* 64MB, enable hard-wired to 1 */
 326 #define CONFIG_SYS_PCI_PTM1PCI 0x00000000       /* Host: use this pci address   */
 327 #define CONFIG_SYS_PCI_PTM2LA   0xffc00000      /* point to flash               */
 328 #define CONFIG_SYS_PCI_PTM2MS   0xffc00001      /* 4MB, enable                  */
 329 #define CONFIG_SYS_PCI_PTM2PCI 0x04000000       /* Host: use this pci address   */
 330 #endif  /* No PCI */
 331
 332 /*-----------------------------------------------------------------------
 333  * Start addresses for the final memory configuration
 334  * (Set up by the startup code)
 335  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 336  */
 337 #define CONFIG_SYS_SDRAM_BASE           0x00000000
 338 #define CONFIG_SYS_FLASH_BASE           0xFFFC0000
 339 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
 340 #define CONFIG_SYS_MONITOR_LEN          (256 * 1024)    /* Reserve 256 kB for Monitor   */
 341 #define CONFIG_SYS_MALLOC_LEN           (256 * 1024)    /* Reserve 256 kB for malloc()  */
 342
 343 /*
 344  * For booting Linux, the board info and command line data
 345  * have to be in the first 8 MB of memory, since this is
 346  * the maximum mapped by the Linux kernel during initialization.
 347  */
 348 #define CONFIG_SYS_BOOTMAPSZ            (8 << 20)       /* Initial Memory map for Linux */
 349 /*-----------------------------------------------------------------------
 350  * FLASH organization
 351  */
 352 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* max number of memory banks           */
 353 #define CONFIG_SYS_MAX_FLASH_SECT       256     /* max number of sectors on one chip    */
 354
 355 #define CONFIG_SYS_FLASH_ERASE_TOUT     120000  /* Timeout for Flash Erase (in ms)      */
 356 #define CONFIG_SYS_FLASH_WRITE_TOUT     1000    /* Timeout for Flash Write (in ms)      */
 357
 358 #define CONFIG_SYS_FLASH_WORD_SIZE      unsigned short  /* flash word size (width)      */
 359 #define CONFIG_SYS_FLASH_ADDR0          0x5555  /* 1st address for flash config cycles  */
 360 #define CONFIG_SYS_FLASH_ADDR1          0x2AAA  /* 2nd address for flash config cycles  */
 361 /*
 362  * The following defines are added for buggy IOP480 byte interface.
 363  * All other boards should use the standard values (CPCI405 etc.)
 364  */
 365 #define CONFIG_SYS_FLASH_READ0          0x0000  /* 0 is standard                        */
 366 #define CONFIG_SYS_FLASH_READ1          0x0001  /* 1 is standard                        */
 367 #define CONFIG_SYS_FLASH_READ2          0x0002  /* 2 is standard                        */
 368
 369 #define CONFIG_SYS_FLASH_EMPTY_INFO             /* print 'E' for empty sector on flinfo */
 370
 371 /*-----------------------------------------------------------------------
 372  * Environment Variable setup
 373  */
 374 #define CONFIG_ENV_IS_IN_FLASH  1       /* use FLASH for environment vars */
 375 #define CONFIG_ENV_ADDR         0xFFFF8000      /* environment starts at the first small sector */
 376 #define CONFIG_ENV_SECT_SIZE    0x2000  /* 8196 bytes may be used for env vars*/
 377 #define CONFIG_ENV_ADDR_REDUND  0xFFFFA000
 378 #define CONFIG_ENV_SIZE_REDUND  0x2000
 379
 380 #define CONFIG_SYS_USE_PPCENV                   /* Environment embedded in sect .ppcenv */
 381
 382 #define CONFIG_SYS_NVRAM_BASE_ADDR      0xF0000500              /* NVRAM base address   */
 383 #define CONFIG_SYS_NVRAM_SIZE           242                     /* NVRAM size           */
 384
 385 /*-----------------------------------------------------------------------
 386  * I2C EEPROM (CAT24WC16) for environment
 387  */
 388 #define CONFIG_SYS_I2C
 389 #define CONFIG_SYS_I2C_PPC4XX
 390 #define CONFIG_SYS_I2C_PPC4XX_CH0
 391 #define CONFIG_SYS_I2C_PPC4XX_SPEED_0           400000
 392 #define CONFIG_SYS_I2C_PPC4XX_SLAVE_0           0x7F
 393
 394 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x50    /* EEPROM CAT28WC08             */
 395 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1        /* Bytes of address             */
 396 /* mask of address bits that overflow into the "EEPROM chip address"    */
 397 /*#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW   0x07*/
 398 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4     /* The Catalyst CAT24WC08 has   */
 399                                         /* 16 byte page write mode using*/
 400                                         /* last 4 bits of the address   */
 401 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   10   /* and takes up to 10 msec */
 402
 403 /*
 404  * Init Memory Controller:
 405  *
 406  * BR0/1 and OR0/1 (FLASH)
 407  */
 408
 409 #define FLASH_BASE0_PRELIM      0xFFC00000      /* FLASH bank #0        */
 410
 411 /*-----------------------------------------------------------------------
 412  * External Bus Controller (EBC) Setup
 413  */
 414
 415 /* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization                       */
 416 #define CONFIG_SYS_EBC_PB0AP            0x92015480
 417 #define CONFIG_SYS_EBC_PB0CR            0xFFC5A000  /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
 418
 419 /* Memory Bank 1 (External SRAM) initialization                                 */
 420 /* Since this must replace NOR Flash, we use the same settings for CS0          */
 421 #define CONFIG_SYS_EBC_PB1AP            0x92015480
 422 #define CONFIG_SYS_EBC_PB1CR            0xFF85A000  /* BAS=0xFF8,BS=4MB,BU=R/W,BW=8bit  */
 423
 424 /* Memory Bank 2 (Flash Bank 1, NAND-FLASH) initialization                      */
 425 #define CONFIG_SYS_EBC_PB2AP            0x92015480
 426 #define CONFIG_SYS_EBC_PB2CR            0xFF458000  /* BAS=0xFF4,BS=4MB,BU=R/W,BW=8bit  */
 427
 428 /* Memory Bank 3 (Flash Bank 2, NAND-FLASH) initialization                      */
 429 #define CONFIG_SYS_EBC_PB3AP            0x92015480
 430 #define CONFIG_SYS_EBC_PB3CR            0xFF058000  /* BAS=0xFF0,BS=4MB,BU=R/W,BW=8bit  */
 431
 432 #ifdef CONFIG_PPCHAMELEON_SMI712
 433 /*
 434  * Video console (graphic: SMI LynxEM)
 435  */
 436 #define CONFIG_VIDEO
 437 #define CONFIG_CFB_CONSOLE
 438 #define CONFIG_VIDEO_SMI_LYNXEM
 439 #define CONFIG_VIDEO_LOGO
 440 /*#define CONFIG_VIDEO_BMP_LOGO*/
 441 #define CONFIG_CONSOLE_EXTRA_INFO
 442 #define CONFIG_VGA_AS_SINGLE_DEVICE
 443 /* This is the base address (on 405EP-side) used to generate I/O accesses on PCI bus */
 444 #define CONFIG_SYS_ISA_IO 0xE8000000
 445 /* see also drivers/video/videomodes.c */
 446 #define CONFIG_SYS_DEFAULT_VIDEO_MODE 0x303
 447 #endif
 448
 449 /*-----------------------------------------------------------------------
 450  * FPGA stuff
 451  */
 452 /* FPGA internal regs */
 453 #define CONFIG_SYS_FPGA_MODE            0x00
 454 #define CONFIG_SYS_FPGA_STATUS          0x02
 455 #define CONFIG_SYS_FPGA_TS              0x04
 456 #define CONFIG_SYS_FPGA_TS_LOW          0x06
 457 #define CONFIG_SYS_FPGA_TS_CAP0 0x10
 458 #define CONFIG_SYS_FPGA_TS_CAP0_LOW     0x12
 459 #define CONFIG_SYS_FPGA_TS_CAP1 0x14
 460 #define CONFIG_SYS_FPGA_TS_CAP1_LOW     0x16
 461 #define CONFIG_SYS_FPGA_TS_CAP2 0x18
 462 #define CONFIG_SYS_FPGA_TS_CAP2_LOW     0x1a
 463 #define CONFIG_SYS_FPGA_TS_CAP3 0x1c
 464 #define CONFIG_SYS_FPGA_TS_CAP3_LOW     0x1e
 465
 466 /* FPGA Mode Reg */
 467 #define CONFIG_SYS_FPGA_MODE_CF_RESET   0x0001
 468 #define CONFIG_SYS_FPGA_MODE_TS_IRQ_ENABLE 0x0100
 469 #define CONFIG_SYS_FPGA_MODE_TS_IRQ_CLEAR  0x1000
 470 #define CONFIG_SYS_FPGA_MODE_TS_CLEAR   0x2000
 471
 472 /* FPGA Status Reg */
 473 #define CONFIG_SYS_FPGA_STATUS_DIP0     0x0001
 474 #define CONFIG_SYS_FPGA_STATUS_DIP1     0x0002
 475 #define CONFIG_SYS_FPGA_STATUS_DIP2     0x0004
 476 #define CONFIG_SYS_FPGA_STATUS_FLASH    0x0008
 477 #define CONFIG_SYS_FPGA_STATUS_TS_IRQ   0x1000
 478
 479 #define CONFIG_SYS_FPGA_SPARTAN2        1               /* using Xilinx Spartan 2 now   */
 480 #define CONFIG_SYS_FPGA_MAX_SIZE        128*1024        /* 128kByte is enough for XC2S50E*/
 481
 482 /* FPGA program pin configuration */
 483 #define CONFIG_SYS_FPGA_PRG             0x04000000      /* FPGA program pin (ppc output) */
 484 #define CONFIG_SYS_FPGA_CLK             0x02000000      /* FPGA clk pin (ppc output)    */
 485 #define CONFIG_SYS_FPGA_DATA            0x01000000      /* FPGA data pin (ppc output)   */
 486 #define CONFIG_SYS_FPGA_INIT            0x00010000      /* FPGA init pin (ppc input)    */
 487 #define CONFIG_SYS_FPGA_DONE            0x00008000      /* FPGA done pin (ppc input)    */
 488
 489 /*-----------------------------------------------------------------------
 490  * Definitions for initial stack pointer and data area (in data cache)
 491  */
 492 /* use on chip memory ( OCM ) for temperary stack until sdram is tested */
 493 #define CONFIG_SYS_TEMP_STACK_OCM       1
 494
 495 /* On Chip Memory location */
 496 #define CONFIG_SYS_OCM_DATA_ADDR        0xF8000000
 497 #define CONFIG_SYS_OCM_DATA_SIZE        0x1000
 498 #define CONFIG_SYS_INIT_RAM_ADDR        CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM             */
 499 #define CONFIG_SYS_INIT_RAM_SIZE        CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM    */
 500
 501 #define CONFIG_SYS_GBL_DATA_OFFSET    (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 502 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 503
 504 /*-----------------------------------------------------------------------
 505  * Definitions for GPIO setup (PPC405EP specific)
 506  *
 507  * GPIO0[0]     - External Bus Controller BLAST output
 508  * GPIO0[1-9]   - Instruction trace outputs -> GPIO
 509  * GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs
 510  * GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs -> GPIO
 511  * GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs
 512  * GPIO0[24-27] - UART0 control signal inputs/outputs
 513  * GPIO0[28-29] - UART1 data signal input/output
 514  * GPIO0[30]    - EMAC0 input
 515  * GPIO0[31]    - EMAC1 reject packet as output
 516  */
 517 #define CONFIG_SYS_GPIO0_OSRL           0x40000550
 518 #define CONFIG_SYS_GPIO0_OSRH           0x00000110
 519 #define CONFIG_SYS_GPIO0_ISR1L          0x00000000
 520 /*#define CONFIG_SYS_GPIO0_ISR1H        0x15555445*/
 521 #define CONFIG_SYS_GPIO0_ISR1H          0x15555444
 522 #define CONFIG_SYS_GPIO0_TSRL           0x00000000
 523 #define CONFIG_SYS_GPIO0_TSRH           0x00000000
 524 #define CONFIG_SYS_GPIO0_TCR            0xF7FF8014
 525
 526 #define CONFIG_NO_SERIAL_EEPROM
 527
 528 /*--------------------------------------------------------------------*/
 529
 530 #ifdef CONFIG_NO_SERIAL_EEPROM
 531
 532 /*
 533 !-----------------------------------------------------------------------
 534 ! Defines for entry options.
 535 ! Note: Because the 405EP SDRAM controller does not support ECC, ECC DIMMs that
 536 !       are plugged in the board will be utilized as non-ECC DIMMs.
 537 !-----------------------------------------------------------------------
 538 */
 539 #undef          AUTO_MEMORY_CONFIG
 540 #define         DIMM_READ_ADDR 0xAB
 541 #define         DIMM_WRITE_ADDR 0xAA
 542
 543 /* Defines for CPC0_PLLMR1 Register fields */
 544 #define PLL_ACTIVE              0x80000000
 545 #define CPC0_PLLMR1_SSCS        0x80000000
 546 #define PLL_RESET               0x40000000
 547 #define CPC0_PLLMR1_PLLR        0x40000000
 548     /* Feedback multiplier */
 549 #define PLL_FBKDIV              0x00F00000
 550 #define CPC0_PLLMR1_FBDV        0x00F00000
 551 #define PLL_FBKDIV_16           0x00000000
 552 #define PLL_FBKDIV_1            0x00100000
 553 #define PLL_FBKDIV_2            0x00200000
 554 #define PLL_FBKDIV_3            0x00300000
 555 #define PLL_FBKDIV_4            0x00400000
 556 #define PLL_FBKDIV_5            0x00500000
 557 #define PLL_FBKDIV_6            0x00600000
 558 #define PLL_FBKDIV_7            0x00700000
 559 #define PLL_FBKDIV_8            0x00800000
 560 #define PLL_FBKDIV_9            0x00900000
 561 #define PLL_FBKDIV_10           0x00A00000
 562 #define PLL_FBKDIV_11           0x00B00000
 563 #define PLL_FBKDIV_12           0x00C00000
 564 #define PLL_FBKDIV_13           0x00D00000
 565 #define PLL_FBKDIV_14           0x00E00000
 566 #define PLL_FBKDIV_15           0x00F00000
 567     /* Forward A divisor */
 568 #define PLL_FWDDIVA             0x00070000
 569 #define CPC0_PLLMR1_FWDVA       0x00070000
 570 #define PLL_FWDDIVA_8           0x00000000
 571 #define PLL_FWDDIVA_7           0x00010000
 572 #define PLL_FWDDIVA_6           0x00020000
 573 #define PLL_FWDDIVA_5           0x00030000
 574 #define PLL_FWDDIVA_4           0x00040000
 575 #define PLL_FWDDIVA_3           0x00050000
 576 #define PLL_FWDDIVA_2           0x00060000
 577 #define PLL_FWDDIVA_1           0x00070000
 578     /* Forward B divisor */
 579 #define PLL_FWDDIVB             0x00007000
 580 #define CPC0_PLLMR1_FWDVB       0x00007000
 581 #define PLL_FWDDIVB_8           0x00000000
 582 #define PLL_FWDDIVB_7           0x00001000
 583 #define PLL_FWDDIVB_6           0x00002000
 584 #define PLL_FWDDIVB_5           0x00003000
 585 #define PLL_FWDDIVB_4           0x00004000
 586 #define PLL_FWDDIVB_3           0x00005000
 587 #define PLL_FWDDIVB_2           0x00006000
 588 #define PLL_FWDDIVB_1           0x00007000
 589     /* PLL tune bits */
 590 #define PLL_TUNE_MASK           0x000003FF
 591 #define PLL_TUNE_2_M_3          0x00000133      /*  2 <= M <= 3                 */
 592 #define PLL_TUNE_4_M_6          0x00000134      /*  3 <  M <= 6                 */
 593 #define PLL_TUNE_7_M_10         0x00000138      /*  6 <  M <= 10                */
 594 #define PLL_TUNE_11_M_14        0x0000013C      /* 10 <  M <= 14                */
 595 #define PLL_TUNE_15_M_40        0x0000023E      /* 14 <  M <= 40                */
 596 #define PLL_TUNE_VCO_LOW        0x00000000      /* 500MHz <= VCO <=  800MHz     */
 597 #define PLL_TUNE_VCO_HI         0x00000080      /* 800MHz <  VCO <= 1000MHz     */
 598
 599 /* Defines for CPC0_PLLMR0 Register fields */
 600     /* CPU divisor */
 601 #define PLL_CPUDIV              0x00300000
 602 #define CPC0_PLLMR0_CCDV        0x00300000
 603 #define PLL_CPUDIV_1            0x00000000
 604 #define PLL_CPUDIV_2            0x00100000
 605 #define PLL_CPUDIV_3            0x00200000
 606 #define PLL_CPUDIV_4            0x00300000
 607     /* PLB divisor */
 608 #define PLL_PLBDIV              0x00030000
 609 #define CPC0_PLLMR0_CBDV        0x00030000
 610 #define PLL_PLBDIV_1            0x00000000
 611 #define PLL_PLBDIV_2            0x00010000
 612 #define PLL_PLBDIV_3            0x00020000
 613 #define PLL_PLBDIV_4            0x00030000
 614     /* OPB divisor */
 615 #define PLL_OPBDIV              0x00003000
 616 #define CPC0_PLLMR0_OPDV        0x00003000
 617 #define PLL_OPBDIV_1            0x00000000
 618 #define PLL_OPBDIV_2            0x00001000
 619 #define PLL_OPBDIV_3            0x00002000
 620 #define PLL_OPBDIV_4            0x00003000
 621     /* EBC divisor */
 622 #define PLL_EXTBUSDIV           0x00000300
 623 #define CPC0_PLLMR0_EPDV        0x00000300
 624 #define PLL_EXTBUSDIV_2         0x00000000
 625 #define PLL_EXTBUSDIV_3         0x00000100
 626 #define PLL_EXTBUSDIV_4         0x00000200
 627 #define PLL_EXTBUSDIV_5         0x00000300
 628     /* MAL divisor */
 629 #define PLL_MALDIV              0x00000030
 630 #define CPC0_PLLMR0_MPDV        0x00000030
 631 #define PLL_MALDIV_1            0x00000000
 632 #define PLL_MALDIV_2            0x00000010
 633 #define PLL_MALDIV_3            0x00000020
 634 #define PLL_MALDIV_4            0x00000030
 635     /* PCI divisor */
 636 #define PLL_PCIDIV              0x00000003
 637 #define CPC0_PLLMR0_PPFD        0x00000003
 638 #define PLL_PCIDIV_1            0x00000000
 639 #define PLL_PCIDIV_2            0x00000001
 640 #define PLL_PCIDIV_3            0x00000002
 641 #define PLL_PCIDIV_4            0x00000003
 642
 643 #ifdef CONFIG_PPCHAMELEON_CLK_25
 644 /* CPU - PLB/SDRAM - EBC - OPB - PCI (assuming a 25.0 MHz input clock to the 405EP) */
 645 #define PPCHAMELEON_PLLMR0_133_133_33_66_33      (PLL_CPUDIV_1 | PLL_PLBDIV_1 |  \
 646                               PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 |  \
 647                               PLL_MALDIV_1 | PLL_PCIDIV_4)
 648 #define PPCHAMELEON_PLLMR1_133_133_33_66_33      (PLL_FBKDIV_8  |  \
 649                               PLL_FWDDIVA_6 | PLL_FWDDIVB_4 |  \
 650                               PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
 651
 652 #define PPCHAMELEON_PLLMR0_200_100_50_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 |  \
 653                               PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 |  \
 654                               PLL_MALDIV_1 | PLL_PCIDIV_4)
 655 #define PPCHAMELEON_PLLMR1_200_100_50_33 (PLL_FBKDIV_8  |  \
 656                               PLL_FWDDIVA_4 | PLL_FWDDIVB_4 |  \
 657                               PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
 658
 659 #define PPCHAMELEON_PLLMR0_266_133_33_66_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 |      \
 660                               PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 |  \
 661                               PLL_MALDIV_1 | PLL_PCIDIV_4)
 662 #define PPCHAMELEON_PLLMR1_266_133_33_66_33 (PLL_FBKDIV_8  |  \
 663                               PLL_FWDDIVA_3 | PLL_FWDDIVB_4 |  \
 664                               PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
 665
 666 #define PPCHAMELEON_PLLMR0_333_111_37_55_55 (PLL_CPUDIV_1 | PLL_PLBDIV_3 |      \
 667                               PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 |  \
 668                               PLL_MALDIV_1 | PLL_PCIDIV_2)
 669 #define PPCHAMELEON_PLLMR1_333_111_37_55_55 (PLL_FBKDIV_10      |  \
 670                               PLL_FWDDIVA_3 | PLL_FWDDIVB_4 |  \
 671                               PLL_TUNE_15_M_40 | PLL_TUNE_VCO_HI)
 672
 673 #elif (defined (CONFIG_PPCHAMELEON_CLK_33))
 674
 675 /* CPU - PLB/SDRAM - EBC - OPB - PCI (assuming a 33.3MHz input clock to the 405EP) */
 676 #define PPCHAMELEON_PLLMR0_133_133_33_66_33      (PLL_CPUDIV_1 | PLL_PLBDIV_1 |  \
 677                                   PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 |      \
 678                                   PLL_MALDIV_1 | PLL_PCIDIV_4)
 679 #define PPCHAMELEON_PLLMR1_133_133_33_66_33      (PLL_FBKDIV_4  |  \
 680                                   PLL_FWDDIVA_6 | PLL_FWDDIVB_6 |  \
 681                                   PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
 682
 683 #define PPCHAMELEON_PLLMR0_200_100_50_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 |  \
 684                                   PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 |      \
 685                                   PLL_MALDIV_1 | PLL_PCIDIV_4)
 686 #define PPCHAMELEON_PLLMR1_200_100_50_33 (PLL_FBKDIV_6  |  \
 687                                   PLL_FWDDIVA_4 | PLL_FWDDIVB_4 |  \
 688                                   PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
 689
 690 #define PPCHAMELEON_PLLMR0_266_133_33_66_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 |      \
 691                                   PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 |      \
 692                                   PLL_MALDIV_1 | PLL_PCIDIV_4)
 693 #define PPCHAMELEON_PLLMR1_266_133_33_66_33 (PLL_FBKDIV_8  |  \
 694                                   PLL_FWDDIVA_3 | PLL_FWDDIVB_3 |  \
 695                                   PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
 696
 697 #define PPCHAMELEON_PLLMR0_333_111_37_55_55 (PLL_CPUDIV_1 | PLL_PLBDIV_3 |      \
 698                                   PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 |      \
 699                                   PLL_MALDIV_1 | PLL_PCIDIV_2)
 700 #define PPCHAMELEON_PLLMR1_333_111_37_55_55 (PLL_FBKDIV_10      |  \
 701                                   PLL_FWDDIVA_3 | PLL_FWDDIVB_3 |  \
 702                                   PLL_TUNE_15_M_40 | PLL_TUNE_VCO_HI)
 703
 704 #else
 705 #error "* External frequency (SysClk) not defined! *"
 706 #endif
 707
 708 #if   (CONFIG_PPCHAMELEON_MODULE_MODEL == CONFIG_PPCHAMELEON_MODULE_HI)
 709 /* Model HI */
 710 #define PLLMR0_DEFAULT  PPCHAMELEON_PLLMR0_333_111_37_55_55
 711 #define PLLMR1_DEFAULT  PPCHAMELEON_PLLMR1_333_111_37_55_55
 712 #define CONFIG_SYS_OPB_FREQ     55555555
 713 /* Model ME */
 714 #elif (CONFIG_PPCHAMELEON_MODULE_MODEL == CONFIG_PPCHAMELEON_MODULE_ME)
 715 #define PLLMR0_DEFAULT  PPCHAMELEON_PLLMR0_266_133_33_66_33
 716 #define PLLMR1_DEFAULT  PPCHAMELEON_PLLMR1_266_133_33_66_33
 717 #define CONFIG_SYS_OPB_FREQ     66666666
 718 #else
 719 /* Model BA (default) */
 720 #define PLLMR0_DEFAULT  PPCHAMELEON_PLLMR0_133_133_33_66_33
 721 #define PLLMR1_DEFAULT  PPCHAMELEON_PLLMR1_133_133_33_66_33
 722 #define CONFIG_SYS_OPB_FREQ     66666666
 723 #endif
 724
 725 #endif /* CONFIG_NO_SERIAL_EEPROM */
 726
 727 #define CONFIG_JFFS2_NAND 1                     /* jffs2 on nand support */
 728 #define NAND_CACHE_PAGES 16                     /* size of nand cache in 512 bytes pages */
 729
 730 /*
 731  * JFFS2 partitions
 732  *
 733  */
 734 /* No command line, one static partition */
 735 #undef CONFIG_CMD_MTDPARTS
 736 #define CONFIG_JFFS2_DEV                "nand"
 737 #define CONFIG_JFFS2_PART_SIZE          0x00200000
 738 #define CONFIG_JFFS2_PART_OFFSET        0x00000000
 739
 740 /* mtdparts command line support
 741  *
 742  * Note: fake mtd_id used, no linux mtd map file
 743  */
 744 /*
 745 #define CONFIG_CMD_MTDPARTS
 746 #define MTDIDS_DEFAULT          "nand0=catcenter"
 747 #define MTDPARTS_DEFAULT        "mtdparts=catcenter:2m(nand)"
 748 */
 749
 750 #endif  /* __CONFIG_H */