2 * Copyright 2013 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
8 * C29XPCIE board configuration file
14 #define CONFIG_DISPLAY_BOARDINFO
16 #ifdef CONFIG_C29XPCIE
17 #define CONFIG_PPC_C29X
20 #ifdef CONFIG_SPIFLASH
21 #define CONFIG_RAMBOOT_SPIFLASH
22 #define CONFIG_SYS_TEXT_BASE 0x11000000
23 #define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc
27 #ifdef CONFIG_TPL_BUILD
28 #define CONFIG_SPL_NAND_BOOT
29 #define CONFIG_SPL_FLUSH_IMAGE
30 #define CONFIG_SPL_NAND_INIT
31 #define CONFIG_TPL_SERIAL_SUPPORT
32 #define CONFIG_TPL_DRIVERS_MISC_SUPPORT
33 #define CONFIG_SPL_COMMON_INIT_DDR
34 #define CONFIG_SPL_MAX_SIZE (128 << 10)
35 #define CONFIG_SPL_TEXT_BASE 0xf8f81000
36 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
37 #define CONFIG_SYS_NAND_U_BOOT_SIZE (832 << 10)
38 #define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000)
39 #define CONFIG_SYS_NAND_U_BOOT_START (0x11000000)
40 #define CONFIG_SYS_NAND_U_BOOT_OFFS ((128 + 128) << 10)
41 #elif defined(CONFIG_SPL_BUILD)
42 #define CONFIG_SPL_INIT_MINIMAL
43 #define CONFIG_SPL_SERIAL_SUPPORT
44 #define CONFIG_SPL_NAND_MINIMAL
45 #define CONFIG_SPL_FLUSH_IMAGE
46 #define CONFIG_SPL_TEXT_BASE 0xff800000
47 #define CONFIG_SPL_MAX_SIZE 8192
48 #define CONFIG_SYS_NAND_U_BOOT_SIZE (128 << 10)
49 #define CONFIG_SYS_NAND_U_BOOT_DST 0xf8f80000
50 #define CONFIG_SYS_NAND_U_BOOT_START 0xf8f80000
51 #define CONFIG_SYS_NAND_U_BOOT_OFFS (128 << 10)
53 #define CONFIG_SPL_PAD_TO 0x20000
54 #define CONFIG_TPL_PAD_TO 0x20000
55 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
56 #define CONFIG_SYS_TEXT_BASE 0x11001000
57 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
60 #ifndef CONFIG_SYS_TEXT_BASE
61 #define CONFIG_SYS_TEXT_BASE 0xeff40000
64 #ifndef CONFIG_RESET_VECTOR_ADDRESS
65 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
68 #ifdef CONFIG_SPL_BUILD
69 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
71 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
74 #ifdef CONFIG_SPL_BUILD
75 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
78 /* High Level Configuration Options */
79 #define CONFIG_BOOKE /* BOOKE */
80 #define CONFIG_E500 /* BOOKE e500 family */
81 #define CONFIG_FSL_IFC /* Enable IFC Support */
82 #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */
83 #define CONFIG_SYS_HAS_SERDES /* common SERDES init code */
85 #define CONFIG_PCI /* Enable PCI/PCIE */
87 #define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */
88 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
89 #define CONFIG_PCI_INDIRECT_BRIDGE
90 #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */
91 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
93 #define CONFIG_CMD_PCI
97 * Memory space is mapped 1-1, but I/O space must start from 0.
99 /* controller 1, Slot 1, tgtid 1, Base address a000 */
100 #define CONFIG_SYS_PCIE1_NAME "Slot 1"
101 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
102 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
103 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
104 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */
105 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000
106 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
107 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
108 #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc00000ull
110 #define CONFIG_PCI_PNP /* do pci plug-and-play */
112 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
113 #define CONFIG_DOS_PARTITION
116 #define CONFIG_FSL_LAW /* Use common FSL init code */
117 #define CONFIG_TSEC_ENET
118 #define CONFIG_ENV_OVERWRITE
120 #define CONFIG_DDR_CLK_FREQ 100000000
121 #define CONFIG_SYS_CLK_FREQ 66666666
123 #define CONFIG_HWCONFIG
126 * These can be toggled for performance analysis, otherwise use default.
128 #define CONFIG_L2_CACHE /* toggle L2 cache */
129 #define CONFIG_BTB /* toggle branch predition */
131 #define CONFIG_ADDR_STREAMING /* toggle addr streaming */
133 #define CONFIG_ENABLE_36BIT_PHYS
135 #define CONFIG_ADDR_MAP 1
136 #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */
138 #define CONFIG_SYS_MEMTEST_START 0x00200000
139 #define CONFIG_SYS_MEMTEST_END 0x00400000
140 #define CONFIG_PANIC_HANG
143 #define CONFIG_SYS_FSL_DDR3
144 #define CONFIG_DDR_SPD
145 #define CONFIG_SYS_SPD_BUS_NUM 0
146 #define SPD_EEPROM_ADDRESS 0x50
147 #define CONFIG_SYS_DDR_RAW_TIMING
150 #define CONFIG_DDR_ECC
151 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef
152 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
154 #define CONFIG_SYS_SDRAM_SIZE 512
155 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
156 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
158 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
159 #define CONFIG_CHIP_SELECTS_PER_CTRL 1
161 #define CONFIG_SYS_CCSRBAR 0xffe00000
162 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
164 /* Platform SRAM setting */
165 #define CONFIG_SYS_PLATFORM_SRAM_BASE 0xffb00000
166 #define CONFIG_SYS_PLATFORM_SRAM_BASE_PHYS \
167 (0xf00000000ull | CONFIG_SYS_PLATFORM_SRAM_BASE)
168 #define CONFIG_SYS_PLATFORM_SRAM_SIZE (512 << 10)
170 #ifdef CONFIG_SPL_BUILD
171 #define CONFIG_SYS_NO_FLASH
177 /* NOR Flash on IFC */
178 #define CONFIG_SYS_FLASH_BASE 0xec000000
179 #define CONFIG_SYS_MAX_FLASH_SECT 512 /* 64M */
181 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
183 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE_PHYS }
184 #define CONFIG_SYS_MAX_FLASH_BANKS 1
186 #define CONFIG_SYS_FLASH_QUIET_TEST
187 #define CONFIG_FLASH_SHOW_PROGRESS 45
188 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* in ms */
189 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* in ms */
191 /* 16Bit NOR Flash - S29GL512S10TFI01 */
192 #define CONFIG_SYS_NOR_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
193 CSPR_PORT_SIZE_16 | \
196 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(64*1024*1024)
197 #define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(4)
199 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
200 FTIM0_NOR_TEADC(0x5) | \
201 FTIM0_NOR_TEAHC(0x5))
202 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
203 FTIM1_NOR_TRAD_NOR(0x1A) |\
204 FTIM1_NOR_TSEQRAD_NOR(0x13))
205 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
206 FTIM2_NOR_TCH(0x4) | \
207 FTIM2_NOR_TWPH(0x0E) | \
209 #define CONFIG_SYS_NOR_FTIM3 0x0
211 /* CFI for NOR Flash */
212 #define CONFIG_FLASH_CFI_DRIVER
213 #define CONFIG_SYS_FLASH_CFI
214 #define CONFIG_SYS_FLASH_EMPTY_INFO
215 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
217 /* NAND Flash on IFC */
218 #define CONFIG_NAND_FSL_IFC
219 #define CONFIG_SYS_NAND_BASE 0xff800000
220 #define CONFIG_SYS_NAND_BASE_PHYS 0xfff800000ull
222 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
224 #define CONFIG_SYS_MAX_NAND_DEVICE 1
225 #define CONFIG_CMD_NAND
226 #define CONFIG_SYS_NAND_BLOCK_SIZE (1024 * 1024)
228 /* 8Bit NAND Flash - K9F1G08U0B */
229 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
233 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
234 #define CONFIG_SYS_NAND_OOBSIZE 0x00000280 /* 640b */
235 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
236 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
237 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
238 | CSOR_NAND_RAL_3 /* RAL = 3 Bytes */ \
239 | CSOR_NAND_PGS_8K /* Page Size = 8K */ \
240 | CSOR_NAND_SPRZ_CSOR_EXT /*oob in csor_ext*/\
241 | CSOR_NAND_PB(128)) /*128 Pages Per Block*/
242 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x01) | \
243 FTIM0_NAND_TWP(0x0c) | \
244 FTIM0_NAND_TWCHT(0x08) | \
245 FTIM0_NAND_TWH(0x06))
246 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x28) | \
247 FTIM1_NAND_TWBE(0x1d) | \
248 FTIM1_NAND_TRR(0x08) | \
249 FTIM1_NAND_TRP(0x0c))
250 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0c) | \
251 FTIM2_NAND_TREH(0x0a) | \
252 FTIM2_NAND_TWHRE(0x18))
253 #define CONFIG_SYS_NAND_FTIM3 (FTIM3_NAND_TWW(0x04))
255 #define CONFIG_SYS_NAND_DDR_LAW 11
257 /* Set up IFC registers for boot location NOR/NAND */
259 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
260 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
261 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
262 #define CONFIG_SYS_CSOR0_EXT CONFIG_SYS_NAND_OOBSIZE
263 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
264 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
265 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
266 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
267 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR_CSPR
268 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
269 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
270 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
271 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
272 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
273 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
275 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR
276 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
277 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
278 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
279 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
280 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
281 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
282 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR
283 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK
284 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR
285 #define CONFIG_SYS_CSOR1_EXT CONFIG_SYS_NAND_OOBSIZE
286 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0
287 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1
288 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2
289 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3
292 /* CPLD on IFC, selected by CS2 */
293 #define CONFIG_SYS_CPLD_BASE 0xffdf0000
294 #define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull \
295 | CONFIG_SYS_CPLD_BASE)
297 #define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \
301 #define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024)
302 #define CONFIG_SYS_CSOR2 0x0
303 /* CPLD Timing parameters for IFC CS2 */
304 #define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
305 FTIM0_GPCM_TEADC(0x0e) | \
306 FTIM0_GPCM_TEAHC(0x0e))
307 #define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \
308 FTIM1_GPCM_TRAD(0x1f))
309 #define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
310 FTIM2_GPCM_TCH(0x8) | \
311 FTIM2_GPCM_TWP(0x1f))
312 #define CONFIG_SYS_CS2_FTIM3 0x0
314 #if defined(CONFIG_RAMBOOT_SPIFLASH)
315 #define CONFIG_SYS_RAMBOOT
316 #define CONFIG_SYS_EXTRA_ENV_RELOC
319 #define CONFIG_BOARD_EARLY_INIT_R
321 #define CONFIG_SYS_INIT_RAM_LOCK
322 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000
323 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
325 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE \
326 - GENERATED_GBL_DATA_SIZE)
327 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
329 #define CONFIG_SYS_MONITOR_LEN (768 * 1024)
330 #define CONFIG_SYS_MALLOC_LEN (2 * 1024 * 1024)
333 * Config the L2 Cache as L2 SRAM
335 #if defined(CONFIG_SPL_BUILD)
336 #if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH)
337 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
338 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
339 #define CONFIG_SYS_L2_SIZE (256 << 10)
340 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
341 #define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000
342 #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 128 * 1024)
343 #define CONFIG_SPL_RELOC_STACK_SIZE (32 << 10)
344 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 160 * 1024)
345 #define CONFIG_SPL_RELOC_MALLOC_SIZE (96 << 10)
346 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 112 * 1024)
347 #elif defined(CONFIG_NAND)
348 #ifdef CONFIG_TPL_BUILD
349 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
350 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
351 #define CONFIG_SYS_L2_SIZE (256 << 10)
352 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
353 #define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000
354 #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 192 * 1024)
355 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 208 * 1024)
356 #define CONFIG_SPL_RELOC_MALLOC_SIZE (48 << 10)
357 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 176 * 1024)
359 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
360 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
361 #define CONFIG_SYS_L2_SIZE (256 << 10)
362 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
363 #define CONFIG_SPL_RELOC_TEXT_BASE (CONFIG_SYS_INIT_L2_END - 0x3000)
364 #define CONFIG_SPL_RELOC_STACK ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
370 #define CONFIG_CONS_INDEX 1
371 #define CONFIG_SYS_NS16550_SERIAL
372 #define CONFIG_SYS_NS16550_REG_SIZE 1
373 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
375 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL)
376 #define CONFIG_NS16550_MIN_FUNCTIONS
379 #define CONFIG_SYS_CONSOLE_IS_IN_ENV
381 #define CONFIG_SYS_BAUDRATE_TABLE \
382 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
384 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
385 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
387 #define CONFIG_SYS_I2C
388 #define CONFIG_SYS_I2C_FSL
389 #define CONFIG_SYS_FSL_I2C_SPEED 400000
390 #define CONFIG_SYS_FSL_I2C2_SPEED 400000
391 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
392 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
393 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
394 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
397 /* enable read and write access to EEPROM */
398 #define CONFIG_CMD_EEPROM
399 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
400 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
401 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
403 /* eSPI - Enhanced SPI */
404 #define CONFIG_SF_DEFAULT_SPEED 10000000
405 #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
407 #ifdef CONFIG_TSEC_ENET
408 #define CONFIG_MII /* MII PHY management */
409 #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */
410 #define CONFIG_TSEC1 1
411 #define CONFIG_TSEC1_NAME "eTSEC1"
412 #define CONFIG_TSEC2 1
413 #define CONFIG_TSEC2_NAME "eTSEC2"
415 /* Default mode is RGMII mode */
416 #define TSEC1_PHY_ADDR 0
417 #define TSEC2_PHY_ADDR 2
419 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
420 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
422 #define CONFIG_ETHPRIME "eTSEC1"
424 #define CONFIG_PHY_GIGE
425 #endif /* CONFIG_TSEC_ENET */
430 #if defined(CONFIG_SYS_RAMBOOT)
431 #if defined(CONFIG_RAMBOOT_SPIFLASH)
432 #define CONFIG_ENV_IS_IN_SPI_FLASH
433 #define CONFIG_ENV_SPI_BUS 0
434 #define CONFIG_ENV_SPI_CS 0
435 #define CONFIG_ENV_SPI_MAX_HZ 10000000
436 #define CONFIG_ENV_SPI_MODE 0
437 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
438 #define CONFIG_ENV_SECT_SIZE 0x10000
439 #define CONFIG_ENV_SIZE 0x2000
441 #elif defined(CONFIG_NAND)
442 #define CONFIG_ENV_IS_IN_NAND
443 #ifdef CONFIG_TPL_BUILD
444 #define CONFIG_ENV_SIZE 0x2000
445 #define CONFIG_ENV_ADDR (CONFIG_SYS_INIT_L2_ADDR + (160 << 10))
447 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
448 #define CONFIG_ENV_RANGE CONFIG_ENV_SIZE
450 #define CONFIG_ENV_OFFSET CONFIG_SYS_NAND_BLOCK_SIZE
452 #define CONFIG_ENV_IS_IN_FLASH
453 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
454 #define CONFIG_ENV_SIZE 0x2000
455 #define CONFIG_ENV_SECT_SIZE 0x20000
458 #define CONFIG_LOADS_ECHO
459 #define CONFIG_SYS_LOADS_BAUD_CHANGE
462 * Command line configuration.
464 #define CONFIG_CMD_ERRATA
465 #define CONFIG_CMD_IRQ
466 #define CONFIG_CMD_REGINFO
468 /* Hash command with SHA acceleration supported in hardware */
469 #ifdef CONFIG_FSL_CAAM
470 #define CONFIG_CMD_HASH
471 #define CONFIG_SHA_HW_ACCEL
475 * Miscellaneous configurable options
477 #define CONFIG_SYS_LONGHELP /* undef to save memory */
478 #define CONFIG_CMDLINE_EDITING /* Command-line editing */
479 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */
480 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
482 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
483 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
484 /* Print Buffer Size */
485 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
486 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
489 * For booting Linux, the board info and command line data
490 * have to be in the first 64 MB of memory, since this is
491 * the maximum mapped by the Linux kernel during initialization.
493 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux */
494 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
497 * Environment Configuration
500 #ifdef CONFIG_TSEC_ENET
501 #define CONFIG_HAS_ETH0
502 #define CONFIG_HAS_ETH1
505 #define CONFIG_ROOTPATH "/opt/nfsroot"
506 #define CONFIG_BOOTFILE "uImage"
507 #define CONFIG_UBOOTPATH u-boot.bin/* U-Boot image on TFTP server */
509 /* default location for tftp and bootm */
510 #define CONFIG_LOADADDR 1000000
513 #define CONFIG_BAUDRATE 115200
515 #define CONFIG_DEF_HWCONFIG fsl_ddr:ecc=on
517 #define CONFIG_EXTRA_ENV_SETTINGS \
518 "hwconfig=" __stringify(CONFIG_DEF_HWCONFIG) "\0" \
520 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
521 "loadaddr=1000000\0" \
522 "consoledev=ttyS0\0" \
523 "ramdiskaddr=2000000\0" \
524 "ramdiskfile=rootfs.ext2.gz.uboot\0" \
525 "fdtaddr=1e00000\0" \
526 "fdtfile=name/of/device-tree.dtb\0" \
527 "othbootargs=ramdisk_size=600000\0" \
529 #define CONFIG_RAMBOOTCOMMAND \
530 "setenv bootargs root=/dev/ram rw " \
531 "console=$consoledev,$baudrate $othbootargs; " \
532 "tftp $ramdiskaddr $ramdiskfile;" \
533 "tftp $loadaddr $bootfile;" \
534 "tftp $fdtaddr $fdtfile;" \
535 "bootm $loadaddr $ramdiskaddr $fdtaddr"
537 #define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND
539 #include <asm/fsl_secure_boot.h>
541 #endif /* __CONFIG_H */