include/configs/C29XPCIE.h

   1 /*
   2  * Copyright 2013 Freescale Semiconductor, Inc.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 /*
   8  * C29XPCIE board configuration file
   9  */
  10
  11 #ifndef __CONFIG_H
  12 #define __CONFIG_H
  13
  14 #define CONFIG_DISPLAY_BOARDINFO
  15
  16 #ifdef CONFIG_C29XPCIE
  17 #define CONFIG_PPC_C29X
  18 #endif
  19
  20 #ifdef CONFIG_SPIFLASH
  21 #define CONFIG_RAMBOOT_SPIFLASH
  22 #define CONFIG_SYS_TEXT_BASE            0x11000000
  23 #define CONFIG_RESET_VECTOR_ADDRESS     0x110bfffc
  24 #endif
  25
  26 #ifdef CONFIG_NAND
  27 #ifdef CONFIG_TPL_BUILD
  28 #define CONFIG_SPL_NAND_BOOT
  29 #define CONFIG_SPL_FLUSH_IMAGE
  30 #define CONFIG_SPL_NAND_INIT
  31 #define CONFIG_TPL_SERIAL_SUPPORT
  32 #define CONFIG_TPL_LIBGENERIC_SUPPORT
  33 #define CONFIG_TPL_LIBCOMMON_SUPPORT
  34 #define CONFIG_TPL_DRIVERS_MISC_SUPPORT
  35 #define CONFIG_TPL_NAND_SUPPORT
  36 #define CONFIG_TPL_MPC8XXX_INIT_DDR_SUPPORT
  37 #define CONFIG_SPL_COMMON_INIT_DDR
  38 #define CONFIG_SPL_MAX_SIZE             (128 << 10)
  39 #define CONFIG_SPL_TEXT_BASE            0xf8f81000
  40 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  41 #define CONFIG_SYS_NAND_U_BOOT_SIZE     (832 << 10)
  42 #define CONFIG_SYS_NAND_U_BOOT_DST      (0x11000000)
  43 #define CONFIG_SYS_NAND_U_BOOT_START    (0x11000000)
  44 #define CONFIG_SYS_NAND_U_BOOT_OFFS     ((128 + 128) << 10)
  45 #elif defined(CONFIG_SPL_BUILD)
  46 #define CONFIG_SPL_INIT_MINIMAL
  47 #define CONFIG_SPL_SERIAL_SUPPORT
  48 #define CONFIG_SPL_NAND_SUPPORT
  49 #define CONFIG_SPL_NAND_MINIMAL
  50 #define CONFIG_SPL_FLUSH_IMAGE
  51 #define CONFIG_SPL_TEXT_BASE            0xff800000
  52 #define CONFIG_SPL_MAX_SIZE             8192
  53 #define CONFIG_SYS_NAND_U_BOOT_SIZE     (128 << 10)
  54 #define CONFIG_SYS_NAND_U_BOOT_DST      0xf8f80000
  55 #define CONFIG_SYS_NAND_U_BOOT_START    0xf8f80000
  56 #define CONFIG_SYS_NAND_U_BOOT_OFFS     (128 << 10)
  57 #endif
  58 #define CONFIG_SPL_PAD_TO               0x20000
  59 #define CONFIG_TPL_PAD_TO               0x20000
  60 #define CONFIG_SPL_TARGET               "u-boot-with-spl.bin"
  61 #define CONFIG_SYS_TEXT_BASE            0x11001000
  62 #define CONFIG_SYS_LDSCRIPT     "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
  63 #endif
  64
  65 #ifndef CONFIG_SYS_TEXT_BASE
  66 #define CONFIG_SYS_TEXT_BASE            0xeff40000
  67 #endif
  68
  69 #ifndef CONFIG_RESET_VECTOR_ADDRESS
  70 #define CONFIG_RESET_VECTOR_ADDRESS     0xeffffffc
  71 #endif
  72
  73 #ifdef CONFIG_SPL_BUILD
  74 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
  75 #else
  76 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
  77 #endif
  78
  79 #ifdef CONFIG_SPL_BUILD
  80 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
  81 #endif
  82
  83 /* High Level Configuration Options */
  84 #define CONFIG_BOOKE                    /* BOOKE */
  85 #define CONFIG_E500                     /* BOOKE e500 family */
  86 #define CONFIG_FSL_IFC                  /* Enable IFC Support */
  87 #define CONFIG_FSL_CAAM                 /* Enable SEC/CAAM */
  88 #define CONFIG_SYS_HAS_SERDES           /* common SERDES init code */
  89
  90 #define CONFIG_PCI                      /* Enable PCI/PCIE */
  91 #ifdef CONFIG_PCI
  92 #define CONFIG_PCIE1                    /* PCIE controller 1 (slot 1) */
  93 #define CONFIG_FSL_PCI_INIT             /* Use common FSL init code */
  94 #define CONFIG_PCI_INDIRECT_BRIDGE
  95 #define CONFIG_FSL_PCIE_RESET           /* need PCIe reset errata */
  96 #define CONFIG_SYS_PCI_64BIT            /* enable 64-bit PCI resources */
  97
  98 #define CONFIG_CMD_PCI
  99
 100 /*
 101  * PCI Windows
 102  * Memory space is mapped 1-1, but I/O space must start from 0.
 103  */
 104 /* controller 1, Slot 1, tgtid 1, Base address a000 */
 105 #define CONFIG_SYS_PCIE1_NAME           "Slot 1"
 106 #define CONFIG_SYS_PCIE1_MEM_VIRT       0x80000000
 107 #define CONFIG_SYS_PCIE1_MEM_BUS        0x80000000
 108 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc00000000ull
 109 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x10000000      /* 256M */
 110 #define CONFIG_SYS_PCIE1_IO_VIRT        0xffc00000
 111 #define CONFIG_SYS_PCIE1_IO_BUS         0x00000000
 112 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00010000      /* 64k */
 113 #define CONFIG_SYS_PCIE1_IO_PHYS        0xfffc00000ull
 114
 115 #define CONFIG_PCI_PNP                  /* do pci plug-and-play */
 116
 117 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
 118 #define CONFIG_DOS_PARTITION
 119 #endif
 120
 121 #define CONFIG_FSL_LAW                  /* Use common FSL init code */
 122 #define CONFIG_TSEC_ENET
 123 #define CONFIG_ENV_OVERWRITE
 124
 125 #define CONFIG_DDR_CLK_FREQ     100000000
 126 #define CONFIG_SYS_CLK_FREQ     66666666
 127
 128 #define CONFIG_HWCONFIG
 129
 130 /*
 131  * These can be toggled for performance analysis, otherwise use default.
 132  */
 133 #define CONFIG_L2_CACHE                 /* toggle L2 cache */
 134 #define CONFIG_BTB                      /* toggle branch predition */
 135
 136 #define CONFIG_ADDR_STREAMING           /* toggle addr streaming */
 137
 138 #define CONFIG_ENABLE_36BIT_PHYS
 139
 140 #define CONFIG_ADDR_MAP                 1
 141 #define CONFIG_SYS_NUM_ADDR_MAP         16      /* number of TLB1 entries */
 142
 143 #define CONFIG_SYS_MEMTEST_START        0x00200000
 144 #define CONFIG_SYS_MEMTEST_END          0x00400000
 145 #define CONFIG_PANIC_HANG
 146
 147 /* DDR Setup */
 148 #define CONFIG_SYS_FSL_DDR3
 149 #define CONFIG_DDR_SPD
 150 #define CONFIG_SYS_SPD_BUS_NUM          0
 151 #define SPD_EEPROM_ADDRESS              0x50
 152 #define CONFIG_SYS_DDR_RAW_TIMING
 153
 154 /* DDR ECC Setup*/
 155 #define CONFIG_DDR_ECC
 156 #define CONFIG_MEM_INIT_VALUE           0xDeadBeef
 157 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
 158
 159 #define CONFIG_SYS_SDRAM_SIZE           512
 160 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
 161 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
 162
 163 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
 164 #define CONFIG_CHIP_SELECTS_PER_CTRL    1
 165
 166 #define CONFIG_SYS_CCSRBAR              0xffe00000
 167 #define CONFIG_SYS_CCSRBAR_PHYS_LOW     CONFIG_SYS_CCSRBAR
 168
 169 /* Platform SRAM setting  */
 170 #define CONFIG_SYS_PLATFORM_SRAM_BASE   0xffb00000
 171 #define CONFIG_SYS_PLATFORM_SRAM_BASE_PHYS \
 172                         (0xf00000000ull | CONFIG_SYS_PLATFORM_SRAM_BASE)
 173 #define CONFIG_SYS_PLATFORM_SRAM_SIZE   (512 << 10)
 174
 175 #ifdef CONFIG_SPL_BUILD
 176 #define CONFIG_SYS_NO_FLASH
 177 #endif
 178
 179 /*
 180  * IFC Definitions
 181  */
 182 /* NOR Flash on IFC */
 183 #define CONFIG_SYS_FLASH_BASE           0xec000000
 184 #define CONFIG_SYS_MAX_FLASH_SECT       512     /* 64M */
 185
 186 #define CONFIG_SYS_FLASH_BASE_PHYS      (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
 187
 188 #define CONFIG_SYS_FLASH_BANKS_LIST     { CONFIG_SYS_FLASH_BASE_PHYS }
 189 #define CONFIG_SYS_MAX_FLASH_BANKS      1
 190
 191 #define CONFIG_SYS_FLASH_QUIET_TEST
 192 #define CONFIG_FLASH_SHOW_PROGRESS      45
 193 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* in ms */
 194 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* in ms */
 195
 196 /* 16Bit NOR Flash - S29GL512S10TFI01 */
 197 #define CONFIG_SYS_NOR_CSPR     (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
 198                                 CSPR_PORT_SIZE_16 | \
 199                                 CSPR_MSEL_NOR | \
 200                                 CSPR_V)
 201 #define CONFIG_SYS_NOR_AMASK    IFC_AMASK(64*1024*1024)
 202 #define CONFIG_SYS_NOR_CSOR     CSOR_NOR_ADM_SHIFT(4)
 203
 204 #define CONFIG_SYS_NOR_FTIM0    (FTIM0_NOR_TACSE(0x4) | \
 205                                 FTIM0_NOR_TEADC(0x5) | \
 206                                 FTIM0_NOR_TEAHC(0x5))
 207 #define CONFIG_SYS_NOR_FTIM1    (FTIM1_NOR_TACO(0x35) | \
 208                                 FTIM1_NOR_TRAD_NOR(0x1A) |\
 209                                 FTIM1_NOR_TSEQRAD_NOR(0x13))
 210 #define CONFIG_SYS_NOR_FTIM2    (FTIM2_NOR_TCS(0x4) | \
 211                                 FTIM2_NOR_TCH(0x4) | \
 212                                 FTIM2_NOR_TWPH(0x0E) | \
 213                                 FTIM2_NOR_TWP(0x1c))
 214 #define CONFIG_SYS_NOR_FTIM3    0x0
 215
 216 /* CFI for NOR Flash */
 217 #define CONFIG_FLASH_CFI_DRIVER
 218 #define CONFIG_SYS_FLASH_CFI
 219 #define CONFIG_SYS_FLASH_EMPTY_INFO
 220 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
 221
 222 /* NAND Flash on IFC */
 223 #define CONFIG_NAND_FSL_IFC
 224 #define CONFIG_SYS_NAND_BASE            0xff800000
 225 #define CONFIG_SYS_NAND_BASE_PHYS       0xfff800000ull
 226
 227 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
 228
 229 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 230 #define CONFIG_CMD_NAND
 231 #define CONFIG_SYS_NAND_BLOCK_SIZE      (1024 * 1024)
 232
 233 /* 8Bit NAND Flash - K9F1G08U0B */
 234 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 235                                 | CSPR_PORT_SIZE_8 \
 236                                 | CSPR_MSEL_NAND \
 237                                 | CSPR_V)
 238 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64*1024)
 239 #define CONFIG_SYS_NAND_OOBSIZE 0x00000280      /* 640b */
 240 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 241                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 242                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
 243                                 | CSOR_NAND_RAL_3       /* RAL = 3 Bytes */ \
 244                                 | CSOR_NAND_PGS_8K      /* Page Size = 8K */ \
 245                                 | CSOR_NAND_SPRZ_CSOR_EXT /*oob in csor_ext*/\
 246                                 | CSOR_NAND_PB(128))    /*128 Pages Per Block*/
 247 #define CONFIG_SYS_NAND_FTIM0   (FTIM0_NAND_TCCST(0x01) | \
 248                                 FTIM0_NAND_TWP(0x0c)   | \
 249                                 FTIM0_NAND_TWCHT(0x08) | \
 250                                 FTIM0_NAND_TWH(0x06))
 251 #define CONFIG_SYS_NAND_FTIM1   (FTIM1_NAND_TADLE(0x28) | \
 252                                 FTIM1_NAND_TWBE(0x1d)  | \
 253                                 FTIM1_NAND_TRR(0x08)   | \
 254                                 FTIM1_NAND_TRP(0x0c))
 255 #define CONFIG_SYS_NAND_FTIM2   (FTIM2_NAND_TRAD(0x0c) | \
 256                                 FTIM2_NAND_TREH(0x0a) | \
 257                                 FTIM2_NAND_TWHRE(0x18))
 258 #define CONFIG_SYS_NAND_FTIM3   (FTIM3_NAND_TWW(0x04))
 259
 260 #define CONFIG_SYS_NAND_DDR_LAW         11
 261
 262 /* Set up IFC registers for boot location NOR/NAND */
 263 #ifdef CONFIG_NAND
 264 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
 265 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
 266 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
 267 #define CONFIG_SYS_CSOR0_EXT            CONFIG_SYS_NAND_OOBSIZE
 268 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
 269 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
 270 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
 271 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
 272 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR_CSPR
 273 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
 274 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 275 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 276 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 277 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 278 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 279 #else
 280 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR_CSPR
 281 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
 282 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
 283 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
 284 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
 285 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
 286 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
 287 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NAND_CSPR
 288 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NAND_AMASK
 289 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NAND_CSOR
 290 #define CONFIG_SYS_CSOR1_EXT            CONFIG_SYS_NAND_OOBSIZE
 291 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NAND_FTIM0
 292 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NAND_FTIM1
 293 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NAND_FTIM2
 294 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NAND_FTIM3
 295 #endif
 296
 297 /* CPLD on IFC, selected by CS2 */
 298 #define CONFIG_SYS_CPLD_BASE            0xffdf0000
 299 #define CONFIG_SYS_CPLD_BASE_PHYS       (0xf00000000ull \
 300                                         | CONFIG_SYS_CPLD_BASE)
 301
 302 #define CONFIG_SYS_CSPR2        (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \
 303                                 | CSPR_PORT_SIZE_8 \
 304                                 | CSPR_MSEL_GPCM \
 305                                 | CSPR_V)
 306 #define CONFIG_SYS_AMASK2       IFC_AMASK(64*1024)
 307 #define CONFIG_SYS_CSOR2        0x0
 308 /* CPLD Timing parameters for IFC CS2 */
 309 #define CONFIG_SYS_CS2_FTIM0    (FTIM0_GPCM_TACSE(0x0e) | \
 310                                 FTIM0_GPCM_TEADC(0x0e) | \
 311                                 FTIM0_GPCM_TEAHC(0x0e))
 312 #define CONFIG_SYS_CS2_FTIM1    (FTIM1_GPCM_TACO(0x0e) | \
 313                                 FTIM1_GPCM_TRAD(0x1f))
 314 #define CONFIG_SYS_CS2_FTIM2    (FTIM2_GPCM_TCS(0x0e) | \
 315                                 FTIM2_GPCM_TCH(0x8) | \
 316                                 FTIM2_GPCM_TWP(0x1f))
 317 #define CONFIG_SYS_CS2_FTIM3    0x0
 318
 319 #if defined(CONFIG_RAMBOOT_SPIFLASH)
 320 #define CONFIG_SYS_RAMBOOT
 321 #define CONFIG_SYS_EXTRA_ENV_RELOC
 322 #endif
 323
 324 #define CONFIG_BOARD_EARLY_INIT_R
 325
 326 #define CONFIG_SYS_INIT_RAM_LOCK
 327 #define CONFIG_SYS_INIT_RAM_ADDR        0xffd00000
 328 #define CONFIG_SYS_INIT_RAM_SIZE        0x00004000
 329
 330 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE \
 331                                                 - GENERATED_GBL_DATA_SIZE)
 332 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 333
 334 #define CONFIG_SYS_MONITOR_LEN          (768 * 1024)
 335 #define CONFIG_SYS_MALLOC_LEN           (2 * 1024 * 1024)
 336
 337 /*
 338  * Config the L2 Cache as L2 SRAM
 339  */
 340 #if defined(CONFIG_SPL_BUILD)
 341 #if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH)
 342 #define CONFIG_SYS_INIT_L2_ADDR         0xf8f80000
 343 #define CONFIG_SYS_INIT_L2_ADDR_PHYS    CONFIG_SYS_INIT_L2_ADDR
 344 #define CONFIG_SYS_L2_SIZE              (256 << 10)
 345 #define CONFIG_SYS_INIT_L2_END  (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
 346 #define CONFIG_SPL_RELOC_TEXT_BASE      0xf8f81000
 347 #define CONFIG_SPL_RELOC_STACK          (CONFIG_SYS_INIT_L2_ADDR + 128 * 1024)
 348 #define CONFIG_SPL_RELOC_STACK_SIZE     (32 << 10)
 349 #define CONFIG_SPL_RELOC_MALLOC_ADDR    (CONFIG_SYS_INIT_L2_ADDR + 160 * 1024)
 350 #define CONFIG_SPL_RELOC_MALLOC_SIZE    (96 << 10)
 351 #define CONFIG_SPL_GD_ADDR              (CONFIG_SYS_INIT_L2_ADDR + 112 * 1024)
 352 #elif defined(CONFIG_NAND)
 353 #ifdef CONFIG_TPL_BUILD
 354 #define CONFIG_SYS_INIT_L2_ADDR         0xf8f80000
 355 #define CONFIG_SYS_INIT_L2_ADDR_PHYS    CONFIG_SYS_INIT_L2_ADDR
 356 #define CONFIG_SYS_L2_SIZE              (256 << 10)
 357 #define CONFIG_SYS_INIT_L2_END  (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
 358 #define CONFIG_SPL_RELOC_TEXT_BASE      0xf8f81000
 359 #define CONFIG_SPL_RELOC_STACK          (CONFIG_SYS_INIT_L2_ADDR + 192 * 1024)
 360 #define CONFIG_SPL_RELOC_MALLOC_ADDR    (CONFIG_SYS_INIT_L2_ADDR + 208 * 1024)
 361 #define CONFIG_SPL_RELOC_MALLOC_SIZE    (48 << 10)
 362 #define CONFIG_SPL_GD_ADDR              (CONFIG_SYS_INIT_L2_ADDR + 176 * 1024)
 363 #else
 364 #define CONFIG_SYS_INIT_L2_ADDR         0xf8f80000
 365 #define CONFIG_SYS_INIT_L2_ADDR_PHYS    CONFIG_SYS_INIT_L2_ADDR
 366 #define CONFIG_SYS_L2_SIZE              (256 << 10)
 367 #define CONFIG_SYS_INIT_L2_END  (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
 368 #define CONFIG_SPL_RELOC_TEXT_BASE      (CONFIG_SYS_INIT_L2_END - 0x3000)
 369 #define CONFIG_SPL_RELOC_STACK          ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
 370 #endif
 371 #endif
 372 #endif
 373
 374 /* Serial Port */
 375 #define CONFIG_CONS_INDEX       1
 376 #define CONFIG_SYS_NS16550_SERIAL
 377 #define CONFIG_SYS_NS16550_REG_SIZE     1
 378 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 379
 380 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL)
 381 #define CONFIG_NS16550_MIN_FUNCTIONS
 382 #endif
 383
 384 #define CONFIG_SYS_CONSOLE_IS_IN_ENV
 385
 386 #define CONFIG_SYS_BAUDRATE_TABLE       \
 387         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 388
 389 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
 390 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
 391
 392 #define CONFIG_SYS_I2C
 393 #define CONFIG_SYS_I2C_FSL
 394 #define CONFIG_SYS_FSL_I2C_SPEED        400000
 395 #define CONFIG_SYS_FSL_I2C2_SPEED       400000
 396 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 397 #define CONFIG_SYS_FSL_I2C2_SLAVE       0x7F
 398 #define CONFIG_SYS_FSL_I2C_OFFSET       0x3000
 399 #define CONFIG_SYS_FSL_I2C2_OFFSET      0x3100
 400
 401 /* I2C EEPROM */
 402 /* enable read and write access to EEPROM */
 403 #define CONFIG_CMD_EEPROM
 404 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
 405 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
 406 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
 407
 408 /* eSPI - Enhanced SPI */
 409 #define CONFIG_SF_DEFAULT_SPEED         10000000
 410 #define CONFIG_SF_DEFAULT_MODE          SPI_MODE_0
 411
 412 #ifdef CONFIG_TSEC_ENET
 413 #define CONFIG_MII                      /* MII PHY management */
 414 #define CONFIG_MII_DEFAULT_TSEC 1       /* Allow unregistered phys */
 415 #define CONFIG_TSEC1            1
 416 #define CONFIG_TSEC1_NAME       "eTSEC1"
 417 #define CONFIG_TSEC2            1
 418 #define CONFIG_TSEC2_NAME       "eTSEC2"
 419
 420 /* Default mode is RGMII mode */
 421 #define TSEC1_PHY_ADDR          0
 422 #define TSEC2_PHY_ADDR          2
 423
 424 #define TSEC1_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
 425 #define TSEC2_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
 426
 427 #define CONFIG_ETHPRIME         "eTSEC1"
 428
 429 #define CONFIG_PHY_GIGE
 430 #endif  /* CONFIG_TSEC_ENET */
 431
 432 /*
 433  * Environment
 434  */
 435 #if defined(CONFIG_SYS_RAMBOOT)
 436 #if defined(CONFIG_RAMBOOT_SPIFLASH)
 437 #define CONFIG_ENV_IS_IN_SPI_FLASH
 438 #define CONFIG_ENV_SPI_BUS      0
 439 #define CONFIG_ENV_SPI_CS       0
 440 #define CONFIG_ENV_SPI_MAX_HZ   10000000
 441 #define CONFIG_ENV_SPI_MODE     0
 442 #define CONFIG_ENV_OFFSET       0x100000        /* 1MB */
 443 #define CONFIG_ENV_SECT_SIZE    0x10000
 444 #define CONFIG_ENV_SIZE         0x2000
 445 #endif
 446 #elif defined(CONFIG_NAND)
 447 #define CONFIG_ENV_IS_IN_NAND
 448 #ifdef CONFIG_TPL_BUILD
 449 #define CONFIG_ENV_SIZE         0x2000
 450 #define CONFIG_ENV_ADDR         (CONFIG_SYS_INIT_L2_ADDR + (160 << 10))
 451 #else
 452 #define CONFIG_ENV_SIZE         CONFIG_SYS_NAND_BLOCK_SIZE
 453 #define CONFIG_ENV_RANGE        CONFIG_ENV_SIZE
 454 #endif
 455 #define CONFIG_ENV_OFFSET       CONFIG_SYS_NAND_BLOCK_SIZE
 456 #else
 457 #define CONFIG_ENV_IS_IN_FLASH
 458 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
 459 #define CONFIG_ENV_SIZE         0x2000
 460 #define CONFIG_ENV_SECT_SIZE    0x20000
 461 #endif
 462
 463 #define CONFIG_LOADS_ECHO
 464 #define CONFIG_SYS_LOADS_BAUD_CHANGE
 465
 466 /*
 467  * Command line configuration.
 468  */
 469 #define CONFIG_CMD_ERRATA
 470 #define CONFIG_CMD_IRQ
 471 #define CONFIG_CMD_REGINFO
 472
 473 /* Hash command with SHA acceleration supported in hardware */
 474 #ifdef CONFIG_FSL_CAAM
 475 #define CONFIG_CMD_HASH
 476 #define CONFIG_SHA_HW_ACCEL
 477 #endif
 478
 479 /*
 480  * Miscellaneous configurable options
 481  */
 482 #define CONFIG_SYS_LONGHELP                     /* undef to save memory */
 483 #define CONFIG_CMDLINE_EDITING                  /* Command-line editing */
 484 #define CONFIG_AUTO_COMPLETE                    /* add autocompletion support */
 485 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 486
 487 #define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size */
 488 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
 489                                                 /* Print Buffer Size */
 490 #define CONFIG_SYS_MAXARGS      16              /* max number of command args */
 491 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
 492
 493 /*
 494  * For booting Linux, the board info and command line data
 495  * have to be in the first 64 MB of memory, since this is
 496  * the maximum mapped by the Linux kernel during initialization.
 497  */
 498 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20) /* Initial Memory map for Linux */
 499 #define CONFIG_SYS_BOOTM_LEN    (64 << 20) /* Increase max gunzip size */
 500
 501 /*
 502  * Environment Configuration
 503  */
 504
 505 #ifdef CONFIG_TSEC_ENET
 506 #define CONFIG_HAS_ETH0
 507 #define CONFIG_HAS_ETH1
 508 #endif
 509
 510 #define CONFIG_ROOTPATH         "/opt/nfsroot"
 511 #define CONFIG_BOOTFILE         "uImage"
 512 #define CONFIG_UBOOTPATH        u-boot.bin/* U-Boot image on TFTP server */
 513
 514 /* default location for tftp and bootm */
 515 #define CONFIG_LOADADDR         1000000
 516
 517
 518 #define CONFIG_BAUDRATE         115200
 519
 520 #define CONFIG_DEF_HWCONFIG     fsl_ddr:ecc=on
 521
 522 #define CONFIG_EXTRA_ENV_SETTINGS                               \
 523         "hwconfig=" __stringify(CONFIG_DEF_HWCONFIG)  "\0"      \
 524         "netdev=eth0\0"                                         \
 525         "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"             \
 526         "loadaddr=1000000\0"                            \
 527         "consoledev=ttyS0\0"                            \
 528         "ramdiskaddr=2000000\0"                         \
 529         "ramdiskfile=rootfs.ext2.gz.uboot\0"            \
 530         "fdtaddr=1e00000\0"                             \
 531         "fdtfile=name/of/device-tree.dtb\0"                     \
 532         "othbootargs=ramdisk_size=600000\0"             \
 533
 534 #define CONFIG_RAMBOOTCOMMAND                   \
 535         "setenv bootargs root=/dev/ram rw "     \
 536         "console=$consoledev,$baudrate $othbootargs; "  \
 537         "tftp $ramdiskaddr $ramdiskfile;"       \
 538         "tftp $loadaddr $bootfile;"             \
 539         "tftp $fdtaddr $fdtfile;"               \
 540         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 541
 542 #define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND
 543
 544 #include <asm/fsl_secure_boot.h>
 545
 546 #endif  /* __CONFIG_H */