1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2013 Freescale Semiconductor, Inc.
7 * C29XPCIE board configuration file
13 #ifdef CONFIG_SPIFLASH
14 #define CONFIG_RAMBOOT_SPIFLASH
15 #define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc
19 #ifdef CONFIG_TPL_BUILD
20 #define CONFIG_SPL_NAND_BOOT
21 #define CONFIG_SPL_FLUSH_IMAGE
22 #define CONFIG_SPL_NAND_INIT
23 #define CONFIG_TPL_DRIVERS_MISC_SUPPORT
24 #define CONFIG_SPL_COMMON_INIT_DDR
25 #define CONFIG_SPL_MAX_SIZE (128 << 10)
26 #define CONFIG_TPL_TEXT_BASE 0xf8f81000
27 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
28 #define CONFIG_SYS_NAND_U_BOOT_SIZE (832 << 10)
29 #define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000)
30 #define CONFIG_SYS_NAND_U_BOOT_START (0x11000000)
31 #define CONFIG_SYS_NAND_U_BOOT_OFFS ((128 + 128) << 10)
32 #elif defined(CONFIG_SPL_BUILD)
33 #define CONFIG_SPL_INIT_MINIMAL
34 #define CONFIG_SPL_NAND_MINIMAL
35 #define CONFIG_SPL_FLUSH_IMAGE
36 #define CONFIG_SPL_TEXT_BASE 0xff800000
37 #define CONFIG_SPL_MAX_SIZE 8192
38 #define CONFIG_SYS_NAND_U_BOOT_SIZE (128 << 10)
39 #define CONFIG_SYS_NAND_U_BOOT_DST 0xf8f80000
40 #define CONFIG_SYS_NAND_U_BOOT_START 0xf8f80000
41 #define CONFIG_SYS_NAND_U_BOOT_OFFS (128 << 10)
43 #define CONFIG_SPL_PAD_TO 0x20000
44 #define CONFIG_TPL_PAD_TO 0x20000
45 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
46 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
49 #ifndef CONFIG_RESET_VECTOR_ADDRESS
50 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
53 #ifdef CONFIG_TPL_BUILD
54 #define CONFIG_SYS_MONITOR_BASE CONFIG_TPL_TEXT_BASE
55 #elif defined(CONFIG_SPL_BUILD)
56 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
58 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
61 #ifdef CONFIG_SPL_BUILD
62 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
65 /* High Level Configuration Options */
66 #define CONFIG_SYS_HAS_SERDES /* common SERDES init code */
69 #define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */
70 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
71 #define CONFIG_PCI_INDIRECT_BRIDGE
72 #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */
73 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
77 * Memory space is mapped 1-1, but I/O space must start from 0.
79 /* controller 1, Slot 1, tgtid 1, Base address a000 */
80 #define CONFIG_SYS_PCIE1_NAME "Slot 1"
81 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
82 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
83 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
84 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */
85 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000
86 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
87 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
88 #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc00000ull
90 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
93 #define CONFIG_ENV_OVERWRITE
95 #define CONFIG_DDR_CLK_FREQ 100000000
96 #define CONFIG_SYS_CLK_FREQ 66666666
98 #define CONFIG_HWCONFIG
101 * These can be toggled for performance analysis, otherwise use default.
103 #define CONFIG_L2_CACHE /* toggle L2 cache */
104 #define CONFIG_BTB /* toggle branch predition */
107 #define CONFIG_ENABLE_36BIT_PHYS
109 #define CONFIG_ADDR_MAP 1
110 #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */
112 #define CONFIG_SYS_MEMTEST_START 0x00200000
113 #define CONFIG_SYS_MEMTEST_END 0x00400000
116 #define CONFIG_DDR_SPD
117 #define CONFIG_SYS_SPD_BUS_NUM 0
118 #define SPD_EEPROM_ADDRESS 0x50
119 #define CONFIG_SYS_DDR_RAW_TIMING
122 #define CONFIG_DDR_ECC
123 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef
124 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
126 #define CONFIG_SYS_SDRAM_SIZE 512
127 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
128 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
130 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
131 #define CONFIG_CHIP_SELECTS_PER_CTRL 1
133 #define CONFIG_SYS_CCSRBAR 0xffe00000
134 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
136 /* Platform SRAM setting */
137 #define CONFIG_SYS_PLATFORM_SRAM_BASE 0xffb00000
138 #define CONFIG_SYS_PLATFORM_SRAM_BASE_PHYS \
139 (0xf00000000ull | CONFIG_SYS_PLATFORM_SRAM_BASE)
140 #define CONFIG_SYS_PLATFORM_SRAM_SIZE (512 << 10)
145 /* NOR Flash on IFC */
146 #define CONFIG_SYS_FLASH_BASE 0xec000000
147 #define CONFIG_SYS_MAX_FLASH_SECT 512 /* 64M */
149 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
151 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE_PHYS }
152 #define CONFIG_SYS_MAX_FLASH_BANKS 1
154 #define CONFIG_SYS_FLASH_QUIET_TEST
155 #define CONFIG_FLASH_SHOW_PROGRESS 45
156 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* in ms */
157 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* in ms */
159 /* 16Bit NOR Flash - S29GL512S10TFI01 */
160 #define CONFIG_SYS_NOR_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
161 CSPR_PORT_SIZE_16 | \
164 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(64*1024*1024)
165 #define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(4)
167 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
168 FTIM0_NOR_TEADC(0x5) | \
169 FTIM0_NOR_TEAHC(0x5))
170 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
171 FTIM1_NOR_TRAD_NOR(0x1A) |\
172 FTIM1_NOR_TSEQRAD_NOR(0x13))
173 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
174 FTIM2_NOR_TCH(0x4) | \
175 FTIM2_NOR_TWPH(0x0E) | \
177 #define CONFIG_SYS_NOR_FTIM3 0x0
179 /* CFI for NOR Flash */
180 #define CONFIG_SYS_FLASH_EMPTY_INFO
182 /* NAND Flash on IFC */
183 #define CONFIG_NAND_FSL_IFC
184 #define CONFIG_SYS_NAND_BASE 0xff800000
185 #define CONFIG_SYS_NAND_BASE_PHYS 0xfff800000ull
187 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
189 #define CONFIG_SYS_MAX_NAND_DEVICE 1
190 #define CONFIG_SYS_NAND_BLOCK_SIZE (1024 * 1024)
192 /* 8Bit NAND Flash - K9F1G08U0B */
193 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
197 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
198 #define CONFIG_SYS_NAND_OOBSIZE 0x00000280 /* 640b */
199 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
200 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
201 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
202 | CSOR_NAND_RAL_3 /* RAL = 3 Bytes */ \
203 | CSOR_NAND_PGS_8K /* Page Size = 8K */ \
204 | CSOR_NAND_SPRZ_CSOR_EXT /*oob in csor_ext*/\
205 | CSOR_NAND_PB(128)) /*128 Pages Per Block*/
206 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x01) | \
207 FTIM0_NAND_TWP(0x0c) | \
208 FTIM0_NAND_TWCHT(0x08) | \
209 FTIM0_NAND_TWH(0x06))
210 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x28) | \
211 FTIM1_NAND_TWBE(0x1d) | \
212 FTIM1_NAND_TRR(0x08) | \
213 FTIM1_NAND_TRP(0x0c))
214 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0c) | \
215 FTIM2_NAND_TREH(0x0a) | \
216 FTIM2_NAND_TWHRE(0x18))
217 #define CONFIG_SYS_NAND_FTIM3 (FTIM3_NAND_TWW(0x04))
219 #define CONFIG_SYS_NAND_DDR_LAW 11
221 /* Set up IFC registers for boot location NOR/NAND */
223 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
224 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
225 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
226 #define CONFIG_SYS_CSOR0_EXT CONFIG_SYS_NAND_OOBSIZE
227 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
228 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
229 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
230 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
231 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR_CSPR
232 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
233 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
234 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
235 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
236 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
237 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
239 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR
240 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
241 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
242 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
243 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
244 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
245 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
246 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR
247 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK
248 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR
249 #define CONFIG_SYS_CSOR1_EXT CONFIG_SYS_NAND_OOBSIZE
250 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0
251 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1
252 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2
253 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3
256 /* CPLD on IFC, selected by CS2 */
257 #define CONFIG_SYS_CPLD_BASE 0xffdf0000
258 #define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull \
259 | CONFIG_SYS_CPLD_BASE)
261 #define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \
265 #define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024)
266 #define CONFIG_SYS_CSOR2 0x0
267 /* CPLD Timing parameters for IFC CS2 */
268 #define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
269 FTIM0_GPCM_TEADC(0x0e) | \
270 FTIM0_GPCM_TEAHC(0x0e))
271 #define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \
272 FTIM1_GPCM_TRAD(0x1f))
273 #define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
274 FTIM2_GPCM_TCH(0x8) | \
275 FTIM2_GPCM_TWP(0x1f))
276 #define CONFIG_SYS_CS2_FTIM3 0x0
278 #if defined(CONFIG_RAMBOOT_SPIFLASH)
279 #define CONFIG_SYS_RAMBOOT
282 #define CONFIG_SYS_INIT_RAM_LOCK
283 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000
284 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
286 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE \
287 - GENERATED_GBL_DATA_SIZE)
288 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
290 #define CONFIG_SYS_MONITOR_LEN (768 * 1024)
291 #define CONFIG_SYS_MALLOC_LEN (2 * 1024 * 1024)
294 * Config the L2 Cache as L2 SRAM
296 #if defined(CONFIG_SPL_BUILD)
297 #if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH)
298 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
299 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
300 #define CONFIG_SYS_L2_SIZE (256 << 10)
301 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
302 #define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000
303 #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 128 * 1024)
304 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 160 * 1024)
305 #define CONFIG_SPL_RELOC_MALLOC_SIZE (96 << 10)
306 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 112 * 1024)
307 #elif defined(CONFIG_NAND)
308 #ifdef CONFIG_TPL_BUILD
309 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
310 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
311 #define CONFIG_SYS_L2_SIZE (256 << 10)
312 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
313 #define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000
314 #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 192 * 1024)
315 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 208 * 1024)
316 #define CONFIG_SPL_RELOC_MALLOC_SIZE (48 << 10)
317 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 176 * 1024)
319 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
320 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
321 #define CONFIG_SYS_L2_SIZE (256 << 10)
322 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
323 #define CONFIG_SPL_RELOC_TEXT_BASE (CONFIG_SYS_INIT_L2_END - 0x3000)
324 #define CONFIG_SPL_RELOC_STACK ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
330 #define CONFIG_SYS_NS16550_SERIAL
331 #define CONFIG_SYS_NS16550_REG_SIZE 1
332 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
334 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL)
335 #define CONFIG_NS16550_MIN_FUNCTIONS
338 #define CONFIG_SYS_BAUDRATE_TABLE \
339 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
341 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
342 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
344 #define CONFIG_SYS_I2C
345 #define CONFIG_SYS_I2C_FSL
346 #define CONFIG_SYS_FSL_I2C_SPEED 400000
347 #define CONFIG_SYS_FSL_I2C2_SPEED 400000
348 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
349 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
350 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
351 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
354 /* enable read and write access to EEPROM */
355 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
356 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
357 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
359 /* eSPI - Enhanced SPI */
360 #define CONFIG_SF_DEFAULT_SPEED 10000000
361 #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
363 #ifdef CONFIG_TSEC_ENET
364 #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */
365 #define CONFIG_TSEC1 1
366 #define CONFIG_TSEC1_NAME "eTSEC1"
367 #define CONFIG_TSEC2 1
368 #define CONFIG_TSEC2_NAME "eTSEC2"
370 /* Default mode is RGMII mode */
371 #define TSEC1_PHY_ADDR 0
372 #define TSEC2_PHY_ADDR 2
374 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
375 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
377 #define CONFIG_ETHPRIME "eTSEC1"
378 #endif /* CONFIG_TSEC_ENET */
383 #if defined(CONFIG_SYS_RAMBOOT)
384 #if defined(CONFIG_RAMBOOT_SPIFLASH)
385 #define CONFIG_ENV_SPI_BUS 0
386 #define CONFIG_ENV_SPI_CS 0
387 #define CONFIG_ENV_SPI_MAX_HZ 10000000
388 #define CONFIG_ENV_SPI_MODE 0
389 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
390 #define CONFIG_ENV_SECT_SIZE 0x10000
391 #define CONFIG_ENV_SIZE 0x2000
393 #elif defined(CONFIG_NAND)
394 #ifdef CONFIG_TPL_BUILD
395 #define CONFIG_ENV_SIZE 0x2000
396 #define CONFIG_ENV_ADDR (CONFIG_SYS_INIT_L2_ADDR + (160 << 10))
398 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
399 #define CONFIG_ENV_RANGE CONFIG_ENV_SIZE
401 #define CONFIG_ENV_OFFSET CONFIG_SYS_NAND_BLOCK_SIZE
403 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
404 #define CONFIG_ENV_SIZE 0x2000
405 #define CONFIG_ENV_SECT_SIZE 0x20000
408 #define CONFIG_LOADS_ECHO
409 #define CONFIG_SYS_LOADS_BAUD_CHANGE
412 * Miscellaneous configurable options
414 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
417 * For booting Linux, the board info and command line data
418 * have to be in the first 64 MB of memory, since this is
419 * the maximum mapped by the Linux kernel during initialization.
421 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux */
422 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
425 * Environment Configuration
428 #ifdef CONFIG_TSEC_ENET
429 #define CONFIG_HAS_ETH0
430 #define CONFIG_HAS_ETH1
433 #define CONFIG_ROOTPATH "/opt/nfsroot"
434 #define CONFIG_BOOTFILE "uImage"
435 #define CONFIG_UBOOTPATH u-boot.bin/* U-Boot image on TFTP server */
437 /* default location for tftp and bootm */
438 #define CONFIG_LOADADDR 1000000
440 #define CONFIG_DEF_HWCONFIG fsl_ddr:ecc=on
442 #define CONFIG_EXTRA_ENV_SETTINGS \
443 "hwconfig=" __stringify(CONFIG_DEF_HWCONFIG) "\0" \
445 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
446 "loadaddr=1000000\0" \
447 "consoledev=ttyS0\0" \
448 "ramdiskaddr=2000000\0" \
449 "ramdiskfile=rootfs.ext2.gz.uboot\0" \
450 "fdtaddr=1e00000\0" \
451 "fdtfile=name/of/device-tree.dtb\0" \
452 "othbootargs=ramdisk_size=600000\0" \
454 #define CONFIG_RAMBOOTCOMMAND \
455 "setenv bootargs root=/dev/ram rw " \
456 "console=$consoledev,$baudrate $othbootargs; " \
457 "tftp $ramdiskaddr $ramdiskfile;" \
458 "tftp $loadaddr $bootfile;" \
459 "tftp $fdtaddr $fdtfile;" \
460 "bootm $loadaddr $ramdiskaddr $fdtaddr"
462 #define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND
464 #include <asm/fsl_secure_boot.h>
466 #endif /* __CONFIG_H */