include/configs/C29XPCIE.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2013 Freescale Semiconductor, Inc.
   4  */
   5
   6 /*
   7  * C29XPCIE board configuration file
   8  */
   9
  10 #ifndef __CONFIG_H
  11 #define __CONFIG_H
  12
  13 #ifdef CONFIG_SPIFLASH
  14 #define CONFIG_RAMBOOT_SPIFLASH
  15 #define CONFIG_RESET_VECTOR_ADDRESS     0x110bfffc
  16 #endif
  17
  18 #ifdef CONFIG_NAND
  19 #ifdef CONFIG_TPL_BUILD
  20 #define CONFIG_SPL_NAND_BOOT
  21 #define CONFIG_SPL_FLUSH_IMAGE
  22 #define CONFIG_SPL_NAND_INIT
  23 #define CONFIG_TPL_DRIVERS_MISC_SUPPORT
  24 #define CONFIG_SPL_COMMON_INIT_DDR
  25 #define CONFIG_SPL_MAX_SIZE             (128 << 10)
  26 #define CONFIG_SPL_TEXT_BASE            0xf8f81000
  27 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  28 #define CONFIG_SYS_NAND_U_BOOT_SIZE     (832 << 10)
  29 #define CONFIG_SYS_NAND_U_BOOT_DST      (0x11000000)
  30 #define CONFIG_SYS_NAND_U_BOOT_START    (0x11000000)
  31 #define CONFIG_SYS_NAND_U_BOOT_OFFS     ((128 + 128) << 10)
  32 #elif defined(CONFIG_SPL_BUILD)
  33 #define CONFIG_SPL_INIT_MINIMAL
  34 #define CONFIG_SPL_NAND_MINIMAL
  35 #define CONFIG_SPL_FLUSH_IMAGE
  36 #define CONFIG_SPL_TEXT_BASE            0xff800000
  37 #define CONFIG_SPL_MAX_SIZE             8192
  38 #define CONFIG_SYS_NAND_U_BOOT_SIZE     (128 << 10)
  39 #define CONFIG_SYS_NAND_U_BOOT_DST      0xf8f80000
  40 #define CONFIG_SYS_NAND_U_BOOT_START    0xf8f80000
  41 #define CONFIG_SYS_NAND_U_BOOT_OFFS     (128 << 10)
  42 #endif
  43 #define CONFIG_SPL_PAD_TO               0x20000
  44 #define CONFIG_TPL_PAD_TO               0x20000
  45 #define CONFIG_SPL_TARGET               "u-boot-with-spl.bin"
  46 #define CONFIG_SYS_LDSCRIPT     "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
  47 #endif
  48
  49 #ifndef CONFIG_RESET_VECTOR_ADDRESS
  50 #define CONFIG_RESET_VECTOR_ADDRESS     0xeffffffc
  51 #endif
  52
  53 #ifdef CONFIG_SPL_BUILD
  54 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
  55 #else
  56 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
  57 #endif
  58
  59 #ifdef CONFIG_SPL_BUILD
  60 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
  61 #endif
  62
  63 /* High Level Configuration Options */
  64 #define CONFIG_SYS_HAS_SERDES           /* common SERDES init code */
  65
  66 #ifdef CONFIG_PCI
  67 #define CONFIG_PCIE1                    /* PCIE controller 1 (slot 1) */
  68 #define CONFIG_FSL_PCI_INIT             /* Use common FSL init code */
  69 #define CONFIG_PCI_INDIRECT_BRIDGE
  70 #define CONFIG_FSL_PCIE_RESET           /* need PCIe reset errata */
  71 #define CONFIG_SYS_PCI_64BIT            /* enable 64-bit PCI resources */
  72
  73 /*
  74  * PCI Windows
  75  * Memory space is mapped 1-1, but I/O space must start from 0.
  76  */
  77 /* controller 1, Slot 1, tgtid 1, Base address a000 */
  78 #define CONFIG_SYS_PCIE1_NAME           "Slot 1"
  79 #define CONFIG_SYS_PCIE1_MEM_VIRT       0x80000000
  80 #define CONFIG_SYS_PCIE1_MEM_BUS        0x80000000
  81 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc00000000ull
  82 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x10000000      /* 256M */
  83 #define CONFIG_SYS_PCIE1_IO_VIRT        0xffc00000
  84 #define CONFIG_SYS_PCIE1_IO_BUS         0x00000000
  85 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00010000      /* 64k */
  86 #define CONFIG_SYS_PCIE1_IO_PHYS        0xfffc00000ull
  87
  88 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
  89 #endif
  90
  91 #define CONFIG_ENV_OVERWRITE
  92
  93 #define CONFIG_DDR_CLK_FREQ     100000000
  94 #define CONFIG_SYS_CLK_FREQ     66666666
  95
  96 #define CONFIG_HWCONFIG
  97
  98 /*
  99  * These can be toggled for performance analysis, otherwise use default.
 100  */
 101 #define CONFIG_L2_CACHE                 /* toggle L2 cache */
 102 #define CONFIG_BTB                      /* toggle branch predition */
 103
 104
 105 #define CONFIG_ENABLE_36BIT_PHYS
 106
 107 #define CONFIG_ADDR_MAP                 1
 108 #define CONFIG_SYS_NUM_ADDR_MAP         16      /* number of TLB1 entries */
 109
 110 #define CONFIG_SYS_MEMTEST_START        0x00200000
 111 #define CONFIG_SYS_MEMTEST_END          0x00400000
 112
 113 /* DDR Setup */
 114 #define CONFIG_DDR_SPD
 115 #define CONFIG_SYS_SPD_BUS_NUM          0
 116 #define SPD_EEPROM_ADDRESS              0x50
 117 #define CONFIG_SYS_DDR_RAW_TIMING
 118
 119 /* DDR ECC Setup*/
 120 #define CONFIG_DDR_ECC
 121 #define CONFIG_MEM_INIT_VALUE           0xDeadBeef
 122 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
 123
 124 #define CONFIG_SYS_SDRAM_SIZE           512
 125 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
 126 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
 127
 128 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
 129 #define CONFIG_CHIP_SELECTS_PER_CTRL    1
 130
 131 #define CONFIG_SYS_CCSRBAR              0xffe00000
 132 #define CONFIG_SYS_CCSRBAR_PHYS_LOW     CONFIG_SYS_CCSRBAR
 133
 134 /* Platform SRAM setting  */
 135 #define CONFIG_SYS_PLATFORM_SRAM_BASE   0xffb00000
 136 #define CONFIG_SYS_PLATFORM_SRAM_BASE_PHYS \
 137                         (0xf00000000ull | CONFIG_SYS_PLATFORM_SRAM_BASE)
 138 #define CONFIG_SYS_PLATFORM_SRAM_SIZE   (512 << 10)
 139
 140 /*
 141  * IFC Definitions
 142  */
 143 /* NOR Flash on IFC */
 144 #define CONFIG_SYS_FLASH_BASE           0xec000000
 145 #define CONFIG_SYS_MAX_FLASH_SECT       512     /* 64M */
 146
 147 #define CONFIG_SYS_FLASH_BASE_PHYS      (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
 148
 149 #define CONFIG_SYS_FLASH_BANKS_LIST     { CONFIG_SYS_FLASH_BASE_PHYS }
 150 #define CONFIG_SYS_MAX_FLASH_BANKS      1
 151
 152 #define CONFIG_SYS_FLASH_QUIET_TEST
 153 #define CONFIG_FLASH_SHOW_PROGRESS      45
 154 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* in ms */
 155 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* in ms */
 156
 157 /* 16Bit NOR Flash - S29GL512S10TFI01 */
 158 #define CONFIG_SYS_NOR_CSPR     (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
 159                                 CSPR_PORT_SIZE_16 | \
 160                                 CSPR_MSEL_NOR | \
 161                                 CSPR_V)
 162 #define CONFIG_SYS_NOR_AMASK    IFC_AMASK(64*1024*1024)
 163 #define CONFIG_SYS_NOR_CSOR     CSOR_NOR_ADM_SHIFT(4)
 164
 165 #define CONFIG_SYS_NOR_FTIM0    (FTIM0_NOR_TACSE(0x4) | \
 166                                 FTIM0_NOR_TEADC(0x5) | \
 167                                 FTIM0_NOR_TEAHC(0x5))
 168 #define CONFIG_SYS_NOR_FTIM1    (FTIM1_NOR_TACO(0x35) | \
 169                                 FTIM1_NOR_TRAD_NOR(0x1A) |\
 170                                 FTIM1_NOR_TSEQRAD_NOR(0x13))
 171 #define CONFIG_SYS_NOR_FTIM2    (FTIM2_NOR_TCS(0x4) | \
 172                                 FTIM2_NOR_TCH(0x4) | \
 173                                 FTIM2_NOR_TWPH(0x0E) | \
 174                                 FTIM2_NOR_TWP(0x1c))
 175 #define CONFIG_SYS_NOR_FTIM3    0x0
 176
 177 /* CFI for NOR Flash */
 178 #define CONFIG_SYS_FLASH_EMPTY_INFO
 179
 180 /* NAND Flash on IFC */
 181 #define CONFIG_NAND_FSL_IFC
 182 #define CONFIG_SYS_NAND_BASE            0xff800000
 183 #define CONFIG_SYS_NAND_BASE_PHYS       0xfff800000ull
 184
 185 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
 186
 187 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 188 #define CONFIG_SYS_NAND_BLOCK_SIZE      (1024 * 1024)
 189
 190 /* 8Bit NAND Flash - K9F1G08U0B */
 191 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 192                                 | CSPR_PORT_SIZE_8 \
 193                                 | CSPR_MSEL_NAND \
 194                                 | CSPR_V)
 195 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64*1024)
 196 #define CONFIG_SYS_NAND_OOBSIZE 0x00000280      /* 640b */
 197 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 198                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 199                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
 200                                 | CSOR_NAND_RAL_3       /* RAL = 3 Bytes */ \
 201                                 | CSOR_NAND_PGS_8K      /* Page Size = 8K */ \
 202                                 | CSOR_NAND_SPRZ_CSOR_EXT /*oob in csor_ext*/\
 203                                 | CSOR_NAND_PB(128))    /*128 Pages Per Block*/
 204 #define CONFIG_SYS_NAND_FTIM0   (FTIM0_NAND_TCCST(0x01) | \
 205                                 FTIM0_NAND_TWP(0x0c)   | \
 206                                 FTIM0_NAND_TWCHT(0x08) | \
 207                                 FTIM0_NAND_TWH(0x06))
 208 #define CONFIG_SYS_NAND_FTIM1   (FTIM1_NAND_TADLE(0x28) | \
 209                                 FTIM1_NAND_TWBE(0x1d)  | \
 210                                 FTIM1_NAND_TRR(0x08)   | \
 211                                 FTIM1_NAND_TRP(0x0c))
 212 #define CONFIG_SYS_NAND_FTIM2   (FTIM2_NAND_TRAD(0x0c) | \
 213                                 FTIM2_NAND_TREH(0x0a) | \
 214                                 FTIM2_NAND_TWHRE(0x18))
 215 #define CONFIG_SYS_NAND_FTIM3   (FTIM3_NAND_TWW(0x04))
 216
 217 #define CONFIG_SYS_NAND_DDR_LAW         11
 218
 219 /* Set up IFC registers for boot location NOR/NAND */
 220 #ifdef CONFIG_NAND
 221 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
 222 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
 223 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
 224 #define CONFIG_SYS_CSOR0_EXT            CONFIG_SYS_NAND_OOBSIZE
 225 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
 226 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
 227 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
 228 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
 229 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR_CSPR
 230 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
 231 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 232 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 233 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 234 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 235 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 236 #else
 237 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR_CSPR
 238 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
 239 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
 240 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
 241 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
 242 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
 243 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
 244 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NAND_CSPR
 245 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NAND_AMASK
 246 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NAND_CSOR
 247 #define CONFIG_SYS_CSOR1_EXT            CONFIG_SYS_NAND_OOBSIZE
 248 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NAND_FTIM0
 249 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NAND_FTIM1
 250 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NAND_FTIM2
 251 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NAND_FTIM3
 252 #endif
 253
 254 /* CPLD on IFC, selected by CS2 */
 255 #define CONFIG_SYS_CPLD_BASE            0xffdf0000
 256 #define CONFIG_SYS_CPLD_BASE_PHYS       (0xf00000000ull \
 257                                         | CONFIG_SYS_CPLD_BASE)
 258
 259 #define CONFIG_SYS_CSPR2        (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \
 260                                 | CSPR_PORT_SIZE_8 \
 261                                 | CSPR_MSEL_GPCM \
 262                                 | CSPR_V)
 263 #define CONFIG_SYS_AMASK2       IFC_AMASK(64*1024)
 264 #define CONFIG_SYS_CSOR2        0x0
 265 /* CPLD Timing parameters for IFC CS2 */
 266 #define CONFIG_SYS_CS2_FTIM0    (FTIM0_GPCM_TACSE(0x0e) | \
 267                                 FTIM0_GPCM_TEADC(0x0e) | \
 268                                 FTIM0_GPCM_TEAHC(0x0e))
 269 #define CONFIG_SYS_CS2_FTIM1    (FTIM1_GPCM_TACO(0x0e) | \
 270                                 FTIM1_GPCM_TRAD(0x1f))
 271 #define CONFIG_SYS_CS2_FTIM2    (FTIM2_GPCM_TCS(0x0e) | \
 272                                 FTIM2_GPCM_TCH(0x8) | \
 273                                 FTIM2_GPCM_TWP(0x1f))
 274 #define CONFIG_SYS_CS2_FTIM3    0x0
 275
 276 #if defined(CONFIG_RAMBOOT_SPIFLASH)
 277 #define CONFIG_SYS_RAMBOOT
 278 #endif
 279
 280 #define CONFIG_SYS_INIT_RAM_LOCK
 281 #define CONFIG_SYS_INIT_RAM_ADDR        0xffd00000
 282 #define CONFIG_SYS_INIT_RAM_SIZE        0x00004000
 283
 284 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE \
 285                                                 - GENERATED_GBL_DATA_SIZE)
 286 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 287
 288 #define CONFIG_SYS_MONITOR_LEN          (768 * 1024)
 289 #define CONFIG_SYS_MALLOC_LEN           (2 * 1024 * 1024)
 290
 291 /*
 292  * Config the L2 Cache as L2 SRAM
 293  */
 294 #if defined(CONFIG_SPL_BUILD)
 295 #if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH)
 296 #define CONFIG_SYS_INIT_L2_ADDR         0xf8f80000
 297 #define CONFIG_SYS_INIT_L2_ADDR_PHYS    CONFIG_SYS_INIT_L2_ADDR
 298 #define CONFIG_SYS_L2_SIZE              (256 << 10)
 299 #define CONFIG_SYS_INIT_L2_END  (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
 300 #define CONFIG_SPL_RELOC_TEXT_BASE      0xf8f81000
 301 #define CONFIG_SPL_RELOC_STACK          (CONFIG_SYS_INIT_L2_ADDR + 128 * 1024)
 302 #define CONFIG_SPL_RELOC_MALLOC_ADDR    (CONFIG_SYS_INIT_L2_ADDR + 160 * 1024)
 303 #define CONFIG_SPL_RELOC_MALLOC_SIZE    (96 << 10)
 304 #define CONFIG_SPL_GD_ADDR              (CONFIG_SYS_INIT_L2_ADDR + 112 * 1024)
 305 #elif defined(CONFIG_NAND)
 306 #ifdef CONFIG_TPL_BUILD
 307 #define CONFIG_SYS_INIT_L2_ADDR         0xf8f80000
 308 #define CONFIG_SYS_INIT_L2_ADDR_PHYS    CONFIG_SYS_INIT_L2_ADDR
 309 #define CONFIG_SYS_L2_SIZE              (256 << 10)
 310 #define CONFIG_SYS_INIT_L2_END  (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
 311 #define CONFIG_SPL_RELOC_TEXT_BASE      0xf8f81000
 312 #define CONFIG_SPL_RELOC_STACK          (CONFIG_SYS_INIT_L2_ADDR + 192 * 1024)
 313 #define CONFIG_SPL_RELOC_MALLOC_ADDR    (CONFIG_SYS_INIT_L2_ADDR + 208 * 1024)
 314 #define CONFIG_SPL_RELOC_MALLOC_SIZE    (48 << 10)
 315 #define CONFIG_SPL_GD_ADDR              (CONFIG_SYS_INIT_L2_ADDR + 176 * 1024)
 316 #else
 317 #define CONFIG_SYS_INIT_L2_ADDR         0xf8f80000
 318 #define CONFIG_SYS_INIT_L2_ADDR_PHYS    CONFIG_SYS_INIT_L2_ADDR
 319 #define CONFIG_SYS_L2_SIZE              (256 << 10)
 320 #define CONFIG_SYS_INIT_L2_END  (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
 321 #define CONFIG_SPL_RELOC_TEXT_BASE      (CONFIG_SYS_INIT_L2_END - 0x3000)
 322 #define CONFIG_SPL_RELOC_STACK          ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
 323 #endif
 324 #endif
 325 #endif
 326
 327 /* Serial Port */
 328 #define CONFIG_SYS_NS16550_SERIAL
 329 #define CONFIG_SYS_NS16550_REG_SIZE     1
 330 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 331
 332 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL)
 333 #define CONFIG_NS16550_MIN_FUNCTIONS
 334 #endif
 335
 336 #define CONFIG_SYS_BAUDRATE_TABLE       \
 337         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 338
 339 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
 340 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
 341
 342 #define CONFIG_SYS_I2C
 343 #define CONFIG_SYS_I2C_FSL
 344 #define CONFIG_SYS_FSL_I2C_SPEED        400000
 345 #define CONFIG_SYS_FSL_I2C2_SPEED       400000
 346 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 347 #define CONFIG_SYS_FSL_I2C2_SLAVE       0x7F
 348 #define CONFIG_SYS_FSL_I2C_OFFSET       0x3000
 349 #define CONFIG_SYS_FSL_I2C2_OFFSET      0x3100
 350
 351 /* I2C EEPROM */
 352 /* enable read and write access to EEPROM */
 353 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
 354 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
 355 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
 356
 357 /* eSPI - Enhanced SPI */
 358 #define CONFIG_SF_DEFAULT_SPEED         10000000
 359 #define CONFIG_SF_DEFAULT_MODE          SPI_MODE_0
 360
 361 #ifdef CONFIG_TSEC_ENET
 362 #define CONFIG_MII_DEFAULT_TSEC 1       /* Allow unregistered phys */
 363 #define CONFIG_TSEC1            1
 364 #define CONFIG_TSEC1_NAME       "eTSEC1"
 365 #define CONFIG_TSEC2            1
 366 #define CONFIG_TSEC2_NAME       "eTSEC2"
 367
 368 /* Default mode is RGMII mode */
 369 #define TSEC1_PHY_ADDR          0
 370 #define TSEC2_PHY_ADDR          2
 371
 372 #define TSEC1_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
 373 #define TSEC2_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
 374
 375 #define CONFIG_ETHPRIME         "eTSEC1"
 376 #endif  /* CONFIG_TSEC_ENET */
 377
 378 /*
 379  * Environment
 380  */
 381 #if defined(CONFIG_SYS_RAMBOOT)
 382 #if defined(CONFIG_RAMBOOT_SPIFLASH)
 383 #define CONFIG_ENV_SPI_BUS      0
 384 #define CONFIG_ENV_SPI_CS       0
 385 #define CONFIG_ENV_SPI_MAX_HZ   10000000
 386 #define CONFIG_ENV_SPI_MODE     0
 387 #define CONFIG_ENV_OFFSET       0x100000        /* 1MB */
 388 #define CONFIG_ENV_SECT_SIZE    0x10000
 389 #define CONFIG_ENV_SIZE         0x2000
 390 #endif
 391 #elif defined(CONFIG_NAND)
 392 #ifdef CONFIG_TPL_BUILD
 393 #define CONFIG_ENV_SIZE         0x2000
 394 #define CONFIG_ENV_ADDR         (CONFIG_SYS_INIT_L2_ADDR + (160 << 10))
 395 #else
 396 #define CONFIG_ENV_SIZE         CONFIG_SYS_NAND_BLOCK_SIZE
 397 #define CONFIG_ENV_RANGE        CONFIG_ENV_SIZE
 398 #endif
 399 #define CONFIG_ENV_OFFSET       CONFIG_SYS_NAND_BLOCK_SIZE
 400 #else
 401 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
 402 #define CONFIG_ENV_SIZE         0x2000
 403 #define CONFIG_ENV_SECT_SIZE    0x20000
 404 #endif
 405
 406 #define CONFIG_LOADS_ECHO
 407 #define CONFIG_SYS_LOADS_BAUD_CHANGE
 408
 409 /*
 410  * Miscellaneous configurable options
 411  */
 412 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 413
 414 /*
 415  * For booting Linux, the board info and command line data
 416  * have to be in the first 64 MB of memory, since this is
 417  * the maximum mapped by the Linux kernel during initialization.
 418  */
 419 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20) /* Initial Memory map for Linux */
 420 #define CONFIG_SYS_BOOTM_LEN    (64 << 20) /* Increase max gunzip size */
 421
 422 /*
 423  * Environment Configuration
 424  */
 425
 426 #ifdef CONFIG_TSEC_ENET
 427 #define CONFIG_HAS_ETH0
 428 #define CONFIG_HAS_ETH1
 429 #endif
 430
 431 #define CONFIG_ROOTPATH         "/opt/nfsroot"
 432 #define CONFIG_BOOTFILE         "uImage"
 433 #define CONFIG_UBOOTPATH        u-boot.bin/* U-Boot image on TFTP server */
 434
 435 /* default location for tftp and bootm */
 436 #define CONFIG_LOADADDR         1000000
 437
 438 #define CONFIG_DEF_HWCONFIG     fsl_ddr:ecc=on
 439
 440 #define CONFIG_EXTRA_ENV_SETTINGS                               \
 441         "hwconfig=" __stringify(CONFIG_DEF_HWCONFIG)  "\0"      \
 442         "netdev=eth0\0"                                         \
 443         "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"             \
 444         "loadaddr=1000000\0"                            \
 445         "consoledev=ttyS0\0"                            \
 446         "ramdiskaddr=2000000\0"                         \
 447         "ramdiskfile=rootfs.ext2.gz.uboot\0"            \
 448         "fdtaddr=1e00000\0"                             \
 449         "fdtfile=name/of/device-tree.dtb\0"                     \
 450         "othbootargs=ramdisk_size=600000\0"             \
 451
 452 #define CONFIG_RAMBOOTCOMMAND                   \
 453         "setenv bootargs root=/dev/ram rw "     \
 454         "console=$consoledev,$baudrate $othbootargs; "  \
 455         "tftp $ramdiskaddr $ramdiskfile;"       \
 456         "tftp $loadaddr $bootfile;"             \
 457         "tftp $fdtaddr $fdtfile;"               \
 458         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 459
 460 #define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND
 461
 462 #include <asm/fsl_secure_boot.h>
 463
 464 #endif  /* __CONFIG_H */