1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2013 Freescale Semiconductor, Inc.
7 * C29XPCIE board configuration file
13 #ifdef CONFIG_SPIFLASH
14 #define CONFIG_RAMBOOT_SPIFLASH
15 #define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc
19 #ifdef CONFIG_TPL_BUILD
20 #define CONFIG_SPL_NAND_BOOT
21 #define CONFIG_SPL_FLUSH_IMAGE
22 #define CONFIG_SPL_NAND_INIT
23 #define CONFIG_TPL_DRIVERS_MISC_SUPPORT
24 #define CONFIG_SPL_COMMON_INIT_DDR
25 #define CONFIG_SPL_MAX_SIZE (128 << 10)
26 #define CONFIG_TPL_TEXT_BASE 0xf8f81000
27 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
28 #define CONFIG_SYS_NAND_U_BOOT_SIZE (832 << 10)
29 #define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000)
30 #define CONFIG_SYS_NAND_U_BOOT_START (0x11000000)
31 #define CONFIG_SYS_NAND_U_BOOT_OFFS ((128 + 128) << 10)
32 #elif defined(CONFIG_SPL_BUILD)
33 #define CONFIG_SPL_INIT_MINIMAL
34 #define CONFIG_SPL_NAND_MINIMAL
35 #define CONFIG_SPL_FLUSH_IMAGE
36 #define CONFIG_SPL_MAX_SIZE 8192
37 #define CONFIG_SYS_NAND_U_BOOT_SIZE (128 << 10)
38 #define CONFIG_SYS_NAND_U_BOOT_DST 0xf8f80000
39 #define CONFIG_SYS_NAND_U_BOOT_START 0xf8f80000
40 #define CONFIG_SYS_NAND_U_BOOT_OFFS (128 << 10)
42 #define CONFIG_SPL_PAD_TO 0x20000
43 #define CONFIG_TPL_PAD_TO 0x20000
44 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
45 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
48 #ifndef CONFIG_RESET_VECTOR_ADDRESS
49 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
52 #ifdef CONFIG_TPL_BUILD
53 #define CONFIG_SYS_MONITOR_BASE CONFIG_TPL_TEXT_BASE
54 #elif defined(CONFIG_SPL_BUILD)
55 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
57 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
60 #ifdef CONFIG_SPL_BUILD
61 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
64 /* High Level Configuration Options */
65 #define CONFIG_SYS_HAS_SERDES /* common SERDES init code */
68 #define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */
69 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
70 #define CONFIG_PCI_INDIRECT_BRIDGE
71 #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */
72 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
76 * Memory space is mapped 1-1, but I/O space must start from 0.
78 /* controller 1, Slot 1, tgtid 1, Base address a000 */
79 #define CONFIG_SYS_PCIE1_NAME "Slot 1"
80 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
81 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
82 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
83 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */
84 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000
85 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
86 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
87 #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc00000ull
89 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
92 #define CONFIG_ENV_OVERWRITE
94 #define CONFIG_DDR_CLK_FREQ 100000000
95 #define CONFIG_SYS_CLK_FREQ 66666666
97 #define CONFIG_HWCONFIG
100 * These can be toggled for performance analysis, otherwise use default.
102 #define CONFIG_L2_CACHE /* toggle L2 cache */
103 #define CONFIG_BTB /* toggle branch predition */
106 #define CONFIG_ENABLE_36BIT_PHYS
108 #define CONFIG_ADDR_MAP 1
109 #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */
111 #define CONFIG_SYS_MEMTEST_START 0x00200000
112 #define CONFIG_SYS_MEMTEST_END 0x00400000
115 #define CONFIG_DDR_SPD
116 #define CONFIG_SYS_SPD_BUS_NUM 0
117 #define SPD_EEPROM_ADDRESS 0x50
118 #define CONFIG_SYS_DDR_RAW_TIMING
121 #define CONFIG_DDR_ECC
122 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef
123 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
125 #define CONFIG_SYS_SDRAM_SIZE 512
126 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
127 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
129 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
130 #define CONFIG_CHIP_SELECTS_PER_CTRL 1
132 #define CONFIG_SYS_CCSRBAR 0xffe00000
133 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
135 /* Platform SRAM setting */
136 #define CONFIG_SYS_PLATFORM_SRAM_BASE 0xffb00000
137 #define CONFIG_SYS_PLATFORM_SRAM_BASE_PHYS \
138 (0xf00000000ull | CONFIG_SYS_PLATFORM_SRAM_BASE)
139 #define CONFIG_SYS_PLATFORM_SRAM_SIZE (512 << 10)
144 /* NOR Flash on IFC */
145 #define CONFIG_SYS_FLASH_BASE 0xec000000
146 #define CONFIG_SYS_MAX_FLASH_SECT 512 /* 64M */
148 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
150 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE_PHYS }
151 #define CONFIG_SYS_MAX_FLASH_BANKS 1
153 #define CONFIG_SYS_FLASH_QUIET_TEST
154 #define CONFIG_FLASH_SHOW_PROGRESS 45
155 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* in ms */
156 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* in ms */
158 /* 16Bit NOR Flash - S29GL512S10TFI01 */
159 #define CONFIG_SYS_NOR_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
160 CSPR_PORT_SIZE_16 | \
163 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(64*1024*1024)
164 #define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(4)
166 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
167 FTIM0_NOR_TEADC(0x5) | \
168 FTIM0_NOR_TEAHC(0x5))
169 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
170 FTIM1_NOR_TRAD_NOR(0x1A) |\
171 FTIM1_NOR_TSEQRAD_NOR(0x13))
172 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
173 FTIM2_NOR_TCH(0x4) | \
174 FTIM2_NOR_TWPH(0x0E) | \
176 #define CONFIG_SYS_NOR_FTIM3 0x0
178 /* CFI for NOR Flash */
179 #define CONFIG_SYS_FLASH_EMPTY_INFO
181 /* NAND Flash on IFC */
182 #define CONFIG_NAND_FSL_IFC
183 #define CONFIG_SYS_NAND_BASE 0xff800000
184 #define CONFIG_SYS_NAND_BASE_PHYS 0xfff800000ull
186 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
188 #define CONFIG_SYS_MAX_NAND_DEVICE 1
189 #define CONFIG_SYS_NAND_BLOCK_SIZE (1024 * 1024)
191 /* 8Bit NAND Flash - K9F1G08U0B */
192 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
196 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
197 #define CONFIG_SYS_NAND_OOBSIZE 0x00000280 /* 640b */
198 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
199 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
200 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
201 | CSOR_NAND_RAL_3 /* RAL = 3 Bytes */ \
202 | CSOR_NAND_PGS_8K /* Page Size = 8K */ \
203 | CSOR_NAND_SPRZ_CSOR_EXT /*oob in csor_ext*/\
204 | CSOR_NAND_PB(128)) /*128 Pages Per Block*/
205 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x01) | \
206 FTIM0_NAND_TWP(0x0c) | \
207 FTIM0_NAND_TWCHT(0x08) | \
208 FTIM0_NAND_TWH(0x06))
209 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x28) | \
210 FTIM1_NAND_TWBE(0x1d) | \
211 FTIM1_NAND_TRR(0x08) | \
212 FTIM1_NAND_TRP(0x0c))
213 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0c) | \
214 FTIM2_NAND_TREH(0x0a) | \
215 FTIM2_NAND_TWHRE(0x18))
216 #define CONFIG_SYS_NAND_FTIM3 (FTIM3_NAND_TWW(0x04))
218 #define CONFIG_SYS_NAND_DDR_LAW 11
220 /* Set up IFC registers for boot location NOR/NAND */
222 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
223 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
224 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
225 #define CONFIG_SYS_CSOR0_EXT CONFIG_SYS_NAND_OOBSIZE
226 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
227 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
228 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
229 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
230 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR_CSPR
231 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
232 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
233 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
234 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
235 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
236 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
238 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR
239 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
240 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
241 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
242 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
243 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
244 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
245 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR
246 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK
247 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR
248 #define CONFIG_SYS_CSOR1_EXT CONFIG_SYS_NAND_OOBSIZE
249 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0
250 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1
251 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2
252 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3
255 /* CPLD on IFC, selected by CS2 */
256 #define CONFIG_SYS_CPLD_BASE 0xffdf0000
257 #define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull \
258 | CONFIG_SYS_CPLD_BASE)
260 #define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \
264 #define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024)
265 #define CONFIG_SYS_CSOR2 0x0
266 /* CPLD Timing parameters for IFC CS2 */
267 #define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
268 FTIM0_GPCM_TEADC(0x0e) | \
269 FTIM0_GPCM_TEAHC(0x0e))
270 #define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \
271 FTIM1_GPCM_TRAD(0x1f))
272 #define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
273 FTIM2_GPCM_TCH(0x8) | \
274 FTIM2_GPCM_TWP(0x1f))
275 #define CONFIG_SYS_CS2_FTIM3 0x0
277 #if defined(CONFIG_RAMBOOT_SPIFLASH)
278 #define CONFIG_SYS_RAMBOOT
281 #define CONFIG_SYS_INIT_RAM_LOCK
282 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000
283 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
285 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE \
286 - GENERATED_GBL_DATA_SIZE)
287 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
289 #define CONFIG_SYS_MONITOR_LEN (768 * 1024)
290 #define CONFIG_SYS_MALLOC_LEN (2 * 1024 * 1024)
293 * Config the L2 Cache as L2 SRAM
295 #if defined(CONFIG_SPL_BUILD)
296 #if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH)
297 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
298 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
299 #define CONFIG_SYS_L2_SIZE (256 << 10)
300 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
301 #define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000
302 #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 128 * 1024)
303 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 160 * 1024)
304 #define CONFIG_SPL_RELOC_MALLOC_SIZE (96 << 10)
305 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 112 * 1024)
306 #elif defined(CONFIG_NAND)
307 #ifdef CONFIG_TPL_BUILD
308 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
309 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
310 #define CONFIG_SYS_L2_SIZE (256 << 10)
311 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
312 #define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000
313 #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 192 * 1024)
314 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 208 * 1024)
315 #define CONFIG_SPL_RELOC_MALLOC_SIZE (48 << 10)
316 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 176 * 1024)
318 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
319 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
320 #define CONFIG_SYS_L2_SIZE (256 << 10)
321 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
322 #define CONFIG_SPL_RELOC_TEXT_BASE (CONFIG_SYS_INIT_L2_END - 0x3000)
323 #define CONFIG_SPL_RELOC_STACK ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
329 #define CONFIG_SYS_NS16550_SERIAL
330 #define CONFIG_SYS_NS16550_REG_SIZE 1
331 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
333 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL)
334 #define CONFIG_NS16550_MIN_FUNCTIONS
337 #define CONFIG_SYS_BAUDRATE_TABLE \
338 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
340 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
341 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
343 #define CONFIG_SYS_I2C
344 #define CONFIG_SYS_I2C_FSL
345 #define CONFIG_SYS_FSL_I2C_SPEED 400000
346 #define CONFIG_SYS_FSL_I2C2_SPEED 400000
347 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
348 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
349 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
350 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
353 /* enable read and write access to EEPROM */
354 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
355 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
356 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
358 /* eSPI - Enhanced SPI */
360 #ifdef CONFIG_TSEC_ENET
361 #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */
362 #define CONFIG_TSEC1 1
363 #define CONFIG_TSEC1_NAME "eTSEC1"
364 #define CONFIG_TSEC2 1
365 #define CONFIG_TSEC2_NAME "eTSEC2"
367 /* Default mode is RGMII mode */
368 #define TSEC1_PHY_ADDR 0
369 #define TSEC2_PHY_ADDR 2
371 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
372 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
374 #define CONFIG_ETHPRIME "eTSEC1"
375 #endif /* CONFIG_TSEC_ENET */
380 #if defined(CONFIG_SYS_RAMBOOT)
381 #if defined(CONFIG_RAMBOOT_SPIFLASH)
382 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
383 #define CONFIG_ENV_SECT_SIZE 0x10000
384 #define CONFIG_ENV_SIZE 0x2000
386 #elif defined(CONFIG_NAND)
387 #ifdef CONFIG_TPL_BUILD
388 #define CONFIG_ENV_SIZE 0x2000
389 #define CONFIG_ENV_ADDR (CONFIG_SYS_INIT_L2_ADDR + (160 << 10))
391 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
392 #define CONFIG_ENV_RANGE CONFIG_ENV_SIZE
394 #define CONFIG_ENV_OFFSET CONFIG_SYS_NAND_BLOCK_SIZE
396 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
397 #define CONFIG_ENV_SIZE 0x2000
398 #define CONFIG_ENV_SECT_SIZE 0x20000
401 #define CONFIG_LOADS_ECHO
402 #define CONFIG_SYS_LOADS_BAUD_CHANGE
405 * Miscellaneous configurable options
407 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
410 * For booting Linux, the board info and command line data
411 * have to be in the first 64 MB of memory, since this is
412 * the maximum mapped by the Linux kernel during initialization.
414 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux */
415 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
418 * Environment Configuration
421 #ifdef CONFIG_TSEC_ENET
422 #define CONFIG_HAS_ETH0
423 #define CONFIG_HAS_ETH1
426 #define CONFIG_ROOTPATH "/opt/nfsroot"
427 #define CONFIG_BOOTFILE "uImage"
428 #define CONFIG_UBOOTPATH u-boot.bin/* U-Boot image on TFTP server */
430 /* default location for tftp and bootm */
431 #define CONFIG_LOADADDR 1000000
433 #define CONFIG_DEF_HWCONFIG fsl_ddr:ecc=on
435 #define CONFIG_EXTRA_ENV_SETTINGS \
436 "hwconfig=" __stringify(CONFIG_DEF_HWCONFIG) "\0" \
438 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
439 "loadaddr=1000000\0" \
440 "consoledev=ttyS0\0" \
441 "ramdiskaddr=2000000\0" \
442 "ramdiskfile=rootfs.ext2.gz.uboot\0" \
443 "fdtaddr=1e00000\0" \
444 "fdtfile=name/of/device-tree.dtb\0" \
445 "othbootargs=ramdisk_size=600000\0" \
447 #define CONFIG_RAMBOOTCOMMAND \
448 "setenv bootargs root=/dev/ram rw " \
449 "console=$consoledev,$baudrate $othbootargs; " \
450 "tftp $ramdiskaddr $ramdiskfile;" \
451 "tftp $loadaddr $bootfile;" \
452 "tftp $fdtaddr $fdtfile;" \
453 "bootm $loadaddr $ramdiskaddr $fdtaddr"
455 #define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND
457 #include <asm/fsl_secure_boot.h>
459 #endif /* __CONFIG_H */