1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2013 Freescale Semiconductor, Inc.
7 * C29XPCIE board configuration file
13 #include <linux/stringify.h>
15 #ifdef CONFIG_SPIFLASH
16 #define CONFIG_RAMBOOT_SPIFLASH
17 #define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc
20 #ifdef CONFIG_MTD_RAW_NAND
21 #ifdef CONFIG_TPL_BUILD
22 #define CONFIG_SPL_FLUSH_IMAGE
23 #define CONFIG_SPL_NAND_INIT
24 #define CONFIG_TPL_DRIVERS_MISC_SUPPORT
25 #define CONFIG_SPL_COMMON_INIT_DDR
26 #define CONFIG_SPL_MAX_SIZE (128 << 10)
27 #define CONFIG_TPL_TEXT_BASE 0xf8f81000
28 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
29 #define CONFIG_SYS_NAND_U_BOOT_SIZE (832 << 10)
30 #define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000)
31 #define CONFIG_SYS_NAND_U_BOOT_START (0x11000000)
32 #define CONFIG_SYS_NAND_U_BOOT_OFFS ((128 + 128) << 10)
33 #elif defined(CONFIG_SPL_BUILD)
34 #define CONFIG_SPL_INIT_MINIMAL
35 #define CONFIG_SPL_NAND_MINIMAL
36 #define CONFIG_SPL_FLUSH_IMAGE
37 #define CONFIG_SPL_MAX_SIZE 8192
38 #define CONFIG_SYS_NAND_U_BOOT_SIZE (128 << 10)
39 #define CONFIG_SYS_NAND_U_BOOT_DST 0xf8f80000
40 #define CONFIG_SYS_NAND_U_BOOT_START 0xf8f80000
41 #define CONFIG_SYS_NAND_U_BOOT_OFFS (128 << 10)
43 #define CONFIG_SPL_PAD_TO 0x20000
44 #define CONFIG_TPL_PAD_TO 0x20000
45 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
48 #ifndef CONFIG_RESET_VECTOR_ADDRESS
49 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
52 #ifdef CONFIG_TPL_BUILD
53 #define CONFIG_SYS_MONITOR_BASE CONFIG_TPL_TEXT_BASE
54 #elif defined(CONFIG_SPL_BUILD)
55 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
57 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
60 #ifdef CONFIG_SPL_BUILD
61 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
64 /* High Level Configuration Options */
65 #define CONFIG_SYS_HAS_SERDES /* common SERDES init code */
68 #define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */
69 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
70 #define CONFIG_PCI_INDIRECT_BRIDGE
71 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
75 * Memory space is mapped 1-1, but I/O space must start from 0.
77 /* controller 1, Slot 1, tgtid 1, Base address a000 */
78 #define CONFIG_SYS_PCIE1_NAME "Slot 1"
79 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
80 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
81 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
82 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */
83 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000
84 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
85 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
86 #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc00000ull
88 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
91 #define CONFIG_ENV_OVERWRITE
93 #define CONFIG_DDR_CLK_FREQ 100000000
94 #define CONFIG_SYS_CLK_FREQ 66666666
96 #define CONFIG_HWCONFIG
99 * These can be toggled for performance analysis, otherwise use default.
101 #define CONFIG_L2_CACHE /* toggle L2 cache */
102 #define CONFIG_BTB /* toggle branch predition */
105 #define CONFIG_ENABLE_36BIT_PHYS
107 #define CONFIG_ADDR_MAP 1
108 #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */
111 #define CONFIG_DDR_SPD
112 #define CONFIG_SYS_SPD_BUS_NUM 0
113 #define SPD_EEPROM_ADDRESS 0x50
114 #define CONFIG_SYS_DDR_RAW_TIMING
117 #define CONFIG_DDR_ECC
118 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef
119 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
121 #define CONFIG_SYS_SDRAM_SIZE 512
122 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
123 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
125 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
126 #define CONFIG_CHIP_SELECTS_PER_CTRL 1
128 #define CONFIG_SYS_CCSRBAR 0xffe00000
129 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
131 /* Platform SRAM setting */
132 #define CONFIG_SYS_PLATFORM_SRAM_BASE 0xffb00000
133 #define CONFIG_SYS_PLATFORM_SRAM_BASE_PHYS \
134 (0xf00000000ull | CONFIG_SYS_PLATFORM_SRAM_BASE)
135 #define CONFIG_SYS_PLATFORM_SRAM_SIZE (512 << 10)
140 /* NOR Flash on IFC */
141 #define CONFIG_SYS_FLASH_BASE 0xec000000
142 #define CONFIG_SYS_MAX_FLASH_SECT 512 /* 64M */
144 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
146 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE_PHYS }
147 #define CONFIG_SYS_MAX_FLASH_BANKS 1
149 #define CONFIG_SYS_FLASH_QUIET_TEST
150 #define CONFIG_FLASH_SHOW_PROGRESS 45
151 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* in ms */
152 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* in ms */
154 /* 16Bit NOR Flash - S29GL512S10TFI01 */
155 #define CONFIG_SYS_NOR_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
156 CSPR_PORT_SIZE_16 | \
159 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(64*1024*1024)
160 #define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(4)
162 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
163 FTIM0_NOR_TEADC(0x5) | \
164 FTIM0_NOR_TEAHC(0x5))
165 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
166 FTIM1_NOR_TRAD_NOR(0x1A) |\
167 FTIM1_NOR_TSEQRAD_NOR(0x13))
168 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
169 FTIM2_NOR_TCH(0x4) | \
170 FTIM2_NOR_TWPH(0x0E) | \
172 #define CONFIG_SYS_NOR_FTIM3 0x0
174 /* CFI for NOR Flash */
175 #define CONFIG_SYS_FLASH_EMPTY_INFO
177 /* NAND Flash on IFC */
178 #define CONFIG_NAND_FSL_IFC
179 #define CONFIG_SYS_NAND_BASE 0xff800000
180 #define CONFIG_SYS_NAND_BASE_PHYS 0xfff800000ull
182 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
184 #define CONFIG_SYS_MAX_NAND_DEVICE 1
185 #define CONFIG_SYS_NAND_BLOCK_SIZE (1024 * 1024)
187 /* 8Bit NAND Flash - K9F1G08U0B */
188 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
192 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
193 #define CONFIG_SYS_NAND_OOBSIZE 0x00000280 /* 640b */
194 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
195 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
196 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
197 | CSOR_NAND_RAL_3 /* RAL = 3 Bytes */ \
198 | CSOR_NAND_PGS_8K /* Page Size = 8K */ \
199 | CSOR_NAND_SPRZ_CSOR_EXT /*oob in csor_ext*/\
200 | CSOR_NAND_PB(128)) /*128 Pages Per Block*/
201 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x01) | \
202 FTIM0_NAND_TWP(0x0c) | \
203 FTIM0_NAND_TWCHT(0x08) | \
204 FTIM0_NAND_TWH(0x06))
205 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x28) | \
206 FTIM1_NAND_TWBE(0x1d) | \
207 FTIM1_NAND_TRR(0x08) | \
208 FTIM1_NAND_TRP(0x0c))
209 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0c) | \
210 FTIM2_NAND_TREH(0x0a) | \
211 FTIM2_NAND_TWHRE(0x18))
212 #define CONFIG_SYS_NAND_FTIM3 (FTIM3_NAND_TWW(0x04))
214 #define CONFIG_SYS_NAND_DDR_LAW 11
216 /* Set up IFC registers for boot location NOR/NAND */
217 #ifdef CONFIG_MTD_RAW_NAND
218 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
219 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
220 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
221 #define CONFIG_SYS_CSOR0_EXT CONFIG_SYS_NAND_OOBSIZE
222 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
223 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
224 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
225 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
226 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR_CSPR
227 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
228 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
229 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
230 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
231 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
232 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
234 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR
235 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
236 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
237 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
238 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
239 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
240 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
241 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR
242 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK
243 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR
244 #define CONFIG_SYS_CSOR1_EXT CONFIG_SYS_NAND_OOBSIZE
245 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0
246 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1
247 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2
248 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3
251 /* CPLD on IFC, selected by CS2 */
252 #define CONFIG_SYS_CPLD_BASE 0xffdf0000
253 #define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull \
254 | CONFIG_SYS_CPLD_BASE)
256 #define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \
260 #define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024)
261 #define CONFIG_SYS_CSOR2 0x0
262 /* CPLD Timing parameters for IFC CS2 */
263 #define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
264 FTIM0_GPCM_TEADC(0x0e) | \
265 FTIM0_GPCM_TEAHC(0x0e))
266 #define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \
267 FTIM1_GPCM_TRAD(0x1f))
268 #define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
269 FTIM2_GPCM_TCH(0x8) | \
270 FTIM2_GPCM_TWP(0x1f))
271 #define CONFIG_SYS_CS2_FTIM3 0x0
273 #if defined(CONFIG_RAMBOOT_SPIFLASH)
274 #define CONFIG_SYS_RAMBOOT
277 #define CONFIG_SYS_INIT_RAM_LOCK
278 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000
279 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
281 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE \
282 - GENERATED_GBL_DATA_SIZE)
283 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
285 #define CONFIG_SYS_MONITOR_LEN (768 * 1024)
286 #define CONFIG_SYS_MALLOC_LEN (2 * 1024 * 1024)
289 * Config the L2 Cache as L2 SRAM
291 #if defined(CONFIG_SPL_BUILD)
292 #if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH)
293 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
294 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
295 #define CONFIG_SYS_L2_SIZE (256 << 10)
296 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
297 #define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000
298 #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 128 * 1024)
299 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 160 * 1024)
300 #define CONFIG_SPL_RELOC_MALLOC_SIZE (96 << 10)
301 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 112 * 1024)
302 #elif defined(CONFIG_MTD_RAW_NAND)
303 #ifdef CONFIG_TPL_BUILD
304 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
305 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
306 #define CONFIG_SYS_L2_SIZE (256 << 10)
307 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
308 #define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000
309 #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 192 * 1024)
310 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 208 * 1024)
311 #define CONFIG_SPL_RELOC_MALLOC_SIZE (48 << 10)
312 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 176 * 1024)
314 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
315 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
316 #define CONFIG_SYS_L2_SIZE (256 << 10)
317 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
318 #define CONFIG_SPL_RELOC_TEXT_BASE (CONFIG_SYS_INIT_L2_END - 0x3000)
319 #define CONFIG_SPL_RELOC_STACK ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
325 #define CONFIG_SYS_NS16550_SERIAL
326 #define CONFIG_SYS_NS16550_REG_SIZE 1
327 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
329 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL)
330 #define CONFIG_NS16550_MIN_FUNCTIONS
333 #define CONFIG_SYS_BAUDRATE_TABLE \
334 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
336 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
337 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
339 #define CONFIG_SYS_I2C
340 #define CONFIG_SYS_I2C_FSL
341 #define CONFIG_SYS_FSL_I2C_SPEED 400000
342 #define CONFIG_SYS_FSL_I2C2_SPEED 400000
343 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
344 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
345 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
346 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
349 /* enable read and write access to EEPROM */
350 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
351 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
352 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
354 /* eSPI - Enhanced SPI */
356 #ifdef CONFIG_TSEC_ENET
357 #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */
358 #define CONFIG_TSEC1 1
359 #define CONFIG_TSEC1_NAME "eTSEC1"
360 #define CONFIG_TSEC2 1
361 #define CONFIG_TSEC2_NAME "eTSEC2"
363 /* Default mode is RGMII mode */
364 #define TSEC1_PHY_ADDR 0
365 #define TSEC2_PHY_ADDR 2
367 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
368 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
370 #define CONFIG_ETHPRIME "eTSEC1"
371 #endif /* CONFIG_TSEC_ENET */
376 #if defined(CONFIG_SYS_RAMBOOT)
377 #elif defined(CONFIG_MTD_RAW_NAND)
378 #ifdef CONFIG_TPL_BUILD
379 #define SPL_ENV_ADDR (CONFIG_SYS_INIT_L2_ADDR + (160 << 10))
381 #define CONFIG_ENV_RANGE CONFIG_ENV_SIZE
385 #define CONFIG_LOADS_ECHO
386 #define CONFIG_SYS_LOADS_BAUD_CHANGE
389 * Miscellaneous configurable options
391 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
394 * For booting Linux, the board info and command line data
395 * have to be in the first 64 MB of memory, since this is
396 * the maximum mapped by the Linux kernel during initialization.
398 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux */
399 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
402 * Environment Configuration
405 #ifdef CONFIG_TSEC_ENET
406 #define CONFIG_HAS_ETH0
407 #define CONFIG_HAS_ETH1
410 #define CONFIG_ROOTPATH "/opt/nfsroot"
411 #define CONFIG_BOOTFILE "uImage"
412 #define CONFIG_UBOOTPATH u-boot.bin/* U-Boot image on TFTP server */
414 /* default location for tftp and bootm */
415 #define CONFIG_LOADADDR 1000000
417 #define CONFIG_DEF_HWCONFIG fsl_ddr:ecc=on
419 #define CONFIG_EXTRA_ENV_SETTINGS \
420 "hwconfig=" __stringify(CONFIG_DEF_HWCONFIG) "\0" \
422 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
423 "loadaddr=1000000\0" \
424 "consoledev=ttyS0\0" \
425 "ramdiskaddr=2000000\0" \
426 "ramdiskfile=rootfs.ext2.gz.uboot\0" \
427 "fdtaddr=1e00000\0" \
428 "fdtfile=name/of/device-tree.dtb\0" \
429 "othbootargs=ramdisk_size=600000\0" \
431 #define CONFIG_RAMBOOTCOMMAND \
432 "setenv bootargs root=/dev/ram rw " \
433 "console=$consoledev,$baudrate $othbootargs; " \
434 "tftp $ramdiskaddr $ramdiskfile;" \
435 "tftp $loadaddr $bootfile;" \
436 "tftp $fdtaddr $fdtfile;" \
437 "bootm $loadaddr $ramdiskaddr $fdtaddr"
439 #define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND
441 #include <asm/fsl_secure_boot.h>
443 #endif /* __CONFIG_H */