1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2013 Freescale Semiconductor, Inc.
7 * C29XPCIE board configuration file
13 #ifdef CONFIG_SPIFLASH
14 #define CONFIG_RAMBOOT_SPIFLASH
15 #define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc
18 #ifdef CONFIG_MTD_RAW_NAND
19 #ifdef CONFIG_TPL_BUILD
20 #define CONFIG_SPL_FLUSH_IMAGE
21 #define CONFIG_SPL_NAND_INIT
22 #define CONFIG_TPL_DRIVERS_MISC_SUPPORT
23 #define CONFIG_SPL_COMMON_INIT_DDR
24 #define CONFIG_SPL_MAX_SIZE (128 << 10)
25 #define CONFIG_TPL_TEXT_BASE 0xf8f81000
26 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
27 #define CONFIG_SYS_NAND_U_BOOT_SIZE (832 << 10)
28 #define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000)
29 #define CONFIG_SYS_NAND_U_BOOT_START (0x11000000)
30 #define CONFIG_SYS_NAND_U_BOOT_OFFS ((128 + 128) << 10)
31 #elif defined(CONFIG_SPL_BUILD)
32 #define CONFIG_SPL_INIT_MINIMAL
33 #define CONFIG_SPL_NAND_MINIMAL
34 #define CONFIG_SPL_FLUSH_IMAGE
35 #define CONFIG_SPL_MAX_SIZE 8192
36 #define CONFIG_SYS_NAND_U_BOOT_SIZE (128 << 10)
37 #define CONFIG_SYS_NAND_U_BOOT_DST 0xf8f80000
38 #define CONFIG_SYS_NAND_U_BOOT_START 0xf8f80000
39 #define CONFIG_SYS_NAND_U_BOOT_OFFS (128 << 10)
41 #define CONFIG_SPL_PAD_TO 0x20000
42 #define CONFIG_TPL_PAD_TO 0x20000
43 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
46 #ifndef CONFIG_RESET_VECTOR_ADDRESS
47 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
50 #ifdef CONFIG_TPL_BUILD
51 #define CONFIG_SYS_MONITOR_BASE CONFIG_TPL_TEXT_BASE
52 #elif defined(CONFIG_SPL_BUILD)
53 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
55 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
58 #ifdef CONFIG_SPL_BUILD
59 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
62 /* High Level Configuration Options */
63 #define CONFIG_SYS_HAS_SERDES /* common SERDES init code */
66 #define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */
67 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
68 #define CONFIG_PCI_INDIRECT_BRIDGE
69 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
73 * Memory space is mapped 1-1, but I/O space must start from 0.
75 /* controller 1, Slot 1, tgtid 1, Base address a000 */
76 #define CONFIG_SYS_PCIE1_NAME "Slot 1"
77 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
78 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
79 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
80 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */
81 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000
82 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
83 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
84 #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc00000ull
86 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
89 #define CONFIG_ENV_OVERWRITE
91 #define CONFIG_DDR_CLK_FREQ 100000000
92 #define CONFIG_SYS_CLK_FREQ 66666666
94 #define CONFIG_HWCONFIG
97 * These can be toggled for performance analysis, otherwise use default.
99 #define CONFIG_L2_CACHE /* toggle L2 cache */
100 #define CONFIG_BTB /* toggle branch predition */
103 #define CONFIG_ENABLE_36BIT_PHYS
105 #define CONFIG_ADDR_MAP 1
106 #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */
109 #define CONFIG_DDR_SPD
110 #define CONFIG_SYS_SPD_BUS_NUM 0
111 #define SPD_EEPROM_ADDRESS 0x50
112 #define CONFIG_SYS_DDR_RAW_TIMING
115 #define CONFIG_DDR_ECC
116 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef
117 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
119 #define CONFIG_SYS_SDRAM_SIZE 512
120 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
121 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
123 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
124 #define CONFIG_CHIP_SELECTS_PER_CTRL 1
126 #define CONFIG_SYS_CCSRBAR 0xffe00000
127 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
129 /* Platform SRAM setting */
130 #define CONFIG_SYS_PLATFORM_SRAM_BASE 0xffb00000
131 #define CONFIG_SYS_PLATFORM_SRAM_BASE_PHYS \
132 (0xf00000000ull | CONFIG_SYS_PLATFORM_SRAM_BASE)
133 #define CONFIG_SYS_PLATFORM_SRAM_SIZE (512 << 10)
138 /* NOR Flash on IFC */
139 #define CONFIG_SYS_FLASH_BASE 0xec000000
140 #define CONFIG_SYS_MAX_FLASH_SECT 512 /* 64M */
142 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
144 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE_PHYS }
145 #define CONFIG_SYS_MAX_FLASH_BANKS 1
147 #define CONFIG_SYS_FLASH_QUIET_TEST
148 #define CONFIG_FLASH_SHOW_PROGRESS 45
149 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* in ms */
150 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* in ms */
152 /* 16Bit NOR Flash - S29GL512S10TFI01 */
153 #define CONFIG_SYS_NOR_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
154 CSPR_PORT_SIZE_16 | \
157 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(64*1024*1024)
158 #define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(4)
160 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
161 FTIM0_NOR_TEADC(0x5) | \
162 FTIM0_NOR_TEAHC(0x5))
163 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
164 FTIM1_NOR_TRAD_NOR(0x1A) |\
165 FTIM1_NOR_TSEQRAD_NOR(0x13))
166 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
167 FTIM2_NOR_TCH(0x4) | \
168 FTIM2_NOR_TWPH(0x0E) | \
170 #define CONFIG_SYS_NOR_FTIM3 0x0
172 /* CFI for NOR Flash */
173 #define CONFIG_SYS_FLASH_EMPTY_INFO
175 /* NAND Flash on IFC */
176 #define CONFIG_NAND_FSL_IFC
177 #define CONFIG_SYS_NAND_BASE 0xff800000
178 #define CONFIG_SYS_NAND_BASE_PHYS 0xfff800000ull
180 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
182 #define CONFIG_SYS_MAX_NAND_DEVICE 1
183 #define CONFIG_SYS_NAND_BLOCK_SIZE (1024 * 1024)
185 /* 8Bit NAND Flash - K9F1G08U0B */
186 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
190 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
191 #define CONFIG_SYS_NAND_OOBSIZE 0x00000280 /* 640b */
192 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
193 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
194 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
195 | CSOR_NAND_RAL_3 /* RAL = 3 Bytes */ \
196 | CSOR_NAND_PGS_8K /* Page Size = 8K */ \
197 | CSOR_NAND_SPRZ_CSOR_EXT /*oob in csor_ext*/\
198 | CSOR_NAND_PB(128)) /*128 Pages Per Block*/
199 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x01) | \
200 FTIM0_NAND_TWP(0x0c) | \
201 FTIM0_NAND_TWCHT(0x08) | \
202 FTIM0_NAND_TWH(0x06))
203 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x28) | \
204 FTIM1_NAND_TWBE(0x1d) | \
205 FTIM1_NAND_TRR(0x08) | \
206 FTIM1_NAND_TRP(0x0c))
207 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0c) | \
208 FTIM2_NAND_TREH(0x0a) | \
209 FTIM2_NAND_TWHRE(0x18))
210 #define CONFIG_SYS_NAND_FTIM3 (FTIM3_NAND_TWW(0x04))
212 #define CONFIG_SYS_NAND_DDR_LAW 11
214 /* Set up IFC registers for boot location NOR/NAND */
215 #ifdef CONFIG_MTD_RAW_NAND
216 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
217 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
218 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
219 #define CONFIG_SYS_CSOR0_EXT CONFIG_SYS_NAND_OOBSIZE
220 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
221 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
222 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
223 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
224 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR_CSPR
225 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
226 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
227 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
228 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
229 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
230 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
232 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR
233 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
234 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
235 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
236 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
237 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
238 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
239 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR
240 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK
241 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR
242 #define CONFIG_SYS_CSOR1_EXT CONFIG_SYS_NAND_OOBSIZE
243 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0
244 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1
245 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2
246 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3
249 /* CPLD on IFC, selected by CS2 */
250 #define CONFIG_SYS_CPLD_BASE 0xffdf0000
251 #define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull \
252 | CONFIG_SYS_CPLD_BASE)
254 #define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \
258 #define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024)
259 #define CONFIG_SYS_CSOR2 0x0
260 /* CPLD Timing parameters for IFC CS2 */
261 #define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
262 FTIM0_GPCM_TEADC(0x0e) | \
263 FTIM0_GPCM_TEAHC(0x0e))
264 #define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \
265 FTIM1_GPCM_TRAD(0x1f))
266 #define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
267 FTIM2_GPCM_TCH(0x8) | \
268 FTIM2_GPCM_TWP(0x1f))
269 #define CONFIG_SYS_CS2_FTIM3 0x0
271 #if defined(CONFIG_RAMBOOT_SPIFLASH)
272 #define CONFIG_SYS_RAMBOOT
275 #define CONFIG_SYS_INIT_RAM_LOCK
276 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000
277 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
279 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE \
280 - GENERATED_GBL_DATA_SIZE)
281 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
283 #define CONFIG_SYS_MONITOR_LEN (768 * 1024)
284 #define CONFIG_SYS_MALLOC_LEN (2 * 1024 * 1024)
287 * Config the L2 Cache as L2 SRAM
289 #if defined(CONFIG_SPL_BUILD)
290 #if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH)
291 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
292 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
293 #define CONFIG_SYS_L2_SIZE (256 << 10)
294 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
295 #define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000
296 #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 128 * 1024)
297 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 160 * 1024)
298 #define CONFIG_SPL_RELOC_MALLOC_SIZE (96 << 10)
299 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 112 * 1024)
300 #elif defined(CONFIG_MTD_RAW_NAND)
301 #ifdef CONFIG_TPL_BUILD
302 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
303 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
304 #define CONFIG_SYS_L2_SIZE (256 << 10)
305 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
306 #define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000
307 #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 192 * 1024)
308 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 208 * 1024)
309 #define CONFIG_SPL_RELOC_MALLOC_SIZE (48 << 10)
310 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 176 * 1024)
312 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
313 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
314 #define CONFIG_SYS_L2_SIZE (256 << 10)
315 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
316 #define CONFIG_SPL_RELOC_TEXT_BASE (CONFIG_SYS_INIT_L2_END - 0x3000)
317 #define CONFIG_SPL_RELOC_STACK ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
323 #define CONFIG_SYS_NS16550_SERIAL
324 #define CONFIG_SYS_NS16550_REG_SIZE 1
325 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
327 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL)
328 #define CONFIG_NS16550_MIN_FUNCTIONS
331 #define CONFIG_SYS_BAUDRATE_TABLE \
332 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
334 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
335 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
337 #define CONFIG_SYS_I2C
338 #define CONFIG_SYS_I2C_FSL
339 #define CONFIG_SYS_FSL_I2C_SPEED 400000
340 #define CONFIG_SYS_FSL_I2C2_SPEED 400000
341 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
342 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
343 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
344 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
347 /* enable read and write access to EEPROM */
348 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
349 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
350 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
352 /* eSPI - Enhanced SPI */
354 #ifdef CONFIG_TSEC_ENET
355 #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */
356 #define CONFIG_TSEC1 1
357 #define CONFIG_TSEC1_NAME "eTSEC1"
358 #define CONFIG_TSEC2 1
359 #define CONFIG_TSEC2_NAME "eTSEC2"
361 /* Default mode is RGMII mode */
362 #define TSEC1_PHY_ADDR 0
363 #define TSEC2_PHY_ADDR 2
365 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
366 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
368 #define CONFIG_ETHPRIME "eTSEC1"
369 #endif /* CONFIG_TSEC_ENET */
374 #if defined(CONFIG_SYS_RAMBOOT)
375 #elif defined(CONFIG_MTD_RAW_NAND)
376 #ifdef CONFIG_TPL_BUILD
377 #define SPL_ENV_ADDR (CONFIG_SYS_INIT_L2_ADDR + (160 << 10))
379 #define CONFIG_ENV_RANGE CONFIG_ENV_SIZE
383 #define CONFIG_LOADS_ECHO
384 #define CONFIG_SYS_LOADS_BAUD_CHANGE
387 * Miscellaneous configurable options
389 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
392 * For booting Linux, the board info and command line data
393 * have to be in the first 64 MB of memory, since this is
394 * the maximum mapped by the Linux kernel during initialization.
396 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux */
397 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
400 * Environment Configuration
403 #ifdef CONFIG_TSEC_ENET
404 #define CONFIG_HAS_ETH0
405 #define CONFIG_HAS_ETH1
408 #define CONFIG_ROOTPATH "/opt/nfsroot"
409 #define CONFIG_BOOTFILE "uImage"
410 #define CONFIG_UBOOTPATH u-boot.bin/* U-Boot image on TFTP server */
412 /* default location for tftp and bootm */
413 #define CONFIG_LOADADDR 1000000
415 #define CONFIG_DEF_HWCONFIG fsl_ddr:ecc=on
417 #define CONFIG_EXTRA_ENV_SETTINGS \
418 "hwconfig=" __stringify(CONFIG_DEF_HWCONFIG) "\0" \
420 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
421 "loadaddr=1000000\0" \
422 "consoledev=ttyS0\0" \
423 "ramdiskaddr=2000000\0" \
424 "ramdiskfile=rootfs.ext2.gz.uboot\0" \
425 "fdtaddr=1e00000\0" \
426 "fdtfile=name/of/device-tree.dtb\0" \
427 "othbootargs=ramdisk_size=600000\0" \
429 #define CONFIG_RAMBOOTCOMMAND \
430 "setenv bootargs root=/dev/ram rw " \
431 "console=$consoledev,$baudrate $othbootargs; " \
432 "tftp $ramdiskaddr $ramdiskfile;" \
433 "tftp $loadaddr $bootfile;" \
434 "tftp $fdtaddr $fdtfile;" \
435 "bootm $loadaddr $ramdiskaddr $fdtaddr"
437 #define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND
439 #include <asm/fsl_secure_boot.h>
441 #endif /* __CONFIG_H */