2 * (C) Copyright 2000, 2001
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 * board/config.h - configuration options, board specific
32 /*#define __DEBUG_START_FROM_SRAM__ */
37 * High Level Configuration Options
41 #define CONFIG_405EP 1 /* This is a PPC405 CPU */
42 #define CONFIG_4xx 1 /* ...member of PPC4xx family */
43 #define CONFIG_BUBINGA405EP 1 /* ...on a BUBINGA405EP board */
45 #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
47 #define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */
49 #define CONFIG_NO_SERIAL_EEPROM
50 /*#undef CONFIG_NO_SERIAL_EEPROM*/
51 /*----------------------------------------------------------------------------*/
52 /*----------------------------------------------------------------------------*/
53 /*----------------------------------------------------------------------------*/
54 #ifdef CONFIG_NO_SERIAL_EEPROM
57 !-------------------------------------------------------------------------------
58 ! Defines for entry options.
59 ! Note: Because the 405EP SDRAM controller does not support ECC, ECC DIMMs that
60 ! are plugged in the board will be utilized as non-ECC DIMMs.
61 !-------------------------------------------------------------------------------
63 #define AUTO_MEMORY_CONFIG
64 #define DIMM_READ_ADDR 0xAB
65 #define DIMM_WRITE_ADDR 0xAA
68 !-------------------------------------------------------------------------------
69 ! PLL settings for 266MHz CPU, 133MHz PLB/SDRAM, 66MHz EBC, 33MHz PCI,
70 ! assuming a 33MHz input clock to the 405EP from the C9531.
71 !-------------------------------------------------------------------------------
73 #define PLLMR0_DEFAULT PLLMR0_266_133_66
74 #define PLLMR1_DEFAULT PLLMR1_266_133_66
77 /*----------------------------------------------------------------------------*/
78 /*----------------------------------------------------------------------------*/
79 /*----------------------------------------------------------------------------*/
81 /*#define CFG_ENV_IS_IN_FLASH 1*/ /* use FLASH for environment vars */
82 #define CFG_ENV_IS_IN_NVRAM 1 /* use NVRAM for environment vars */
84 #ifdef CFG_ENV_IS_IN_NVRAM
85 #undef CFG_ENV_IS_IN_FLASH
87 #ifdef CFG_ENV_IS_IN_FLASH
88 #undef CFG_ENV_IS_IN_NVRAM
92 #define CONFIG_BAUDRATE 115200
93 #define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */
96 #define CONFIG_BOOTCOMMAND "" /* autoboot command */
98 #define CONFIG_BOOTCOMMAND "bootp" /* autoboot command */
101 /* Size (bytes) of interrupt driven serial port buffer.
102 * Set to 0 to use polling instead of interrupts.
103 * Setting to 0 will also disable RTS/CTS handshaking.
106 #define CONFIG_SERIAL_SOFTWARE_FIFO 4000
108 #undef CONFIG_SERIAL_SOFTWARE_FIFO
112 #define CONFIG_BOOTARGS "root=/dev/nfs " \
113 "ip=192.168.2.176:192.168.2.190:192.168.2.79:255.255.255.0 " \
114 "nfsroot=192.168.2.190:/home/stefan/cpci405/target_ftest4"
116 #define CONFIG_BOOTARGS "root=/dev/hda1 " \
117 "ip=192.168.2.176:192.168.2.190:192.168.2.79:255.255.255.0"
121 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
122 #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
124 #define CONFIG_MII 1 /* MII PHY management */
125 #define CONFIG_PHY_ADDR 1 /* PHY address */
127 #define CONFIG_RTC_DS174x 1 /* use DS1743 RTC in Bubinga */
130 #ifndef __DEBUG_START_FROM_SRAM__
131 #define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
140 #define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
151 #define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
168 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
169 #include <cmd_confdefs.h>
171 #undef CONFIG_WATCHDOG /* watchdog disabled */
173 #define CONFIG_SPD_EEPROM 1 /* use SPD EEPROM for setup */
176 * Miscellaneous configurable options
178 #define CFG_LONGHELP /* undef to save memory */
179 #define CFG_PROMPT "=> " /* Monitor Command Prompt */
180 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
181 #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
183 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
185 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
186 #define CFG_MAXARGS 16 /* max number of command args */
187 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
189 #define CFG_MEMTEST_START 0x0400000 /* memtest works on */
190 #define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
193 * If CFG_EXT_SERIAL_CLOCK, then the UART divisor is 1.
194 * If CFG_405_UART_ERRATA_59, then UART divisor is 31.
195 * Otherwise, UART divisor is determined by CPU Clock and CFG_BASE_BAUD value.
196 * The Linux BASE_BAUD define should match this configuration.
197 * baseBaud = cpuClock/(uartDivisor*16)
198 * If CFG_405_UART_ERRATA_59 and 200MHz CPU clock,
199 * set Linux BASE_BAUD to 403200.
201 #undef CFG_EXT_SERIAL_CLOCK /* external serial clock */
202 #undef CFG_405_UART_ERRATA_59 /* 405GP/CR Rev. D silicon */
203 #define CFG_BASE_BAUD 691200
205 /* The following table includes the supported baudrates */
206 #define CFG_BAUDRATE_TABLE \
207 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400}
209 #define CFG_LOAD_ADDR 0x100000 /* default load address */
210 #define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */
212 #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
214 #define CONFIG_HARD_I2C 1 /* I2C with hardware support */
215 #undef CONFIG_SOFT_I2C /* I2C bit-banged */
216 #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
217 #define CFG_I2C_SLAVE 0x7F
219 #define CFG_I2C_NOPROBES { 0x69 } /* avoid iprobe hangup (why?) */
220 #define CFG_EEPROM_PAGE_WRITE_DELAY_MS 6 /* 24C02 requires 5ms delay */
222 #if (CONFIG_COMMANDS & CFG_CMD_EEPROM)
223 #define CFG_I2C_EEPROM_ADDR 0x50 /* I2C boot EEPROM (24C02W) */
224 #define CFG_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
228 /*-----------------------------------------------------------------------
230 *-----------------------------------------------------------------------
232 #define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */
233 #define PCI_HOST_FORCE 1 /* configure as pci host */
234 #define PCI_HOST_AUTO 2 /* detected via arbiter enable */
236 #define CONFIG_PCI /* include pci support */
237 #define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */
238 #define CONFIG_PCI_PNP /* do pci plug-and-play */
239 /* resource configuration */
240 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
242 #define CFG_PCI_SUBSYS_VENDORID 0x1014 /* IBM */
243 #define CFG_PCI_SUBSYS_DEVICEID 0x0000 /* PCI Device ID: to-do!!! */
244 #define CFG_PCI_CLASSCODE 0x0600 /* PCI Class Code: bridge/host */
245 #define CFG_PCI_PTM1LA 0x00000000 /* point to sdram */
246 #define CFG_PCI_PTM1MS 0x80000001 /* 2GB, enable hard-wired to 1 */
247 #define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
248 #define CFG_PCI_PTM2LA 0x00000000 /* disabled */
249 #define CFG_PCI_PTM2MS 0x00000000 /* disabled */
250 #define CFG_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */
252 /*-----------------------------------------------------------------------
253 * External peripheral base address
254 *-----------------------------------------------------------------------
256 #undef CONFIG_IDE_LED /* no led for ide supported */
257 #undef CONFIG_IDE_RESET /* no reset for ide supported */
259 #define CFG_KEY_REG_BASE_ADDR 0xF0100000
260 #define CFG_IR_REG_BASE_ADDR 0xF0200000
261 #define CFG_FPGA_REG_BASE_ADDR 0xF0300000
263 /*-----------------------------------------------------------------------
264 * Start addresses for the final memory configuration
265 * (Set up by the startup code)
266 * Please note that CFG_SDRAM_BASE _must_ start at 0
268 #define CFG_SDRAM_BASE 0x00000000
269 #ifdef __DEBUG_START_FROM_SRAM__
270 #define CFG_SRAM_BASE 0xFFF80000
271 #define CFG_FLASH_BASE 0xFFF00000
272 #define CFG_MONITOR_BASE CFG_SRAM_BASE
274 #define CFG_SRAM_BASE 0xFFF00000
275 #define CFG_FLASH_BASE 0xFFF80000
276 #define CFG_MONITOR_BASE CFG_FLASH_BASE
280 /*#define CFG_MONITOR_LEN (200 * 1024) /XXX* Reserve 200 kB for Monitor */
281 #define CFG_MONITOR_LEN (192 * 1024) /* Reserve 200 kB for Monitor */
282 #define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */
285 * For booting Linux, the board info and command line data
286 * have to be in the first 8 MB of memory, since this is
287 * the maximum mapped by the Linux kernel during initialization.
289 #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
290 /*-----------------------------------------------------------------------
293 #define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
294 #define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
296 #define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
297 #define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
299 /* BEG ENVIRONNEMENT FLASH */
300 #ifdef CFG_ENV_IS_IN_FLASH
301 #define CFG_ENV_OFFSET 0x00050000 /* Offset of Environment Sector */
302 #define CFG_ENV_SIZE 0x10000 /* Total Size of Environment Sector */
303 #define CFG_ENV_SECT_SIZE 0x10000 /* see README - env sector total size */
305 /* END ENVIRONNEMENT FLASH */
306 /*-----------------------------------------------------------------------
309 #define CFG_NVRAM_BASE_ADDR 0xf0000000 /* NVRAM base address */
310 #define CFG_NVRAM_SIZE 0x1ff8 /* NVRAM size */
312 #ifdef CFG_ENV_IS_IN_NVRAM
313 #define CFG_ENV_SIZE 0x0ff8 /* Size of Environment vars */
314 #define CFG_ENV_ADDR \
315 (CFG_NVRAM_BASE_ADDR+CFG_NVRAM_SIZE-CFG_ENV_SIZE) /* Env */
317 /*-----------------------------------------------------------------------
318 * Cache Configuration
320 #define CFG_DCACHE_SIZE 16384 /* For IBM 405EP CPU */
321 #define CFG_CACHELINE_SIZE 32 /* ... */
322 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
323 #define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
327 * Init Memory Controller:
329 * BR0/1 and OR0/1 (FLASH)
332 #define FLASH_BASE0_PRELIM CFG_FLASH_BASE /* FLASH bank #0 */
333 #define FLASH_BASE1_PRELIM 0 /* FLASH bank #1 */
336 /*-----------------------------------------------------------------------
337 * Definitions for initial stack pointer and data area (in data cache)
339 /* use on chip memory ( OCM ) for temperary stack until sdram is tested */
340 #define CFG_TEMP_STACK_OCM 1
342 /* On Chip Memory location */
343 #define CFG_OCM_DATA_ADDR 0xF8000000
344 #define CFG_OCM_DATA_SIZE 0x1000
345 #define CFG_INIT_RAM_ADDR CFG_OCM_DATA_ADDR /* inside of SDRAM */
346 #define CFG_INIT_RAM_END CFG_OCM_DATA_SIZE /* End of used area in RAM */
348 #define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
349 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
350 #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
352 /*-----------------------------------------------------------------------
353 * External Bus Controller (EBC) Setup
356 /* Memory Bank 0 (Flash/SRAM) initialization */
357 #define CFG_EBC_PB0AP 0x04006000
358 #define CFG_EBC_PB0CR 0xFFF18000 /* BAS=0xFFF,BS=1MB,BU=R/W,BW=8bit */
360 /* Memory Bank 1 (NVRAM/RTC) initialization */
361 #define CFG_EBC_PB1AP 0x04041000
362 #define CFG_EBC_PB1CR 0xF0018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */
364 /* Memory Bank 2 (not used) initialization */
365 #define CFG_EBC_PB2AP 0x00000000
366 #define CFG_EBC_PB2CR 0x00000000
368 /* Memory Bank 2 (not used) initialization */
369 #define CFG_EBC_PB3AP 0x00000000
370 #define CFG_EBC_PB3CR 0x00000000
372 /* Memory Bank 4 (FPGA regs) initialization */
373 #define CFG_EBC_PB4AP 0x01815000
374 #define CFG_EBC_PB4CR 0xF0318000 /* BAS=0xF03,BS=1MB,BU=R/W,BW=8bit */
376 /*-----------------------------------------------------------------------
377 * Definitions for Serial Presence Detect EEPROM address
378 * (to get SDRAM settings)
380 #define SPD_EEPROM_ADDRESS 0x55
382 /*-----------------------------------------------------------------------
383 * Definitions for GPIO setup (PPC405EP specific)
385 * GPIO0[0] - External Bus Controller BLAST output
386 * GPIO0[1-9] - Instruction trace outputs
387 * GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs
388 * GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs
389 * GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs
390 * GPIO0[24-27] - UART0 control signal inputs/outputs
391 * GPIO0[28-29] - UART1 data signal input/output
392 * GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs
394 #define CFG_GPIO0_OSRH 0x55555555
395 #define CFG_GPIO0_OSRL 0x40000110
396 #define CFG_GPIO0_ISR1H 0x00000000
397 #define CFG_GPIO0_ISR1L 0x15555445
398 #define CFG_GPIO0_TSRH 0x00000000
399 #define CFG_GPIO0_TSRL 0x00000000
400 #define CFG_GPIO0_TCR 0xFFFF8014
402 /*-----------------------------------------------------------------------
403 * Some BUBINGA stuff...
405 #define NVRAM_BASE 0xF0000000
406 #define FPGA_REG0 0xF0300000 /* FPGA Reg 0 */
407 #define FPGA_REG1 0xF0300001 /* FPGA Reg 1 */
408 #define NVRVFY1 0x4f532d4f /* used to determine if state data in */
409 #define NVRVFY2 0x50454e00 /* NVRAM initialized (ascii for OS-OPEN)*/
411 #define FPGA_REG0_F_RANGE 0x80 /* SDRAM PLL freq range */
412 #define FPGA_REG0_EXT_INT_DIS 0x20 /* External interface disable */
413 #define FPGA_REG0_LED_MASK 0x07 /* Board LEDs DS9, DS10, and DS11 */
414 #define FPGA_REG0_LED0 0x04 /* Turn on LED0 */
415 #define FPGA_REG0_LED1 0x02 /* Turn on LED1 */
416 #define FPGA_REG0_LED2 0x01 /* Turn on LED2 */
418 #define FPGA_REG1_SSPEC_DIS 0x80 /* C9531 Spread Spectrum disabled */
419 #define FPGA_REG1_OFFBD_PCICLK 0x40 /* Onboard PCI clock selected */
420 #define FPGA_REG1_CLOCK_MASK 0x30 /* Mask for C9531 output freq select */
421 #define FPGA_REG1_CLOCK_BIT_SHIFT 4
422 #define FPGA_REG1_PCI_INT_ARB 0x08 /* PCI Internal arbiter selected */
423 #define FPGA_REG1_PCI_FREQ 0x04 /* PCI Frequency select */
424 #define FPGA_REG1_OFFB_FLASH 0x02 /* Off board flash */
425 #define FPGA_REG1_SRAM_BOOT 0x01 /* SRAM at 0xFFF80000 not Flash */
429 * Internal Definitions
433 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
434 #define BOOTFLAG_WARM 0x02 /* Software reboot */
436 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
437 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
438 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
441 #endif /* __CONFIG_H */