1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2013 Freescale Semiconductor, Inc.
7 * BSC9132 QDS board configuration file
14 #define CONFIG_RAMBOOT_SDCARD
15 #define CONFIG_SYS_RAMBOOT
16 #define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc
18 #ifdef CONFIG_SPIFLASH
19 #define CONFIG_RAMBOOT_SPIFLASH
20 #define CONFIG_SYS_RAMBOOT
21 #define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc
23 #ifdef CONFIG_NAND_SECBOOT
24 #define CONFIG_RAMBOOT_NAND
25 #define CONFIG_SYS_RAMBOOT
26 #define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc
29 #ifdef CONFIG_MTD_RAW_NAND
30 #define CONFIG_SPL_INIT_MINIMAL
31 #define CONFIG_SPL_FLUSH_IMAGE
32 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
34 #define CONFIG_SPL_MAX_SIZE 8192
35 #define CONFIG_SPL_RELOC_TEXT_BASE 0x00100000
36 #define CONFIG_SPL_RELOC_STACK 0x00100000
37 #define CONFIG_SYS_NAND_U_BOOT_SIZE ((768 << 10) - 0x2000)
38 #define CONFIG_SYS_NAND_U_BOOT_DST (0x00200000 - CONFIG_SPL_MAX_SIZE)
39 #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000
40 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0
43 #ifndef CONFIG_RESET_VECTOR_ADDRESS
44 #define CONFIG_RESET_VECTOR_ADDRESS 0x8ffffffc
47 #ifdef CONFIG_SPL_BUILD
48 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
50 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
53 /* High Level Configuration Options */
54 #define CONFIG_SYS_HAS_SERDES /* common SERDES init code */
56 #if defined(CONFIG_PCI)
57 #define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */
58 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
59 #define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
60 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
64 * Memory space is mapped 1-1, but I/O space must start from 0.
66 /* controller 1, Slot 1, tgtid 1, Base address a000 */
67 #define CONFIG_SYS_PCIE1_NAME "PCIe Slot"
68 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x90000000
69 #define CONFIG_SYS_PCIE1_MEM_BUS 0x90000000
70 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x90000000
71 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */
72 #define CONFIG_SYS_PCIE1_IO_VIRT 0xC0010000
73 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
74 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
75 #define CONFIG_SYS_PCIE1_IO_PHYS 0xC0010000
77 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
80 #define CONFIG_ENV_OVERWRITE
82 #if defined(CONFIG_SYS_CLK_100_DDR_100)
83 #define CONFIG_SYS_CLK_FREQ 100000000
84 #define CONFIG_DDR_CLK_FREQ 100000000
85 #elif defined(CONFIG_SYS_CLK_100_DDR_133)
86 #define CONFIG_SYS_CLK_FREQ 100000000
87 #define CONFIG_DDR_CLK_FREQ 133000000
90 #define CONFIG_HWCONFIG
92 * These can be toggled for performance analysis, otherwise use default.
94 #define CONFIG_L2_CACHE /* toggle L2 cache */
95 #define CONFIG_BTB /* enable branch predition */
98 #define CONFIG_SYS_SPD_BUS_NUM 0
99 #define SPD_EEPROM_ADDRESS1 0x54 /* I2C access */
100 #define SPD_EEPROM_ADDRESS2 0x56 /* I2C access */
102 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef
104 #define CONFIG_SYS_SDRAM_SIZE (1024)
105 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
106 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
108 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
110 /* DDR3 Controller Settings */
111 #define CONFIG_CHIP_SELECTS_PER_CTRL 1
112 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003F
113 #define CONFIG_SYS_DDR_CS0_CONFIG_1333 0x80004302
114 #define CONFIG_SYS_DDR_CS0_CONFIG_800 0x80014302
115 #define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000
116 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
117 #define CONFIG_SYS_DDR_INIT_ADDR 0x00000000
118 #define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000
119 #define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000
120 #define CONFIG_SYS_DDR1_CS0_BNDS 0x0040007F
122 #define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600
123 #define CONFIG_SYS_DDR_SR_CNTR 0x00000000
124 #define CONFIG_SYS_DDR_RCW_1 0x00000000
125 #define CONFIG_SYS_DDR_RCW_2 0x00000000
126 #define CONFIG_SYS_DDR_CONTROL_800 0x470C0000
127 #define CONFIG_SYS_DDR_CONTROL_2_800 0x04401050
128 #define CONFIG_SYS_DDR_TIMING_4_800 0x00220001
129 #define CONFIG_SYS_DDR_TIMING_5_800 0x03402400
131 #define CONFIG_SYS_DDR_CONTROL_1333 0x470C0008
132 #define CONFIG_SYS_DDR_CONTROL_2_1333 0x24401010
133 #define CONFIG_SYS_DDR_TIMING_4_1333 0x00000001
134 #define CONFIG_SYS_DDR_TIMING_5_1333 0x03401400
136 #define CONFIG_SYS_DDR_TIMING_3_800 0x00020000
137 #define CONFIG_SYS_DDR_TIMING_0_800 0x00330004
138 #define CONFIG_SYS_DDR_TIMING_1_800 0x6f6B4846
139 #define CONFIG_SYS_DDR_TIMING_2_800 0x0FA8C8CF
140 #define CONFIG_SYS_DDR_CLK_CTRL_800 0x03000000
141 #define CONFIG_SYS_DDR_MODE_1_800 0x40461520
142 #define CONFIG_SYS_DDR_MODE_2_800 0x8000c000
143 #define CONFIG_SYS_DDR_INTERVAL_800 0x0C300000
144 #define CONFIG_SYS_DDR_WRLVL_CONTROL_800 0x8655A608
146 #define CONFIG_SYS_DDR_TIMING_3_1333 0x01061000
147 #define CONFIG_SYS_DDR_TIMING_0_1333 0x00440104
148 #define CONFIG_SYS_DDR_TIMING_1_1333 0x98913A45
149 #define CONFIG_SYS_DDR_TIMING_2_1333 0x0FB8B114
150 #define CONFIG_SYS_DDR_CLK_CTRL_1333 0x02800000
151 #define CONFIG_SYS_DDR_MODE_1_1333 0x00061A50
152 #define CONFIG_SYS_DDR_MODE_2_1333 0x00100000
153 #define CONFIG_SYS_DDR_INTERVAL_1333 0x144E0513
154 #define CONFIG_SYS_DDR_WRLVL_CONTROL_1333 0x8655F607
156 /*FIXME: the following params are constant w.r.t diff freq
157 combinations. this should be removed later
159 #if CONFIG_DDR_CLK_FREQ == 100000000
160 #define CONFIG_SYS_DDR_CS0_CONFIG CONFIG_SYS_DDR_CS0_CONFIG_800
161 #define CONFIG_SYS_DDR_CONTROL CONFIG_SYS_DDR_CONTROL_800
162 #define CONFIG_SYS_DDR_CONTROL_2 CONFIG_SYS_DDR_CONTROL_2_800
163 #define CONFIG_SYS_DDR_TIMING_4 CONFIG_SYS_DDR_TIMING_4_800
164 #define CONFIG_SYS_DDR_TIMING_5 CONFIG_SYS_DDR_TIMING_5_800
165 #elif CONFIG_DDR_CLK_FREQ == 133000000
166 #define CONFIG_SYS_DDR_CS0_CONFIG CONFIG_SYS_DDR_CS0_CONFIG_1333
167 #define CONFIG_SYS_DDR_CONTROL CONFIG_SYS_DDR_CONTROL_1333
168 #define CONFIG_SYS_DDR_CONTROL_2 CONFIG_SYS_DDR_CONTROL_2_1333
169 #define CONFIG_SYS_DDR_TIMING_4 CONFIG_SYS_DDR_TIMING_4_1333
170 #define CONFIG_SYS_DDR_TIMING_5 CONFIG_SYS_DDR_TIMING_5_1333
172 #define CONFIG_SYS_DDR_CS0_CONFIG CONFIG_SYS_DDR_CS0_CONFIG_800
173 #define CONFIG_SYS_DDR_CONTROL CONFIG_SYS_DDR_CONTROL_800
174 #define CONFIG_SYS_DDR_CONTROL_2 CONFIG_SYS_DDR_CONTROL_2_800
175 #define CONFIG_SYS_DDR_TIMING_4 CONFIG_SYS_DDR_TIMING_4_800
176 #define CONFIG_SYS_DDR_TIMING_5 CONFIG_SYS_DDR_TIMING_5_800
179 /* relocated CCSRBAR */
180 #define CONFIG_SYS_CCSRBAR CONFIG_SYS_CCSRBAR_DEFAULT
181 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR_DEFAULT
183 #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR
186 #define CONFIG_SYS_FSL_DSP_CCSRBAR CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT
187 #define CONFIG_SYS_FSL_DSP_CCSRBAR_PHYS CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT
192 /* NOR Flash on IFC */
194 #define CONFIG_SYS_FLASH_BASE 0x88000000
195 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* Max number of sector: 32M */
197 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
199 #define CONFIG_SYS_NOR_CSPR 0x88000101
200 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
201 #define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(5)
202 /* NOR Flash Timing Params */
204 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x01) \
205 | FTIM0_NOR_TEADC(0x03) \
206 | FTIM0_NOR_TAVDS(0x00) \
207 | FTIM0_NOR_TEAHC(0x0f))
208 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x1d) \
209 | FTIM1_NOR_TRAD_NOR(0x09) \
210 | FTIM1_NOR_TSEQRAD_NOR(0x09))
211 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x1) \
212 | FTIM2_NOR_TCH(0x4) \
213 | FTIM2_NOR_TWPH(0x7) \
214 | FTIM2_NOR_TWP(0x1e))
215 #define CONFIG_SYS_NOR_FTIM3 0x0
217 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
218 #define CONFIG_SYS_FLASH_QUIET_TEST
219 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
220 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
222 #undef CONFIG_SYS_FLASH_CHECKSUM
223 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
224 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
226 /* CFI for NOR Flash */
227 #define CONFIG_SYS_FLASH_EMPTY_INFO
229 /* NAND Flash on IFC */
230 #define CONFIG_SYS_NAND_BASE 0xff800000
231 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
233 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
234 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
235 | CSPR_MSEL_NAND /* MSEL = NAND */ \
237 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
239 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
240 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
241 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
242 | CSOR_NAND_RAL_2 /* RAL = 2Byes */ \
243 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \
244 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
245 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
247 /* NAND Flash Timing Params */
248 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x03) \
249 | FTIM0_NAND_TWP(0x05) \
250 | FTIM0_NAND_TWCHT(0x02) \
251 | FTIM0_NAND_TWH(0x04))
252 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x1c) \
253 | FTIM1_NAND_TWBE(0x1e) \
254 | FTIM1_NAND_TRR(0x07) \
255 | FTIM1_NAND_TRP(0x05))
256 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x08) \
257 | FTIM2_NAND_TREH(0x04) \
258 | FTIM2_NAND_TWHRE(0x11))
259 #define CONFIG_SYS_NAND_FTIM3 FTIM3_NAND_TWW(0x04)
261 #define CONFIG_SYS_NAND_DDR_LAW 11
264 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
265 #define CONFIG_SYS_MAX_NAND_DEVICE 1
267 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
269 #ifndef CONFIG_SPL_BUILD
270 #define CONFIG_FSL_QIXIS
272 #ifdef CONFIG_FSL_QIXIS
273 #define CONFIG_SYS_FPGA_BASE 0xffb00000
274 #define CONFIG_SYS_I2C_FPGA_ADDR 0x66
275 #define QIXIS_BASE CONFIG_SYS_FPGA_BASE
276 #define QIXIS_LBMAP_SWITCH 9
277 #define QIXIS_LBMAP_MASK 0x07
278 #define QIXIS_LBMAP_SHIFT 0
279 #define QIXIS_LBMAP_DFLTBANK 0x00
280 #define QIXIS_LBMAP_ALTBANK 0x04
281 #define QIXIS_RST_CTL_RESET 0x83
282 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
283 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21
284 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
286 #define CONFIG_SYS_FPGA_BASE_PHYS CONFIG_SYS_FPGA_BASE
288 #define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_FPGA_BASE) \
292 #define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024)
293 #define CONFIG_SYS_CSOR2 0x0
294 /* CPLD Timing parameters for IFC CS3 */
295 #define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
296 FTIM0_GPCM_TEADC(0x0e) | \
297 FTIM0_GPCM_TEAHC(0x0e))
298 #define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \
299 FTIM1_GPCM_TRAD(0x1f))
300 #define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
301 FTIM2_GPCM_TCH(0x8) | \
302 FTIM2_GPCM_TWP(0x1f))
303 #define CONFIG_SYS_CS2_FTIM3 0x0
306 /* Set up IFC registers for boot location NOR/NAND */
307 #if defined(CONFIG_MTD_RAW_NAND) || defined(CONFIG_NAND_SECBOOT)
308 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
309 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
310 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
311 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
312 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
313 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
314 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
315 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR_CSPR
316 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
317 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
318 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
319 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
320 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
321 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
323 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR
324 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
325 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
326 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
327 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
328 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
329 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
330 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR
331 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK
332 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR
333 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0
334 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1
335 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2
336 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3
339 #define CONFIG_SYS_INIT_RAM_LOCK
340 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */
341 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* End of used area in RAM */
343 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE \
344 - GENERATED_GBL_DATA_SIZE)
345 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
347 #define CONFIG_SYS_MONITOR_LEN (768 * 1024)
348 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc*/
351 #undef CONFIG_SERIAL_SOFTWARE_FIFO
352 #define CONFIG_SYS_NS16550_SERIAL
353 #define CONFIG_SYS_NS16550_REG_SIZE 1
354 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
355 #ifdef CONFIG_SPL_BUILD
356 #define CONFIG_NS16550_MIN_FUNCTIONS
359 #define CONFIG_SYS_BAUDRATE_TABLE \
360 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
362 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR + 0x4500)
363 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR + 0x4600)
364 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR + 0x4700)
365 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR + 0x4800)
367 #define CONFIG_SYS_I2C
368 #define CONFIG_SYS_I2C_FSL
369 #define CONFIG_SYS_FSL_I2C_SPEED 400800 /* I2C speed and slave address*/
370 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
371 #define CONFIG_SYS_FSL_I2C2_SPEED 400800 /* I2C speed and slave address*/
372 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
373 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
374 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
377 #define CONFIG_ID_EEPROM
378 #ifdef CONFIG_ID_EEPROM
379 #define CONFIG_SYS_I2C_EEPROM_NXID
381 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
382 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
383 #define CONFIG_SYS_EEPROM_BUS_NUM 0
385 /* enable read and write access to EEPROM */
386 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
387 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
388 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
391 #define CONFIG_I2C_FPGA
392 #define CONFIG_SYS_I2C_FPGA_ADDR 0x66
394 #define CONFIG_RTC_DS3231
395 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
398 * SPI interface will not be available in case of NAND boot SPI CS0 will be
401 /* eSPI - Enhanced SPI */
403 #if defined(CONFIG_TSEC_ENET)
405 #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */
406 #define CONFIG_TSEC1 1
407 #define CONFIG_TSEC1_NAME "eTSEC1"
408 #define CONFIG_TSEC2 1
409 #define CONFIG_TSEC2_NAME "eTSEC2"
411 #define TSEC1_PHY_ADDR 0
412 #define TSEC2_PHY_ADDR 1
414 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
415 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
417 #define TSEC1_PHYIDX 0
418 #define TSEC2_PHYIDX 0
420 #define CONFIG_ETHPRIME "eTSEC1"
422 /* TBI PHY configuration for SGMII mode */
423 #define CONFIG_TSEC_TBICR_SETTINGS ( \
425 | TBICR_ANEG_ENABLE \
426 | TBICR_FULL_DUPLEX \
430 #endif /* CONFIG_TSEC_ENET */
433 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
436 #ifdef CONFIG_USB_EHCI_HCD
437 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
438 #define CONFIG_USB_EHCI_FSL
439 #define CONFIG_HAS_FSL_DR_USB
445 #if defined(CONFIG_RAMBOOT_SDCARD)
446 #define CONFIG_FSL_FIXED_MMC_LOCATION
447 #define CONFIG_SYS_MMC_ENV_DEV 0
448 #elif defined(CONFIG_MTD_RAW_NAND) || defined(CONFIG_NAND_SECBOOT)
449 #define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE)
452 #define CONFIG_LOADS_ECHO /* echo on for serial download */
453 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
456 * Miscellaneous configurable options
458 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
461 * For booting Linux, the board info and command line data
462 * have to be in the first 64 MB of memory, since this is
463 * the maximum mapped by the Linux kernel during initialization.
465 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux */
466 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
468 #if defined(CONFIG_CMD_KGDB)
469 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
473 * Dynamic MTD Partition support with mtdparts
476 * Environment Configuration
479 #if defined(CONFIG_TSEC_ENET)
480 #define CONFIG_HAS_ETH0
481 #define CONFIG_HAS_ETH1
484 #define CONFIG_HOSTNAME "BSC9132qds"
485 #define CONFIG_ROOTPATH "/opt/nfsroot"
486 #define CONFIG_BOOTFILE "uImage"
487 #define CONFIG_UBOOTPATH "u-boot.bin"
490 #define CONFIG_DEF_HWCONFIG "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0"
492 #define CONFIG_DEF_HWCONFIG "hwconfig=sim;usb1:dr_mode=host,phy_type=ulpi\0"
495 #define CONFIG_EXTRA_ENV_SETTINGS \
497 "uboot=" CONFIG_UBOOTPATH "\0" \
498 "loadaddr=1000000\0" \
499 "bootfile=uImage\0" \
500 "consoledev=ttyS0\0" \
501 "ramdiskaddr=2000000\0" \
502 "ramdiskfile=rootfs.ext2.gz.uboot\0" \
503 "fdtaddr=1e00000\0" \
504 "fdtfile=bsc9132qds.dtb\0" \
507 "othbootargs=mem=880M ramdisk_size=600000 " \
508 "default_hugepagesz=256m hugepagesz=256m hugepages=1 " \
510 "usbext2boot=setenv bootargs root=/dev/ram rw " \
511 "console=$consoledev,$baudrate $othbootargs; " \
513 "ext2load usb 0:4 $loadaddr $bootfile;" \
514 "ext2load usb 0:4 $fdtaddr $fdtfile;" \
515 "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \
516 "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \
517 "debug_halt_off=mw ff7e0e30 0xf0000000;"
519 #define CONFIG_NFSBOOTCOMMAND \
520 "setenv bootargs root=/dev/nfs rw " \
521 "nfsroot=$serverip:$rootpath " \
522 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
523 "console=$consoledev,$baudrate $othbootargs;" \
524 "tftp $loadaddr $bootfile;" \
525 "tftp $fdtaddr $fdtfile;" \
526 "bootm $loadaddr - $fdtaddr"
528 #define CONFIG_HDBOOT \
529 "setenv bootargs root=/dev/$bdev rw rootdelay=30 " \
530 "console=$consoledev,$baudrate $othbootargs;" \
532 "ext2load usb 0:1 $loadaddr /boot/$bootfile;" \
533 "ext2load usb 0:1 $fdtaddr /boot/$fdtfile;" \
534 "bootm $loadaddr - $fdtaddr"
536 #define CONFIG_RAMBOOTCOMMAND \
537 "setenv bootargs root=/dev/ram rw " \
538 "console=$consoledev,$baudrate $othbootargs; " \
539 "tftp $ramdiskaddr $ramdiskfile;" \
540 "tftp $loadaddr $bootfile;" \
541 "tftp $fdtaddr $fdtfile;" \
542 "bootm $loadaddr $ramdiskaddr $fdtaddr"
544 #define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND
546 #include <asm/fsl_secure_boot.h>
548 #endif /* __CONFIG_H */