1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2013 Freescale Semiconductor, Inc.
7 * BSC9132 QDS board configuration file
14 #define CONFIG_RAMBOOT_SDCARD
15 #define CONFIG_SYS_RAMBOOT
16 #define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc
18 #ifdef CONFIG_SPIFLASH
19 #define CONFIG_RAMBOOT_SPIFLASH
20 #define CONFIG_SYS_RAMBOOT
21 #define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc
23 #ifdef CONFIG_NAND_SECBOOT
24 #define CONFIG_RAMBOOT_NAND
25 #define CONFIG_SYS_RAMBOOT
26 #define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc
30 #define CONFIG_SPL_INIT_MINIMAL
31 #define CONFIG_SPL_FLUSH_IMAGE
32 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
34 #define CONFIG_SPL_MAX_SIZE 8192
35 #define CONFIG_SPL_RELOC_TEXT_BASE 0x00100000
36 #define CONFIG_SPL_RELOC_STACK 0x00100000
37 #define CONFIG_SYS_NAND_U_BOOT_SIZE ((768 << 10) - 0x2000)
38 #define CONFIG_SYS_NAND_U_BOOT_DST (0x00200000 - CONFIG_SPL_MAX_SIZE)
39 #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000
40 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0
41 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
44 #ifndef CONFIG_RESET_VECTOR_ADDRESS
45 #define CONFIG_RESET_VECTOR_ADDRESS 0x8ffffffc
48 #ifdef CONFIG_SPL_BUILD
49 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
51 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
54 /* High Level Configuration Options */
55 #define CONFIG_SYS_HAS_SERDES /* common SERDES init code */
57 #if defined(CONFIG_PCI)
58 #define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */
59 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
60 #define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
61 #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */
62 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
66 * Memory space is mapped 1-1, but I/O space must start from 0.
68 /* controller 1, Slot 1, tgtid 1, Base address a000 */
69 #define CONFIG_SYS_PCIE1_NAME "PCIe Slot"
70 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x90000000
71 #define CONFIG_SYS_PCIE1_MEM_BUS 0x90000000
72 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x90000000
73 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */
74 #define CONFIG_SYS_PCIE1_IO_VIRT 0xC0010000
75 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
76 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
77 #define CONFIG_SYS_PCIE1_IO_PHYS 0xC0010000
79 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
82 #define CONFIG_ENV_OVERWRITE
84 #if defined(CONFIG_SYS_CLK_100_DDR_100)
85 #define CONFIG_SYS_CLK_FREQ 100000000
86 #define CONFIG_DDR_CLK_FREQ 100000000
87 #elif defined(CONFIG_SYS_CLK_100_DDR_133)
88 #define CONFIG_SYS_CLK_FREQ 100000000
89 #define CONFIG_DDR_CLK_FREQ 133000000
92 #define CONFIG_HWCONFIG
94 * These can be toggled for performance analysis, otherwise use default.
96 #define CONFIG_L2_CACHE /* toggle L2 cache */
97 #define CONFIG_BTB /* enable branch predition */
99 #define CONFIG_SYS_MEMTEST_START 0x01000000 /* memtest works on */
100 #define CONFIG_SYS_MEMTEST_END 0x01ffffff
103 #define CONFIG_SYS_SPD_BUS_NUM 0
104 #define SPD_EEPROM_ADDRESS1 0x54 /* I2C access */
105 #define SPD_EEPROM_ADDRESS2 0x56 /* I2C access */
107 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef
109 #define CONFIG_SYS_SDRAM_SIZE (1024)
110 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
111 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
113 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
115 /* DDR3 Controller Settings */
116 #define CONFIG_CHIP_SELECTS_PER_CTRL 1
117 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003F
118 #define CONFIG_SYS_DDR_CS0_CONFIG_1333 0x80004302
119 #define CONFIG_SYS_DDR_CS0_CONFIG_800 0x80014302
120 #define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000
121 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
122 #define CONFIG_SYS_DDR_INIT_ADDR 0x00000000
123 #define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000
124 #define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000
125 #define CONFIG_SYS_DDR1_CS0_BNDS 0x0040007F
127 #define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600
128 #define CONFIG_SYS_DDR_SR_CNTR 0x00000000
129 #define CONFIG_SYS_DDR_RCW_1 0x00000000
130 #define CONFIG_SYS_DDR_RCW_2 0x00000000
131 #define CONFIG_SYS_DDR_CONTROL_800 0x470C0000
132 #define CONFIG_SYS_DDR_CONTROL_2_800 0x04401050
133 #define CONFIG_SYS_DDR_TIMING_4_800 0x00220001
134 #define CONFIG_SYS_DDR_TIMING_5_800 0x03402400
136 #define CONFIG_SYS_DDR_CONTROL_1333 0x470C0008
137 #define CONFIG_SYS_DDR_CONTROL_2_1333 0x24401010
138 #define CONFIG_SYS_DDR_TIMING_4_1333 0x00000001
139 #define CONFIG_SYS_DDR_TIMING_5_1333 0x03401400
141 #define CONFIG_SYS_DDR_TIMING_3_800 0x00020000
142 #define CONFIG_SYS_DDR_TIMING_0_800 0x00330004
143 #define CONFIG_SYS_DDR_TIMING_1_800 0x6f6B4846
144 #define CONFIG_SYS_DDR_TIMING_2_800 0x0FA8C8CF
145 #define CONFIG_SYS_DDR_CLK_CTRL_800 0x03000000
146 #define CONFIG_SYS_DDR_MODE_1_800 0x40461520
147 #define CONFIG_SYS_DDR_MODE_2_800 0x8000c000
148 #define CONFIG_SYS_DDR_INTERVAL_800 0x0C300000
149 #define CONFIG_SYS_DDR_WRLVL_CONTROL_800 0x8655A608
151 #define CONFIG_SYS_DDR_TIMING_3_1333 0x01061000
152 #define CONFIG_SYS_DDR_TIMING_0_1333 0x00440104
153 #define CONFIG_SYS_DDR_TIMING_1_1333 0x98913A45
154 #define CONFIG_SYS_DDR_TIMING_2_1333 0x0FB8B114
155 #define CONFIG_SYS_DDR_CLK_CTRL_1333 0x02800000
156 #define CONFIG_SYS_DDR_MODE_1_1333 0x00061A50
157 #define CONFIG_SYS_DDR_MODE_2_1333 0x00100000
158 #define CONFIG_SYS_DDR_INTERVAL_1333 0x144E0513
159 #define CONFIG_SYS_DDR_WRLVL_CONTROL_1333 0x8655F607
161 /*FIXME: the following params are constant w.r.t diff freq
162 combinations. this should be removed later
164 #if CONFIG_DDR_CLK_FREQ == 100000000
165 #define CONFIG_SYS_DDR_CS0_CONFIG CONFIG_SYS_DDR_CS0_CONFIG_800
166 #define CONFIG_SYS_DDR_CONTROL CONFIG_SYS_DDR_CONTROL_800
167 #define CONFIG_SYS_DDR_CONTROL_2 CONFIG_SYS_DDR_CONTROL_2_800
168 #define CONFIG_SYS_DDR_TIMING_4 CONFIG_SYS_DDR_TIMING_4_800
169 #define CONFIG_SYS_DDR_TIMING_5 CONFIG_SYS_DDR_TIMING_5_800
170 #elif CONFIG_DDR_CLK_FREQ == 133000000
171 #define CONFIG_SYS_DDR_CS0_CONFIG CONFIG_SYS_DDR_CS0_CONFIG_1333
172 #define CONFIG_SYS_DDR_CONTROL CONFIG_SYS_DDR_CONTROL_1333
173 #define CONFIG_SYS_DDR_CONTROL_2 CONFIG_SYS_DDR_CONTROL_2_1333
174 #define CONFIG_SYS_DDR_TIMING_4 CONFIG_SYS_DDR_TIMING_4_1333
175 #define CONFIG_SYS_DDR_TIMING_5 CONFIG_SYS_DDR_TIMING_5_1333
177 #define CONFIG_SYS_DDR_CS0_CONFIG CONFIG_SYS_DDR_CS0_CONFIG_800
178 #define CONFIG_SYS_DDR_CONTROL CONFIG_SYS_DDR_CONTROL_800
179 #define CONFIG_SYS_DDR_CONTROL_2 CONFIG_SYS_DDR_CONTROL_2_800
180 #define CONFIG_SYS_DDR_TIMING_4 CONFIG_SYS_DDR_TIMING_4_800
181 #define CONFIG_SYS_DDR_TIMING_5 CONFIG_SYS_DDR_TIMING_5_800
184 /* relocated CCSRBAR */
185 #define CONFIG_SYS_CCSRBAR CONFIG_SYS_CCSRBAR_DEFAULT
186 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR_DEFAULT
188 #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR
191 #define CONFIG_SYS_FSL_DSP_CCSRBAR CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT
192 #define CONFIG_SYS_FSL_DSP_CCSRBAR_PHYS CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT
197 /* NOR Flash on IFC */
199 #define CONFIG_SYS_FLASH_BASE 0x88000000
200 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* Max number of sector: 32M */
202 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
204 #define CONFIG_SYS_NOR_CSPR 0x88000101
205 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
206 #define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(5)
207 /* NOR Flash Timing Params */
209 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x01) \
210 | FTIM0_NOR_TEADC(0x03) \
211 | FTIM0_NOR_TAVDS(0x00) \
212 | FTIM0_NOR_TEAHC(0x0f))
213 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x1d) \
214 | FTIM1_NOR_TRAD_NOR(0x09) \
215 | FTIM1_NOR_TSEQRAD_NOR(0x09))
216 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x1) \
217 | FTIM2_NOR_TCH(0x4) \
218 | FTIM2_NOR_TWPH(0x7) \
219 | FTIM2_NOR_TWP(0x1e))
220 #define CONFIG_SYS_NOR_FTIM3 0x0
222 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
223 #define CONFIG_SYS_FLASH_QUIET_TEST
224 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
225 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
227 #undef CONFIG_SYS_FLASH_CHECKSUM
228 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
229 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
231 /* CFI for NOR Flash */
232 #define CONFIG_SYS_FLASH_EMPTY_INFO
234 /* NAND Flash on IFC */
235 #define CONFIG_SYS_NAND_BASE 0xff800000
236 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
238 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
239 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
240 | CSPR_MSEL_NAND /* MSEL = NAND */ \
242 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
244 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
245 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
246 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
247 | CSOR_NAND_RAL_2 /* RAL = 2Byes */ \
248 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \
249 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
250 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
252 /* NAND Flash Timing Params */
253 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x03) \
254 | FTIM0_NAND_TWP(0x05) \
255 | FTIM0_NAND_TWCHT(0x02) \
256 | FTIM0_NAND_TWH(0x04))
257 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x1c) \
258 | FTIM1_NAND_TWBE(0x1e) \
259 | FTIM1_NAND_TRR(0x07) \
260 | FTIM1_NAND_TRP(0x05))
261 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x08) \
262 | FTIM2_NAND_TREH(0x04) \
263 | FTIM2_NAND_TWHRE(0x11))
264 #define CONFIG_SYS_NAND_FTIM3 FTIM3_NAND_TWW(0x04)
266 #define CONFIG_SYS_NAND_DDR_LAW 11
269 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
270 #define CONFIG_SYS_MAX_NAND_DEVICE 1
272 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
274 #ifndef CONFIG_SPL_BUILD
275 #define CONFIG_FSL_QIXIS
277 #ifdef CONFIG_FSL_QIXIS
278 #define CONFIG_SYS_FPGA_BASE 0xffb00000
279 #define CONFIG_SYS_I2C_FPGA_ADDR 0x66
280 #define QIXIS_BASE CONFIG_SYS_FPGA_BASE
281 #define QIXIS_LBMAP_SWITCH 9
282 #define QIXIS_LBMAP_MASK 0x07
283 #define QIXIS_LBMAP_SHIFT 0
284 #define QIXIS_LBMAP_DFLTBANK 0x00
285 #define QIXIS_LBMAP_ALTBANK 0x04
286 #define QIXIS_RST_CTL_RESET 0x83
287 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
288 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21
289 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
291 #define CONFIG_SYS_FPGA_BASE_PHYS CONFIG_SYS_FPGA_BASE
293 #define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_FPGA_BASE) \
297 #define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024)
298 #define CONFIG_SYS_CSOR2 0x0
299 /* CPLD Timing parameters for IFC CS3 */
300 #define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
301 FTIM0_GPCM_TEADC(0x0e) | \
302 FTIM0_GPCM_TEAHC(0x0e))
303 #define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \
304 FTIM1_GPCM_TRAD(0x1f))
305 #define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
306 FTIM2_GPCM_TCH(0x8) | \
307 FTIM2_GPCM_TWP(0x1f))
308 #define CONFIG_SYS_CS2_FTIM3 0x0
311 /* Set up IFC registers for boot location NOR/NAND */
312 #if defined(CONFIG_NAND) || defined(CONFIG_NAND_SECBOOT)
313 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
314 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
315 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
316 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
317 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
318 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
319 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
320 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR_CSPR
321 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
322 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
323 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
324 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
325 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
326 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
328 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR
329 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
330 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
331 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
332 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
333 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
334 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
335 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR
336 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK
337 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR
338 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0
339 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1
340 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2
341 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3
344 #define CONFIG_SYS_INIT_RAM_LOCK
345 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */
346 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* End of used area in RAM */
348 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE \
349 - GENERATED_GBL_DATA_SIZE)
350 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
352 #define CONFIG_SYS_MONITOR_LEN (768 * 1024)
353 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc*/
356 #undef CONFIG_SERIAL_SOFTWARE_FIFO
357 #define CONFIG_SYS_NS16550_SERIAL
358 #define CONFIG_SYS_NS16550_REG_SIZE 1
359 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
360 #ifdef CONFIG_SPL_BUILD
361 #define CONFIG_NS16550_MIN_FUNCTIONS
364 #define CONFIG_SYS_BAUDRATE_TABLE \
365 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
367 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR + 0x4500)
368 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR + 0x4600)
369 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR + 0x4700)
370 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR + 0x4800)
372 #define CONFIG_SYS_I2C
373 #define CONFIG_SYS_I2C_FSL
374 #define CONFIG_SYS_FSL_I2C_SPEED 400800 /* I2C speed and slave address*/
375 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
376 #define CONFIG_SYS_FSL_I2C2_SPEED 400800 /* I2C speed and slave address*/
377 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
378 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
379 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
382 #define CONFIG_ID_EEPROM
383 #ifdef CONFIG_ID_EEPROM
384 #define CONFIG_SYS_I2C_EEPROM_NXID
386 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
387 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
388 #define CONFIG_SYS_EEPROM_BUS_NUM 0
390 /* enable read and write access to EEPROM */
391 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
392 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
393 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
396 #define CONFIG_I2C_FPGA
397 #define CONFIG_SYS_I2C_FPGA_ADDR 0x66
399 #define CONFIG_RTC_DS3231
400 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
403 * SPI interface will not be available in case of NAND boot SPI CS0 will be
406 /* eSPI - Enhanced SPI */
408 #if defined(CONFIG_TSEC_ENET)
410 #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */
411 #define CONFIG_TSEC1 1
412 #define CONFIG_TSEC1_NAME "eTSEC1"
413 #define CONFIG_TSEC2 1
414 #define CONFIG_TSEC2_NAME "eTSEC2"
416 #define TSEC1_PHY_ADDR 0
417 #define TSEC2_PHY_ADDR 1
419 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
420 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
422 #define TSEC1_PHYIDX 0
423 #define TSEC2_PHYIDX 0
425 #define CONFIG_ETHPRIME "eTSEC1"
427 /* TBI PHY configuration for SGMII mode */
428 #define CONFIG_TSEC_TBICR_SETTINGS ( \
430 | TBICR_ANEG_ENABLE \
431 | TBICR_FULL_DUPLEX \
435 #endif /* CONFIG_TSEC_ENET */
438 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
441 #ifdef CONFIG_USB_EHCI_HCD
442 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
443 #define CONFIG_USB_EHCI_FSL
444 #define CONFIG_HAS_FSL_DR_USB
450 #if defined(CONFIG_RAMBOOT_SDCARD)
451 #define CONFIG_FSL_FIXED_MMC_LOCATION
452 #define CONFIG_SYS_MMC_ENV_DEV 0
453 #define CONFIG_ENV_SIZE 0x2000
454 #elif defined(CONFIG_RAMBOOT_SPIFLASH)
455 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
456 #define CONFIG_ENV_SECT_SIZE 0x10000
457 #define CONFIG_ENV_SIZE 0x2000
458 #elif defined(CONFIG_NAND) || defined(CONFIG_NAND_SECBOOT)
459 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
460 #define CONFIG_ENV_OFFSET ((768 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE)
461 #define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE)
462 #elif defined(CONFIG_SYS_RAMBOOT)
463 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
464 #define CONFIG_ENV_SIZE 0x2000
466 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
467 #define CONFIG_ENV_SIZE 0x2000
468 #define CONFIG_ENV_SECT_SIZE 0x20000
471 #define CONFIG_LOADS_ECHO /* echo on for serial download */
472 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
475 * Miscellaneous configurable options
477 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
480 * For booting Linux, the board info and command line data
481 * have to be in the first 64 MB of memory, since this is
482 * the maximum mapped by the Linux kernel during initialization.
484 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux */
485 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
487 #if defined(CONFIG_CMD_KGDB)
488 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
492 * Dynamic MTD Partition support with mtdparts
495 * Environment Configuration
498 #if defined(CONFIG_TSEC_ENET)
499 #define CONFIG_HAS_ETH0
500 #define CONFIG_HAS_ETH1
503 #define CONFIG_HOSTNAME "BSC9132qds"
504 #define CONFIG_ROOTPATH "/opt/nfsroot"
505 #define CONFIG_BOOTFILE "uImage"
506 #define CONFIG_UBOOTPATH "u-boot.bin"
509 #define CONFIG_DEF_HWCONFIG "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0"
511 #define CONFIG_DEF_HWCONFIG "hwconfig=sim;usb1:dr_mode=host,phy_type=ulpi\0"
514 #define CONFIG_EXTRA_ENV_SETTINGS \
516 "uboot=" CONFIG_UBOOTPATH "\0" \
517 "loadaddr=1000000\0" \
518 "bootfile=uImage\0" \
519 "consoledev=ttyS0\0" \
520 "ramdiskaddr=2000000\0" \
521 "ramdiskfile=rootfs.ext2.gz.uboot\0" \
522 "fdtaddr=1e00000\0" \
523 "fdtfile=bsc9132qds.dtb\0" \
526 "othbootargs=mem=880M ramdisk_size=600000 " \
527 "default_hugepagesz=256m hugepagesz=256m hugepages=1 " \
529 "usbext2boot=setenv bootargs root=/dev/ram rw " \
530 "console=$consoledev,$baudrate $othbootargs; " \
532 "ext2load usb 0:4 $loadaddr $bootfile;" \
533 "ext2load usb 0:4 $fdtaddr $fdtfile;" \
534 "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \
535 "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \
536 "debug_halt_off=mw ff7e0e30 0xf0000000;"
538 #define CONFIG_NFSBOOTCOMMAND \
539 "setenv bootargs root=/dev/nfs rw " \
540 "nfsroot=$serverip:$rootpath " \
541 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
542 "console=$consoledev,$baudrate $othbootargs;" \
543 "tftp $loadaddr $bootfile;" \
544 "tftp $fdtaddr $fdtfile;" \
545 "bootm $loadaddr - $fdtaddr"
547 #define CONFIG_HDBOOT \
548 "setenv bootargs root=/dev/$bdev rw rootdelay=30 " \
549 "console=$consoledev,$baudrate $othbootargs;" \
551 "ext2load usb 0:1 $loadaddr /boot/$bootfile;" \
552 "ext2load usb 0:1 $fdtaddr /boot/$fdtfile;" \
553 "bootm $loadaddr - $fdtaddr"
555 #define CONFIG_RAMBOOTCOMMAND \
556 "setenv bootargs root=/dev/ram rw " \
557 "console=$consoledev,$baudrate $othbootargs; " \
558 "tftp $ramdiskaddr $ramdiskfile;" \
559 "tftp $loadaddr $bootfile;" \
560 "tftp $fdtaddr $fdtfile;" \
561 "bootm $loadaddr $ramdiskaddr $fdtaddr"
563 #define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND
565 #include <asm/fsl_secure_boot.h>
567 #endif /* __CONFIG_H */