1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2013 Freescale Semiconductor, Inc.
7 * BSC9132 QDS board configuration file
13 #define CONFIG_MISC_INIT_R
16 #define CONFIG_RAMBOOT_SDCARD
17 #define CONFIG_SYS_RAMBOOT
18 #define CONFIG_SYS_EXTRA_ENV_RELOC
19 #define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc
21 #ifdef CONFIG_SPIFLASH
22 #define CONFIG_RAMBOOT_SPIFLASH
23 #define CONFIG_SYS_RAMBOOT
24 #define CONFIG_SYS_EXTRA_ENV_RELOC
25 #define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc
27 #ifdef CONFIG_NAND_SECBOOT
28 #define CONFIG_RAMBOOT_NAND
29 #define CONFIG_SYS_RAMBOOT
30 #define CONFIG_SYS_EXTRA_ENV_RELOC
31 #define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc
35 #define CONFIG_SPL_INIT_MINIMAL
36 #define CONFIG_SPL_NAND_BOOT
37 #define CONFIG_SPL_FLUSH_IMAGE
38 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
40 #define CONFIG_SPL_TEXT_BASE 0xFFFFE000
41 #define CONFIG_SPL_MAX_SIZE 8192
42 #define CONFIG_SPL_RELOC_TEXT_BASE 0x00100000
43 #define CONFIG_SPL_RELOC_STACK 0x00100000
44 #define CONFIG_SYS_NAND_U_BOOT_SIZE ((768 << 10) - 0x2000)
45 #define CONFIG_SYS_NAND_U_BOOT_DST (0x00200000 - CONFIG_SPL_MAX_SIZE)
46 #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000
47 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0
48 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
51 #ifndef CONFIG_RESET_VECTOR_ADDRESS
52 #define CONFIG_RESET_VECTOR_ADDRESS 0x8ffffffc
55 #ifdef CONFIG_SPL_BUILD
56 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
58 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
61 /* High Level Configuration Options */
62 #define CONFIG_SYS_HAS_SERDES /* common SERDES init code */
64 #if defined(CONFIG_PCI)
65 #define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */
66 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
67 #define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
68 #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */
69 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
73 * Memory space is mapped 1-1, but I/O space must start from 0.
75 /* controller 1, Slot 1, tgtid 1, Base address a000 */
76 #define CONFIG_SYS_PCIE1_NAME "PCIe Slot"
77 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x90000000
78 #define CONFIG_SYS_PCIE1_MEM_BUS 0x90000000
79 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x90000000
80 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */
81 #define CONFIG_SYS_PCIE1_IO_VIRT 0xC0010000
82 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
83 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
84 #define CONFIG_SYS_PCIE1_IO_PHYS 0xC0010000
86 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
89 #define CONFIG_ENV_OVERWRITE
91 #if defined(CONFIG_SYS_CLK_100_DDR_100)
92 #define CONFIG_SYS_CLK_FREQ 100000000
93 #define CONFIG_DDR_CLK_FREQ 100000000
94 #elif defined(CONFIG_SYS_CLK_100_DDR_133)
95 #define CONFIG_SYS_CLK_FREQ 100000000
96 #define CONFIG_DDR_CLK_FREQ 133000000
99 #define CONFIG_HWCONFIG
101 * These can be toggled for performance analysis, otherwise use default.
103 #define CONFIG_L2_CACHE /* toggle L2 cache */
104 #define CONFIG_BTB /* enable branch predition */
106 #define CONFIG_SYS_MEMTEST_START 0x01000000 /* memtest works on */
107 #define CONFIG_SYS_MEMTEST_END 0x01ffffff
110 #define CONFIG_SYS_SPD_BUS_NUM 0
111 #define SPD_EEPROM_ADDRESS1 0x54 /* I2C access */
112 #define SPD_EEPROM_ADDRESS2 0x56 /* I2C access */
113 #define CONFIG_FSL_DDR_INTERACTIVE
115 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef
117 #define CONFIG_SYS_SDRAM_SIZE (1024)
118 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
119 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
121 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
123 /* DDR3 Controller Settings */
124 #define CONFIG_CHIP_SELECTS_PER_CTRL 1
125 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003F
126 #define CONFIG_SYS_DDR_CS0_CONFIG_1333 0x80004302
127 #define CONFIG_SYS_DDR_CS0_CONFIG_800 0x80014302
128 #define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000
129 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
130 #define CONFIG_SYS_DDR_INIT_ADDR 0x00000000
131 #define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000
132 #define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000
133 #define CONFIG_SYS_DDR1_CS0_BNDS 0x0040007F
135 #define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600
136 #define CONFIG_SYS_DDR_SR_CNTR 0x00000000
137 #define CONFIG_SYS_DDR_RCW_1 0x00000000
138 #define CONFIG_SYS_DDR_RCW_2 0x00000000
139 #define CONFIG_SYS_DDR_CONTROL_800 0x470C0000
140 #define CONFIG_SYS_DDR_CONTROL_2_800 0x04401050
141 #define CONFIG_SYS_DDR_TIMING_4_800 0x00220001
142 #define CONFIG_SYS_DDR_TIMING_5_800 0x03402400
144 #define CONFIG_SYS_DDR_CONTROL_1333 0x470C0008
145 #define CONFIG_SYS_DDR_CONTROL_2_1333 0x24401010
146 #define CONFIG_SYS_DDR_TIMING_4_1333 0x00000001
147 #define CONFIG_SYS_DDR_TIMING_5_1333 0x03401400
149 #define CONFIG_SYS_DDR_TIMING_3_800 0x00020000
150 #define CONFIG_SYS_DDR_TIMING_0_800 0x00330004
151 #define CONFIG_SYS_DDR_TIMING_1_800 0x6f6B4846
152 #define CONFIG_SYS_DDR_TIMING_2_800 0x0FA8C8CF
153 #define CONFIG_SYS_DDR_CLK_CTRL_800 0x03000000
154 #define CONFIG_SYS_DDR_MODE_1_800 0x40461520
155 #define CONFIG_SYS_DDR_MODE_2_800 0x8000c000
156 #define CONFIG_SYS_DDR_INTERVAL_800 0x0C300000
157 #define CONFIG_SYS_DDR_WRLVL_CONTROL_800 0x8655A608
159 #define CONFIG_SYS_DDR_TIMING_3_1333 0x01061000
160 #define CONFIG_SYS_DDR_TIMING_0_1333 0x00440104
161 #define CONFIG_SYS_DDR_TIMING_1_1333 0x98913A45
162 #define CONFIG_SYS_DDR_TIMING_2_1333 0x0FB8B114
163 #define CONFIG_SYS_DDR_CLK_CTRL_1333 0x02800000
164 #define CONFIG_SYS_DDR_MODE_1_1333 0x00061A50
165 #define CONFIG_SYS_DDR_MODE_2_1333 0x00100000
166 #define CONFIG_SYS_DDR_INTERVAL_1333 0x144E0513
167 #define CONFIG_SYS_DDR_WRLVL_CONTROL_1333 0x8655F607
169 /*FIXME: the following params are constant w.r.t diff freq
170 combinations. this should be removed later
172 #if CONFIG_DDR_CLK_FREQ == 100000000
173 #define CONFIG_SYS_DDR_CS0_CONFIG CONFIG_SYS_DDR_CS0_CONFIG_800
174 #define CONFIG_SYS_DDR_CONTROL CONFIG_SYS_DDR_CONTROL_800
175 #define CONFIG_SYS_DDR_CONTROL_2 CONFIG_SYS_DDR_CONTROL_2_800
176 #define CONFIG_SYS_DDR_TIMING_4 CONFIG_SYS_DDR_TIMING_4_800
177 #define CONFIG_SYS_DDR_TIMING_5 CONFIG_SYS_DDR_TIMING_5_800
178 #elif CONFIG_DDR_CLK_FREQ == 133000000
179 #define CONFIG_SYS_DDR_CS0_CONFIG CONFIG_SYS_DDR_CS0_CONFIG_1333
180 #define CONFIG_SYS_DDR_CONTROL CONFIG_SYS_DDR_CONTROL_1333
181 #define CONFIG_SYS_DDR_CONTROL_2 CONFIG_SYS_DDR_CONTROL_2_1333
182 #define CONFIG_SYS_DDR_TIMING_4 CONFIG_SYS_DDR_TIMING_4_1333
183 #define CONFIG_SYS_DDR_TIMING_5 CONFIG_SYS_DDR_TIMING_5_1333
185 #define CONFIG_SYS_DDR_CS0_CONFIG CONFIG_SYS_DDR_CS0_CONFIG_800
186 #define CONFIG_SYS_DDR_CONTROL CONFIG_SYS_DDR_CONTROL_800
187 #define CONFIG_SYS_DDR_CONTROL_2 CONFIG_SYS_DDR_CONTROL_2_800
188 #define CONFIG_SYS_DDR_TIMING_4 CONFIG_SYS_DDR_TIMING_4_800
189 #define CONFIG_SYS_DDR_TIMING_5 CONFIG_SYS_DDR_TIMING_5_800
192 /* relocated CCSRBAR */
193 #define CONFIG_SYS_CCSRBAR CONFIG_SYS_CCSRBAR_DEFAULT
194 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR_DEFAULT
196 #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR
199 #define CONFIG_SYS_FSL_DSP_CCSRBAR CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT
200 #define CONFIG_SYS_FSL_DSP_CCSRBAR_PHYS CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT
205 /* NOR Flash on IFC */
207 #define CONFIG_SYS_FLASH_BASE 0x88000000
208 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* Max number of sector: 32M */
210 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
212 #define CONFIG_SYS_NOR_CSPR 0x88000101
213 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
214 #define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(5)
215 /* NOR Flash Timing Params */
217 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x01) \
218 | FTIM0_NOR_TEADC(0x03) \
219 | FTIM0_NOR_TAVDS(0x00) \
220 | FTIM0_NOR_TEAHC(0x0f))
221 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x1d) \
222 | FTIM1_NOR_TRAD_NOR(0x09) \
223 | FTIM1_NOR_TSEQRAD_NOR(0x09))
224 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x1) \
225 | FTIM2_NOR_TCH(0x4) \
226 | FTIM2_NOR_TWPH(0x7) \
227 | FTIM2_NOR_TWP(0x1e))
228 #define CONFIG_SYS_NOR_FTIM3 0x0
230 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
231 #define CONFIG_SYS_FLASH_QUIET_TEST
232 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
233 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
235 #undef CONFIG_SYS_FLASH_CHECKSUM
236 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
237 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
239 /* CFI for NOR Flash */
240 #define CONFIG_FLASH_CFI_DRIVER
241 #define CONFIG_SYS_FLASH_CFI
242 #define CONFIG_SYS_FLASH_EMPTY_INFO
243 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
245 /* NAND Flash on IFC */
246 #define CONFIG_SYS_NAND_BASE 0xff800000
247 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
249 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
250 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
251 | CSPR_MSEL_NAND /* MSEL = NAND */ \
253 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
255 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
256 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
257 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
258 | CSOR_NAND_RAL_2 /* RAL = 2Byes */ \
259 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \
260 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
261 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
263 /* NAND Flash Timing Params */
264 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x03) \
265 | FTIM0_NAND_TWP(0x05) \
266 | FTIM0_NAND_TWCHT(0x02) \
267 | FTIM0_NAND_TWH(0x04))
268 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x1c) \
269 | FTIM1_NAND_TWBE(0x1e) \
270 | FTIM1_NAND_TRR(0x07) \
271 | FTIM1_NAND_TRP(0x05))
272 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x08) \
273 | FTIM2_NAND_TREH(0x04) \
274 | FTIM2_NAND_TWHRE(0x11))
275 #define CONFIG_SYS_NAND_FTIM3 FTIM3_NAND_TWW(0x04)
277 #define CONFIG_SYS_NAND_DDR_LAW 11
280 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
281 #define CONFIG_SYS_MAX_NAND_DEVICE 1
283 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
285 #ifndef CONFIG_SPL_BUILD
286 #define CONFIG_FSL_QIXIS
288 #ifdef CONFIG_FSL_QIXIS
289 #define CONFIG_SYS_FPGA_BASE 0xffb00000
290 #define CONFIG_SYS_I2C_FPGA_ADDR 0x66
291 #define QIXIS_BASE CONFIG_SYS_FPGA_BASE
292 #define QIXIS_LBMAP_SWITCH 9
293 #define QIXIS_LBMAP_MASK 0x07
294 #define QIXIS_LBMAP_SHIFT 0
295 #define QIXIS_LBMAP_DFLTBANK 0x00
296 #define QIXIS_LBMAP_ALTBANK 0x04
297 #define QIXIS_RST_CTL_RESET 0x83
298 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
299 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21
300 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
302 #define CONFIG_SYS_FPGA_BASE_PHYS CONFIG_SYS_FPGA_BASE
304 #define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_FPGA_BASE) \
308 #define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024)
309 #define CONFIG_SYS_CSOR2 0x0
310 /* CPLD Timing parameters for IFC CS3 */
311 #define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
312 FTIM0_GPCM_TEADC(0x0e) | \
313 FTIM0_GPCM_TEAHC(0x0e))
314 #define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \
315 FTIM1_GPCM_TRAD(0x1f))
316 #define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
317 FTIM2_GPCM_TCH(0x8) | \
318 FTIM2_GPCM_TWP(0x1f))
319 #define CONFIG_SYS_CS2_FTIM3 0x0
322 /* Set up IFC registers for boot location NOR/NAND */
323 #if defined(CONFIG_NAND) || defined(CONFIG_NAND_SECBOOT)
324 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
325 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
326 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
327 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
328 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
329 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
330 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
331 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR_CSPR
332 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
333 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
334 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
335 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
336 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
337 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
339 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR
340 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
341 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
342 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
343 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
344 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
345 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
346 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR
347 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK
348 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR
349 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0
350 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1
351 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2
352 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3
355 #define CONFIG_SYS_INIT_RAM_LOCK
356 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */
357 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* End of used area in RAM */
359 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE \
360 - GENERATED_GBL_DATA_SIZE)
361 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
363 #define CONFIG_SYS_MONITOR_LEN (768 * 1024)
364 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc*/
367 #undef CONFIG_SERIAL_SOFTWARE_FIFO
368 #define CONFIG_SYS_NS16550_SERIAL
369 #define CONFIG_SYS_NS16550_REG_SIZE 1
370 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
371 #ifdef CONFIG_SPL_BUILD
372 #define CONFIG_NS16550_MIN_FUNCTIONS
375 #define CONFIG_SYS_BAUDRATE_TABLE \
376 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
378 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR + 0x4500)
379 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR + 0x4600)
380 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR + 0x4700)
381 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR + 0x4800)
383 #define CONFIG_SYS_I2C
384 #define CONFIG_SYS_I2C_FSL
385 #define CONFIG_SYS_FSL_I2C_SPEED 400800 /* I2C speed and slave address*/
386 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
387 #define CONFIG_SYS_FSL_I2C2_SPEED 400800 /* I2C speed and slave address*/
388 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
389 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
390 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
393 #define CONFIG_ID_EEPROM
394 #ifdef CONFIG_ID_EEPROM
395 #define CONFIG_SYS_I2C_EEPROM_NXID
397 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
398 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
399 #define CONFIG_SYS_EEPROM_BUS_NUM 0
401 /* enable read and write access to EEPROM */
402 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
403 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
404 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
407 #define CONFIG_I2C_FPGA
408 #define CONFIG_SYS_I2C_FPGA_ADDR 0x66
410 #define CONFIG_RTC_DS3231
411 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
414 * SPI interface will not be available in case of NAND boot SPI CS0 will be
417 /* eSPI - Enhanced SPI */
418 #ifdef CONFIG_FSL_ESPI
419 #define CONFIG_SF_DEFAULT_SPEED 10000000
420 #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
423 #if defined(CONFIG_TSEC_ENET)
425 #define CONFIG_MII /* MII PHY management */
426 #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */
427 #define CONFIG_TSEC1 1
428 #define CONFIG_TSEC1_NAME "eTSEC1"
429 #define CONFIG_TSEC2 1
430 #define CONFIG_TSEC2_NAME "eTSEC2"
432 #define TSEC1_PHY_ADDR 0
433 #define TSEC2_PHY_ADDR 1
435 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
436 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
438 #define TSEC1_PHYIDX 0
439 #define TSEC2_PHYIDX 0
441 #define CONFIG_ETHPRIME "eTSEC1"
443 /* TBI PHY configuration for SGMII mode */
444 #define CONFIG_TSEC_TBICR_SETTINGS ( \
446 | TBICR_ANEG_ENABLE \
447 | TBICR_FULL_DUPLEX \
451 #endif /* CONFIG_TSEC_ENET */
454 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
457 #ifdef CONFIG_USB_EHCI_HCD
458 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
459 #define CONFIG_USB_EHCI_FSL
460 #define CONFIG_HAS_FSL_DR_USB
466 #if defined(CONFIG_RAMBOOT_SDCARD)
467 #define CONFIG_FSL_FIXED_MMC_LOCATION
468 #define CONFIG_SYS_MMC_ENV_DEV 0
469 #define CONFIG_ENV_SIZE 0x2000
470 #elif defined(CONFIG_RAMBOOT_SPIFLASH)
471 #define CONFIG_ENV_SPI_BUS 0
472 #define CONFIG_ENV_SPI_CS 0
473 #define CONFIG_ENV_SPI_MAX_HZ 10000000
474 #define CONFIG_ENV_SPI_MODE 0
475 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
476 #define CONFIG_ENV_SECT_SIZE 0x10000
477 #define CONFIG_ENV_SIZE 0x2000
478 #elif defined(CONFIG_NAND) || defined(CONFIG_NAND_SECBOOT)
479 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
480 #define CONFIG_ENV_OFFSET ((768 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE)
481 #define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE)
482 #elif defined(CONFIG_SYS_RAMBOOT)
483 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
484 #define CONFIG_ENV_SIZE 0x2000
486 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
487 #define CONFIG_ENV_SIZE 0x2000
488 #define CONFIG_ENV_SECT_SIZE 0x20000
491 #define CONFIG_LOADS_ECHO /* echo on for serial download */
492 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
495 * Miscellaneous configurable options
497 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
500 * For booting Linux, the board info and command line data
501 * have to be in the first 64 MB of memory, since this is
502 * the maximum mapped by the Linux kernel during initialization.
504 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux */
505 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
507 #if defined(CONFIG_CMD_KGDB)
508 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
512 * Dynamic MTD Partition support with mtdparts
514 #ifdef CONFIG_MTD_NOR_FLASH
515 #define CONFIG_FLASH_CFI_MTD
518 * Environment Configuration
521 #if defined(CONFIG_TSEC_ENET)
522 #define CONFIG_HAS_ETH0
523 #define CONFIG_HAS_ETH1
526 #define CONFIG_HOSTNAME "BSC9132qds"
527 #define CONFIG_ROOTPATH "/opt/nfsroot"
528 #define CONFIG_BOOTFILE "uImage"
529 #define CONFIG_UBOOTPATH "u-boot.bin"
532 #define CONFIG_DEF_HWCONFIG "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0"
534 #define CONFIG_DEF_HWCONFIG "hwconfig=sim;usb1:dr_mode=host,phy_type=ulpi\0"
537 #define CONFIG_EXTRA_ENV_SETTINGS \
539 "uboot=" CONFIG_UBOOTPATH "\0" \
540 "loadaddr=1000000\0" \
541 "bootfile=uImage\0" \
542 "consoledev=ttyS0\0" \
543 "ramdiskaddr=2000000\0" \
544 "ramdiskfile=rootfs.ext2.gz.uboot\0" \
545 "fdtaddr=1e00000\0" \
546 "fdtfile=bsc9132qds.dtb\0" \
549 "othbootargs=mem=880M ramdisk_size=600000 " \
550 "default_hugepagesz=256m hugepagesz=256m hugepages=1 " \
552 "usbext2boot=setenv bootargs root=/dev/ram rw " \
553 "console=$consoledev,$baudrate $othbootargs; " \
555 "ext2load usb 0:4 $loadaddr $bootfile;" \
556 "ext2load usb 0:4 $fdtaddr $fdtfile;" \
557 "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \
558 "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \
559 "debug_halt_off=mw ff7e0e30 0xf0000000;"
561 #define CONFIG_NFSBOOTCOMMAND \
562 "setenv bootargs root=/dev/nfs rw " \
563 "nfsroot=$serverip:$rootpath " \
564 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
565 "console=$consoledev,$baudrate $othbootargs;" \
566 "tftp $loadaddr $bootfile;" \
567 "tftp $fdtaddr $fdtfile;" \
568 "bootm $loadaddr - $fdtaddr"
570 #define CONFIG_HDBOOT \
571 "setenv bootargs root=/dev/$bdev rw rootdelay=30 " \
572 "console=$consoledev,$baudrate $othbootargs;" \
574 "ext2load usb 0:1 $loadaddr /boot/$bootfile;" \
575 "ext2load usb 0:1 $fdtaddr /boot/$fdtfile;" \
576 "bootm $loadaddr - $fdtaddr"
578 #define CONFIG_RAMBOOTCOMMAND \
579 "setenv bootargs root=/dev/ram rw " \
580 "console=$consoledev,$baudrate $othbootargs; " \
581 "tftp $ramdiskaddr $ramdiskfile;" \
582 "tftp $loadaddr $bootfile;" \
583 "tftp $fdtaddr $fdtfile;" \
584 "bootm $loadaddr $ramdiskaddr $fdtaddr"
586 #define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND
588 #include <asm/fsl_secure_boot.h>
590 #endif /* __CONFIG_H */