Merge branch 'master' of git://git.denx.de/u-boot-spi
[platform/kernel/u-boot.git] / include / configs / BSC9132QDS.h
1 /*
2  * Copyright 2013 Freescale Semiconductor, Inc.
3  *
4  * SPDX-License-Identifier:     GPL-2.0+
5  */
6
7 /*
8  * BSC9132 QDS board configuration file
9  */
10
11 #ifndef __CONFIG_H
12 #define __CONFIG_H
13
14 #define CONFIG_MISC_INIT_R
15
16 #ifdef CONFIG_SDCARD
17 #define CONFIG_RAMBOOT_SDCARD
18 #define CONFIG_SYS_RAMBOOT
19 #define CONFIG_SYS_EXTRA_ENV_RELOC
20 #define CONFIG_SYS_TEXT_BASE            0x11000000
21 #define CONFIG_RESET_VECTOR_ADDRESS     0x110bfffc
22 #endif
23 #ifdef CONFIG_SPIFLASH
24 #define CONFIG_RAMBOOT_SPIFLASH
25 #define CONFIG_SYS_RAMBOOT
26 #define CONFIG_SYS_EXTRA_ENV_RELOC
27 #define CONFIG_SYS_TEXT_BASE            0x11000000
28 #define CONFIG_RESET_VECTOR_ADDRESS     0x110bfffc
29 #endif
30 #ifdef CONFIG_NAND_SECBOOT
31 #define CONFIG_RAMBOOT_NAND
32 #define CONFIG_SYS_RAMBOOT
33 #define CONFIG_SYS_EXTRA_ENV_RELOC
34 #define CONFIG_SYS_TEXT_BASE            0x11000000
35 #define CONFIG_RESET_VECTOR_ADDRESS     0x110bfffc
36 #endif
37
38 #ifdef CONFIG_NAND
39 #define CONFIG_SPL_INIT_MINIMAL
40 #define CONFIG_SPL_NAND_BOOT
41 #define CONFIG_SPL_FLUSH_IMAGE
42 #define CONFIG_SPL_TARGET               "u-boot-with-spl.bin"
43
44 #define CONFIG_SYS_TEXT_BASE            0x00201000
45 #define CONFIG_SPL_TEXT_BASE            0xFFFFE000
46 #define CONFIG_SPL_MAX_SIZE             8192
47 #define CONFIG_SPL_RELOC_TEXT_BASE      0x00100000
48 #define CONFIG_SPL_RELOC_STACK          0x00100000
49 #define CONFIG_SYS_NAND_U_BOOT_SIZE     ((768 << 10) - 0x2000)
50 #define CONFIG_SYS_NAND_U_BOOT_DST      (0x00200000 - CONFIG_SPL_MAX_SIZE)
51 #define CONFIG_SYS_NAND_U_BOOT_START    0x00200000
52 #define CONFIG_SYS_NAND_U_BOOT_OFFS     0
53 #define CONFIG_SYS_LDSCRIPT     "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
54 #endif
55
56 #ifndef CONFIG_SYS_TEXT_BASE
57 #define CONFIG_SYS_TEXT_BASE            0x8ff40000
58 #endif
59
60 #ifndef CONFIG_RESET_VECTOR_ADDRESS
61 #define CONFIG_RESET_VECTOR_ADDRESS     0x8ffffffc
62 #endif
63
64 #ifdef CONFIG_SPL_BUILD
65 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
66 #else
67 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
68 #endif
69
70 /* High Level Configuration Options */
71 #define CONFIG_FSL_IFC                  /* Enable IFC Support */
72 #define CONFIG_FSL_CAAM                 /* Enable SEC/CAAM */
73 #define CONFIG_SYS_HAS_SERDES           /* common SERDES init code */
74
75 #if defined(CONFIG_PCI)
76 #define CONFIG_PCIE1                    /* PCIE controller 1 (slot 1) */
77 #define CONFIG_FSL_PCI_INIT             /* Use common FSL init code */
78 #define CONFIG_PCI_INDIRECT_BRIDGE      /* indirect PCI bridge support */
79 #define CONFIG_FSL_PCIE_RESET           /* need PCIe reset errata */
80 #define CONFIG_SYS_PCI_64BIT            /* enable 64-bit PCI resources */
81
82 #define CONFIG_CMD_PCI
83
84 /*
85  * PCI Windows
86  * Memory space is mapped 1-1, but I/O space must start from 0.
87  */
88 /* controller 1, Slot 1, tgtid 1, Base address a000 */
89 #define CONFIG_SYS_PCIE1_NAME           "PCIe Slot"
90 #define CONFIG_SYS_PCIE1_MEM_VIRT       0x90000000
91 #define CONFIG_SYS_PCIE1_MEM_BUS        0x90000000
92 #define CONFIG_SYS_PCIE1_MEM_PHYS       0x90000000
93 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x10000000      /* 256M */
94 #define CONFIG_SYS_PCIE1_IO_VIRT        0xC0010000
95 #define CONFIG_SYS_PCIE1_IO_BUS         0x00000000
96 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00010000      /* 64k */
97 #define CONFIG_SYS_PCIE1_IO_PHYS        0xC0010000
98
99 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
100 #define CONFIG_DOS_PARTITION
101 #endif
102
103 #define CONFIG_ENV_OVERWRITE
104 #define CONFIG_TSEC_ENET /* ethernet */
105
106 #if defined(CONFIG_SYS_CLK_100_DDR_100)
107 #define CONFIG_SYS_CLK_FREQ     100000000
108 #define CONFIG_DDR_CLK_FREQ     100000000
109 #elif defined(CONFIG_SYS_CLK_100_DDR_133)
110 #define CONFIG_SYS_CLK_FREQ     100000000
111 #define CONFIG_DDR_CLK_FREQ     133000000
112 #endif
113
114 #define CONFIG_MP
115
116 #define CONFIG_HWCONFIG
117 /*
118  * These can be toggled for performance analysis, otherwise use default.
119  */
120 #define CONFIG_L2_CACHE                 /* toggle L2 cache */
121 #define CONFIG_BTB                      /* enable branch predition */
122
123 #define CONFIG_SYS_MEMTEST_START        0x01000000      /* memtest works on */
124 #define CONFIG_SYS_MEMTEST_END          0x01ffffff
125
126 /* DDR Setup */
127 #define CONFIG_SYS_SPD_BUS_NUM          0
128 #define SPD_EEPROM_ADDRESS1             0x54 /* I2C access */
129 #define SPD_EEPROM_ADDRESS2             0x56 /* I2C access */
130 #define CONFIG_FSL_DDR_INTERACTIVE
131
132 #define CONFIG_MEM_INIT_VALUE           0xDeadBeef
133
134 #define CONFIG_SYS_SDRAM_SIZE           (1024)
135 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
136 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
137
138 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
139
140 /* DDR3 Controller Settings */
141 #define CONFIG_CHIP_SELECTS_PER_CTRL    1
142 #define CONFIG_SYS_DDR_CS0_BNDS         0x0000003F
143 #define CONFIG_SYS_DDR_CS0_CONFIG_1333  0x80004302
144 #define CONFIG_SYS_DDR_CS0_CONFIG_800   0x80014302
145 #define CONFIG_SYS_DDR_CS0_CONFIG_2     0x00000000
146 #define CONFIG_SYS_DDR_DATA_INIT        0xdeadbeef
147 #define CONFIG_SYS_DDR_INIT_ADDR        0x00000000
148 #define CONFIG_SYS_DDR_INIT_EXT_ADDR    0x00000000
149 #define CONFIG_SYS_DDR_MODE_CONTROL     0x00000000
150 #define CONFIG_SYS_DDR1_CS0_BNDS       0x0040007F
151
152 #define CONFIG_SYS_DDR_ZQ_CONTROL       0x89080600
153 #define CONFIG_SYS_DDR_SR_CNTR          0x00000000
154 #define CONFIG_SYS_DDR_RCW_1            0x00000000
155 #define CONFIG_SYS_DDR_RCW_2            0x00000000
156 #define CONFIG_SYS_DDR_CONTROL_800              0x470C0000
157 #define CONFIG_SYS_DDR_CONTROL_2_800    0x04401050
158 #define CONFIG_SYS_DDR_TIMING_4_800             0x00220001
159 #define CONFIG_SYS_DDR_TIMING_5_800             0x03402400
160
161 #define CONFIG_SYS_DDR_CONTROL_1333             0x470C0008
162 #define CONFIG_SYS_DDR_CONTROL_2_1333   0x24401010
163 #define CONFIG_SYS_DDR_TIMING_4_1333            0x00000001
164 #define CONFIG_SYS_DDR_TIMING_5_1333            0x03401400
165
166 #define CONFIG_SYS_DDR_TIMING_3_800             0x00020000
167 #define CONFIG_SYS_DDR_TIMING_0_800             0x00330004
168 #define CONFIG_SYS_DDR_TIMING_1_800             0x6f6B4846
169 #define CONFIG_SYS_DDR_TIMING_2_800             0x0FA8C8CF
170 #define CONFIG_SYS_DDR_CLK_CTRL_800             0x03000000
171 #define CONFIG_SYS_DDR_MODE_1_800               0x40461520
172 #define CONFIG_SYS_DDR_MODE_2_800               0x8000c000
173 #define CONFIG_SYS_DDR_INTERVAL_800             0x0C300000
174 #define CONFIG_SYS_DDR_WRLVL_CONTROL_800        0x8655A608
175
176 #define CONFIG_SYS_DDR_TIMING_3_1333            0x01061000
177 #define CONFIG_SYS_DDR_TIMING_0_1333            0x00440104
178 #define CONFIG_SYS_DDR_TIMING_1_1333            0x98913A45
179 #define CONFIG_SYS_DDR_TIMING_2_1333            0x0FB8B114
180 #define CONFIG_SYS_DDR_CLK_CTRL_1333            0x02800000
181 #define CONFIG_SYS_DDR_MODE_1_1333              0x00061A50
182 #define CONFIG_SYS_DDR_MODE_2_1333              0x00100000
183 #define CONFIG_SYS_DDR_INTERVAL_1333            0x144E0513
184 #define CONFIG_SYS_DDR_WRLVL_CONTROL_1333       0x8655F607
185
186 /*FIXME: the following params are constant w.r.t diff freq
187 combinations. this should be removed later
188 */
189 #if CONFIG_DDR_CLK_FREQ == 100000000
190 #define CONFIG_SYS_DDR_CS0_CONFIG CONFIG_SYS_DDR_CS0_CONFIG_800
191 #define CONFIG_SYS_DDR_CONTROL          CONFIG_SYS_DDR_CONTROL_800
192 #define CONFIG_SYS_DDR_CONTROL_2 CONFIG_SYS_DDR_CONTROL_2_800
193 #define CONFIG_SYS_DDR_TIMING_4 CONFIG_SYS_DDR_TIMING_4_800
194 #define CONFIG_SYS_DDR_TIMING_5 CONFIG_SYS_DDR_TIMING_5_800
195 #elif CONFIG_DDR_CLK_FREQ == 133000000
196 #define CONFIG_SYS_DDR_CS0_CONFIG CONFIG_SYS_DDR_CS0_CONFIG_1333
197 #define CONFIG_SYS_DDR_CONTROL          CONFIG_SYS_DDR_CONTROL_1333
198 #define CONFIG_SYS_DDR_CONTROL_2        CONFIG_SYS_DDR_CONTROL_2_1333
199 #define CONFIG_SYS_DDR_TIMING_4 CONFIG_SYS_DDR_TIMING_4_1333
200 #define CONFIG_SYS_DDR_TIMING_5 CONFIG_SYS_DDR_TIMING_5_1333
201 #else
202 #define CONFIG_SYS_DDR_CS0_CONFIG CONFIG_SYS_DDR_CS0_CONFIG_800
203 #define CONFIG_SYS_DDR_CONTROL          CONFIG_SYS_DDR_CONTROL_800
204 #define CONFIG_SYS_DDR_CONTROL_2        CONFIG_SYS_DDR_CONTROL_2_800
205 #define CONFIG_SYS_DDR_TIMING_4 CONFIG_SYS_DDR_TIMING_4_800
206 #define CONFIG_SYS_DDR_TIMING_5 CONFIG_SYS_DDR_TIMING_5_800
207 #endif
208
209 /* relocated CCSRBAR */
210 #define CONFIG_SYS_CCSRBAR      CONFIG_SYS_CCSRBAR_DEFAULT
211 #define CONFIG_SYS_CCSRBAR_PHYS_LOW     CONFIG_SYS_CCSRBAR_DEFAULT
212
213 #define CONFIG_SYS_IMMR         CONFIG_SYS_CCSRBAR
214
215 /* DSP CCSRBAR */
216 #define CONFIG_SYS_FSL_DSP_CCSRBAR      CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT
217 #define CONFIG_SYS_FSL_DSP_CCSRBAR_PHYS CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT
218
219 /*
220  * IFC Definitions
221  */
222 /* NOR Flash on IFC */
223
224 #ifdef CONFIG_SPL_BUILD
225 #define CONFIG_SYS_NO_FLASH
226 #endif
227 #define CONFIG_SYS_FLASH_BASE           0x88000000
228 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /* Max number of sector: 32M */
229
230 #define CONFIG_SYS_FLASH_BASE_PHYS      CONFIG_SYS_FLASH_BASE
231
232 #define CONFIG_SYS_NOR_CSPR     0x88000101
233 #define CONFIG_SYS_NOR_AMASK    IFC_AMASK(128*1024*1024)
234 #define CONFIG_SYS_NOR_CSOR     CSOR_NOR_ADM_SHIFT(5)
235 /* NOR Flash Timing Params */
236
237 #define CONFIG_SYS_NOR_FTIM0    (FTIM0_NOR_TACSE(0x01) \
238                                 | FTIM0_NOR_TEADC(0x03) \
239                                 | FTIM0_NOR_TAVDS(0x00) \
240                                 | FTIM0_NOR_TEAHC(0x0f))
241 #define CONFIG_SYS_NOR_FTIM1    (FTIM1_NOR_TACO(0x1d) \
242                                 | FTIM1_NOR_TRAD_NOR(0x09) \
243                                 | FTIM1_NOR_TSEQRAD_NOR(0x09))
244 #define CONFIG_SYS_NOR_FTIM2    (FTIM2_NOR_TCS(0x1) \
245                                 | FTIM2_NOR_TCH(0x4) \
246                                 | FTIM2_NOR_TWPH(0x7) \
247                                 | FTIM2_NOR_TWP(0x1e))
248 #define CONFIG_SYS_NOR_FTIM3    0x0
249
250 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS}
251 #define CONFIG_SYS_FLASH_QUIET_TEST
252 #define CONFIG_FLASH_SHOW_PROGRESS      45      /* count down from 45/5: 9..1 */
253 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* number of banks */
254
255 #undef CONFIG_SYS_FLASH_CHECKSUM
256 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
257 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
258
259 /* CFI for NOR Flash */
260 #define CONFIG_FLASH_CFI_DRIVER
261 #define CONFIG_SYS_FLASH_CFI
262 #define CONFIG_SYS_FLASH_EMPTY_INFO
263 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
264
265 /* NAND Flash on IFC */
266 #define CONFIG_SYS_NAND_BASE            0xff800000
267 #define CONFIG_SYS_NAND_BASE_PHYS       CONFIG_SYS_NAND_BASE
268
269 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
270                                 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
271                                 | CSPR_MSEL_NAND        /* MSEL = NAND */ \
272                                 | CSPR_V)
273 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64*1024)
274
275 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
276                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
277                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
278                                 | CSOR_NAND_RAL_2       /* RAL = 2Byes */ \
279                                 | CSOR_NAND_PGS_2K      /* Page Size = 2K */ \
280                                 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
281                                 | CSOR_NAND_PB(64))     /*Pages Per Block = 64*/
282
283 /* NAND Flash Timing Params */
284 #define CONFIG_SYS_NAND_FTIM0           (FTIM0_NAND_TCCST(0x03) \
285                                         | FTIM0_NAND_TWP(0x05) \
286                                         | FTIM0_NAND_TWCHT(0x02) \
287                                         | FTIM0_NAND_TWH(0x04))
288 #define CONFIG_SYS_NAND_FTIM1           (FTIM1_NAND_TADLE(0x1c) \
289                                         | FTIM1_NAND_TWBE(0x1e) \
290                                         | FTIM1_NAND_TRR(0x07) \
291                                         | FTIM1_NAND_TRP(0x05))
292 #define CONFIG_SYS_NAND_FTIM2           (FTIM2_NAND_TRAD(0x08) \
293                                         | FTIM2_NAND_TREH(0x04) \
294                                         | FTIM2_NAND_TWHRE(0x11))
295 #define CONFIG_SYS_NAND_FTIM3           FTIM3_NAND_TWW(0x04)
296
297 #define CONFIG_SYS_NAND_DDR_LAW         11
298
299 /* NAND */
300 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
301 #define CONFIG_SYS_MAX_NAND_DEVICE      1
302 #define CONFIG_CMD_NAND
303
304 #define CONFIG_SYS_NAND_BLOCK_SIZE      (128 * 1024)
305
306 #ifndef CONFIG_SPL_BUILD
307 #define CONFIG_FSL_QIXIS
308 #endif
309 #ifdef CONFIG_FSL_QIXIS
310 #define CONFIG_SYS_FPGA_BASE    0xffb00000
311 #define CONFIG_SYS_I2C_FPGA_ADDR        0x66
312 #define QIXIS_BASE      CONFIG_SYS_FPGA_BASE
313 #define QIXIS_LBMAP_SWITCH      9
314 #define QIXIS_LBMAP_MASK        0x07
315 #define QIXIS_LBMAP_SHIFT       0
316 #define QIXIS_LBMAP_DFLTBANK            0x00
317 #define QIXIS_LBMAP_ALTBANK             0x04
318 #define QIXIS_RST_CTL_RESET             0x83
319 #define QIXIS_RCFG_CTL_RECONFIG_IDLE    0x20
320 #define QIXIS_RCFG_CTL_RECONFIG_START   0x21
321 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE   0x08
322
323 #define CONFIG_SYS_FPGA_BASE_PHYS       CONFIG_SYS_FPGA_BASE
324
325 #define CONFIG_SYS_CSPR2                (CSPR_PHYS_ADDR(CONFIG_SYS_FPGA_BASE) \
326                                         | CSPR_PORT_SIZE_8 \
327                                         | CSPR_MSEL_GPCM \
328                                         | CSPR_V)
329 #define CONFIG_SYS_AMASK2               IFC_AMASK(64*1024)
330 #define CONFIG_SYS_CSOR2                0x0
331 /* CPLD Timing parameters for IFC CS3 */
332 #define CONFIG_SYS_CS2_FTIM0            (FTIM0_GPCM_TACSE(0x0e) | \
333                                         FTIM0_GPCM_TEADC(0x0e) | \
334                                         FTIM0_GPCM_TEAHC(0x0e))
335 #define CONFIG_SYS_CS2_FTIM1            (FTIM1_GPCM_TACO(0x0e) | \
336                                         FTIM1_GPCM_TRAD(0x1f))
337 #define CONFIG_SYS_CS2_FTIM2            (FTIM2_GPCM_TCS(0x0e) | \
338                                         FTIM2_GPCM_TCH(0x8) | \
339                                         FTIM2_GPCM_TWP(0x1f))
340 #define CONFIG_SYS_CS2_FTIM3            0x0
341 #endif
342
343 /* Set up IFC registers for boot location NOR/NAND */
344 #if defined(CONFIG_NAND) || defined(CONFIG_NAND_SECBOOT)
345 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
346 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
347 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
348 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
349 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
350 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
351 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
352 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR_CSPR
353 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
354 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
355 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
356 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
357 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
358 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
359 #else
360 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR_CSPR
361 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
362 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
363 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
364 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
365 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
366 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
367 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NAND_CSPR
368 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NAND_AMASK
369 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NAND_CSOR
370 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NAND_FTIM0
371 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NAND_FTIM1
372 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NAND_FTIM2
373 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NAND_FTIM3
374 #endif
375
376 #define CONFIG_BOARD_EARLY_INIT_F       /* Call board_pre_init */
377 #define CONFIG_BOARD_EARLY_INIT_R
378
379 #define CONFIG_SYS_INIT_RAM_LOCK
380 #define CONFIG_SYS_INIT_RAM_ADDR        0xffd00000      /* stack in RAM */
381 #define CONFIG_SYS_INIT_RAM_SIZE        0x00004000 /* End of used area in RAM */
382
383 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE \
384                                                 - GENERATED_GBL_DATA_SIZE)
385 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
386
387 #define CONFIG_SYS_MONITOR_LEN          (768 * 1024)
388 #define CONFIG_SYS_MALLOC_LEN           (1024 * 1024)   /* Reserved for malloc*/
389
390 /* Serial Port */
391 #define CONFIG_CONS_INDEX       1
392 #undef  CONFIG_SERIAL_SOFTWARE_FIFO
393 #define CONFIG_SYS_NS16550_SERIAL
394 #define CONFIG_SYS_NS16550_REG_SIZE     1
395 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
396 #ifdef CONFIG_SPL_BUILD
397 #define CONFIG_NS16550_MIN_FUNCTIONS
398 #endif
399
400 #define CONFIG_SYS_BAUDRATE_TABLE       \
401         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
402
403 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR + 0x4500)
404 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR + 0x4600)
405 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR + 0x4700)
406 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR + 0x4800)
407
408 #define CONFIG_SYS_I2C
409 #define CONFIG_SYS_I2C_FSL
410 #define CONFIG_SYS_FSL_I2C_SPEED        400800 /* I2C speed and slave address*/
411 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
412 #define CONFIG_SYS_FSL_I2C2_SPEED       400800 /* I2C speed and slave address*/
413 #define CONFIG_SYS_FSL_I2C2_SLAVE       0x7F
414 #define CONFIG_SYS_FSL_I2C_OFFSET       0x3000
415 #define CONFIG_SYS_FSL_I2C2_OFFSET      0x3100
416
417 /* I2C EEPROM */
418 #define CONFIG_ID_EEPROM
419 #ifdef CONFIG_ID_EEPROM
420 #define CONFIG_SYS_I2C_EEPROM_NXID
421 #endif
422 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x57
423 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
424 #define CONFIG_SYS_EEPROM_BUS_NUM       0
425
426 /* enable read and write access to EEPROM */
427 #define CONFIG_CMD_EEPROM
428 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
429 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
430 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
431
432 /* I2C FPGA */
433 #define CONFIG_I2C_FPGA
434 #define CONFIG_SYS_I2C_FPGA_ADDR        0x66
435
436 #define CONFIG_RTC_DS3231
437 #define CONFIG_SYS_I2C_RTC_ADDR         0x68
438
439 /*
440  * SPI interface will not be available in case of NAND boot SPI CS0 will be
441  * used for SLIC
442  */
443 /* eSPI - Enhanced SPI */
444 #ifdef CONFIG_FSL_ESPI
445 #define CONFIG_SF_DEFAULT_SPEED         10000000
446 #define CONFIG_SF_DEFAULT_MODE          SPI_MODE_0
447 #endif
448
449 #if defined(CONFIG_TSEC_ENET)
450
451 #define CONFIG_MII                      /* MII PHY management */
452 #define CONFIG_MII_DEFAULT_TSEC 1       /* Allow unregistered phys */
453 #define CONFIG_TSEC1    1
454 #define CONFIG_TSEC1_NAME       "eTSEC1"
455 #define CONFIG_TSEC2    1
456 #define CONFIG_TSEC2_NAME       "eTSEC2"
457
458 #define TSEC1_PHY_ADDR          0
459 #define TSEC2_PHY_ADDR          1
460
461 #define TSEC1_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
462 #define TSEC2_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
463
464 #define TSEC1_PHYIDX            0
465 #define TSEC2_PHYIDX            0
466
467 #define CONFIG_ETHPRIME         "eTSEC1"
468
469 #define CONFIG_PHY_GIGE         /* Include GbE speed/duplex detection */
470
471 /* TBI PHY configuration for SGMII mode */
472 #define CONFIG_TSEC_TBICR_SETTINGS ( \
473                 TBICR_PHY_RESET \
474                 | TBICR_ANEG_ENABLE \
475                 | TBICR_FULL_DUPLEX \
476                 | TBICR_SPEED1_SET \
477                 )
478
479 #endif  /* CONFIG_TSEC_ENET */
480
481 #ifdef CONFIG_MMC
482 #define CONFIG_DOS_PARTITION
483 #define CONFIG_FSL_ESDHC
484 #define CONFIG_GENERIC_MMC
485 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
486 #endif
487
488 #define CONFIG_USB_EHCI  /* USB */
489 #ifdef CONFIG_USB_EHCI
490 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
491 #define CONFIG_USB_EHCI_FSL
492 #define CONFIG_HAS_FSL_DR_USB
493 #endif
494
495 /*
496  * Environment
497  */
498 #if defined(CONFIG_RAMBOOT_SDCARD)
499 #define CONFIG_ENV_IS_IN_MMC
500 #define CONFIG_FSL_FIXED_MMC_LOCATION
501 #define CONFIG_SYS_MMC_ENV_DEV          0
502 #define CONFIG_ENV_SIZE                 0x2000
503 #elif defined(CONFIG_RAMBOOT_SPIFLASH)
504 #define CONFIG_ENV_IS_IN_SPI_FLASH
505 #define CONFIG_ENV_SPI_BUS      0
506 #define CONFIG_ENV_SPI_CS       0
507 #define CONFIG_ENV_SPI_MAX_HZ   10000000
508 #define CONFIG_ENV_SPI_MODE     0
509 #define CONFIG_ENV_OFFSET       0x100000        /* 1MB */
510 #define CONFIG_ENV_SECT_SIZE    0x10000
511 #define CONFIG_ENV_SIZE         0x2000
512 #elif defined(CONFIG_NAND) || defined(CONFIG_NAND_SECBOOT)
513 #define CONFIG_ENV_IS_IN_NAND
514 #define CONFIG_ENV_SIZE         CONFIG_SYS_NAND_BLOCK_SIZE
515 #define CONFIG_ENV_OFFSET       ((768 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE)
516 #define CONFIG_ENV_RANGE        (3 * CONFIG_ENV_SIZE)
517 #elif defined(CONFIG_SYS_RAMBOOT)
518 #define CONFIG_ENV_IS_NOWHERE           /* Store ENV in memory only */
519 #define CONFIG_ENV_ADDR                 (CONFIG_SYS_MONITOR_BASE - 0x1000)
520 #define CONFIG_ENV_SIZE                 0x2000
521 #else
522 #define CONFIG_ENV_IS_IN_FLASH
523 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
524 #define CONFIG_ENV_SIZE         0x2000
525 #define CONFIG_ENV_SECT_SIZE    0x20000
526 #endif
527
528 #define CONFIG_LOADS_ECHO               /* echo on for serial download */
529 #define CONFIG_SYS_LOADS_BAUD_CHANGE    /* allow baudrate change */
530
531 /*
532  * Command line configuration.
533  */
534 #define CONFIG_CMD_DATE
535 #define CONFIG_CMD_ERRATA
536 #define CONFIG_CMD_IRQ
537 #define CONFIG_CMD_REGINFO
538
539 #if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI)
540 #define CONFIG_DOS_PARTITION
541 #endif
542
543 /* Hash command with SHA acceleration supported in hardware */
544 #ifdef CONFIG_FSL_CAAM
545 #define CONFIG_CMD_HASH
546 #define CONFIG_SHA_HW_ACCEL
547 #endif
548
549 /*
550  * Miscellaneous configurable options
551  */
552 #define CONFIG_SYS_LONGHELP                     /* undef to save memory */
553 #define CONFIG_CMDLINE_EDITING                  /* Command-line editing */
554 #define CONFIG_AUTO_COMPLETE                    /* add autocompletion support */
555 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
556
557 #if defined(CONFIG_CMD_KGDB)
558 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size */
559 #else
560 #define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size */
561 #endif
562 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
563                                                 /* Print Buffer Size */
564 #define CONFIG_SYS_MAXARGS      16              /* max number of command args */
565 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
566
567 /*
568  * For booting Linux, the board info and command line data
569  * have to be in the first 64 MB of memory, since this is
570  * the maximum mapped by the Linux kernel during initialization.
571  */
572 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20) /* Initial Memory map for Linux */
573 #define CONFIG_SYS_BOOTM_LEN    (64 << 20) /* Increase max gunzip size */
574
575 #if defined(CONFIG_CMD_KGDB)
576 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
577 #endif
578
579 /*
580  * Dynamic MTD Partition support with mtdparts
581  */
582 #ifndef CONFIG_SYS_NO_FLASH
583 #define CONFIG_MTD_DEVICE
584 #define CONFIG_MTD_PARTITIONS
585 #define CONFIG_CMD_MTDPARTS
586 #define CONFIG_FLASH_CFI_MTD
587 #define MTDIDS_DEFAULT "nor0=88000000.nor,nand0=ff800000.flash,"
588 #define MTDPARTS_DEFAULT "mtdparts=88000000.nor:256k(dtb),7m(kernel)," \
589                         "55m(fs),1m(uboot);ff800000.flash:1m(uboot)," \
590                         "8m(kernel),512k(dtb),-(fs)"
591 #endif
592 /*
593  * Environment Configuration
594  */
595
596 #if defined(CONFIG_TSEC_ENET)
597 #define CONFIG_HAS_ETH0
598 #define CONFIG_HAS_ETH1
599 #endif
600
601 #define CONFIG_HOSTNAME         BSC9132qds
602 #define CONFIG_ROOTPATH         "/opt/nfsroot"
603 #define CONFIG_BOOTFILE         "uImage"
604 #define CONFIG_UBOOTPATH        "u-boot.bin"
605
606 #define CONFIG_BAUDRATE         115200
607
608 #ifdef CONFIG_SDCARD
609 #define CONFIG_DEF_HWCONFIG     "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0"
610 #else
611 #define CONFIG_DEF_HWCONFIG     "hwconfig=sim;usb1:dr_mode=host,phy_type=ulpi\0"
612 #endif
613
614 #define CONFIG_EXTRA_ENV_SETTINGS                               \
615         "netdev=eth0\0"                                         \
616         "uboot=" CONFIG_UBOOTPATH "\0"                          \
617         "loadaddr=1000000\0"                    \
618         "bootfile=uImage\0"     \
619         "consoledev=ttyS0\0"                            \
620         "ramdiskaddr=2000000\0"                 \
621         "ramdiskfile=rootfs.ext2.gz.uboot\0"            \
622         "fdtaddr=1e00000\0"                             \
623         "fdtfile=bsc9132qds.dtb\0"              \
624         "bdev=sda1\0"   \
625         CONFIG_DEF_HWCONFIG\
626         "othbootargs=mem=880M ramdisk_size=600000 " \
627                 "default_hugepagesz=256m hugepagesz=256m hugepages=1 " \
628                 "isolcpus=0\0" \
629         "usbext2boot=setenv bootargs root=/dev/ram rw " \
630                 "console=$consoledev,$baudrate $othbootargs; "  \
631                 "usb start;"                    \
632                 "ext2load usb 0:4 $loadaddr $bootfile;"         \
633                 "ext2load usb 0:4 $fdtaddr $fdtfile;"   \
634                 "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;"   \
635                 "bootm $loadaddr $ramdiskaddr $fdtaddr\0"       \
636         "debug_halt_off=mw ff7e0e30 0xf0000000;"
637
638 #define CONFIG_NFSBOOTCOMMAND   \
639         "setenv bootargs root=/dev/nfs rw "     \
640         "nfsroot=$serverip:$rootpath "  \
641         "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
642         "console=$consoledev,$baudrate $othbootargs;" \
643         "tftp $loadaddr $bootfile;"     \
644         "tftp $fdtaddr $fdtfile;"       \
645         "bootm $loadaddr - $fdtaddr"
646
647 #define CONFIG_HDBOOT   \
648         "setenv bootargs root=/dev/$bdev rw rootdelay=30 "      \
649         "console=$consoledev,$baudrate $othbootargs;" \
650         "usb start;"    \
651         "ext2load usb 0:1 $loadaddr /boot/$bootfile;"   \
652         "ext2load usb 0:1 $fdtaddr /boot/$fdtfile;"     \
653         "bootm $loadaddr - $fdtaddr"
654
655 #define CONFIG_RAMBOOTCOMMAND           \
656         "setenv bootargs root=/dev/ram rw "     \
657         "console=$consoledev,$baudrate $othbootargs; "  \
658         "tftp $ramdiskaddr $ramdiskfile;"       \
659         "tftp $loadaddr $bootfile;"             \
660         "tftp $fdtaddr $fdtfile;"               \
661         "bootm $loadaddr $ramdiskaddr $fdtaddr"
662
663 #define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND
664
665 #include <asm/fsl_secure_boot.h>
666
667 #endif  /* __CONFIG_H */