2 * Copyright 2013 Freescale Semiconductor, Inc.
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 * BSC9132 QDS board configuration file
30 #ifdef CONFIG_BSC9132QDS
31 #define CONFIG_BSC9132
34 #define CONFIG_MISC_INIT_R
37 #define CONFIG_RAMBOOT_SDCARD
38 #define CONFIG_SYS_RAMBOOT
39 #define CONFIG_SYS_EXTRA_ENV_RELOC
40 #define CONFIG_SYS_TEXT_BASE 0x11000000
41 #define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc
43 #define CONFIG_SYS_FSL_ERRATUM_IFC_A002769 1
44 #ifdef CONFIG_SPIFLASH
45 #define CONFIG_RAMBOOT_SPIFLASH
46 #define CONFIG_SYS_RAMBOOT
47 #define CONFIG_SYS_EXTRA_ENV_RELOC
48 #define CONFIG_SYS_TEXT_BASE 0x11000000
49 #define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc
52 #ifndef CONFIG_SYS_TEXT_BASE
53 #define CONFIG_SYS_TEXT_BASE 0x8ff80000
56 #ifndef CONFIG_RESET_VECTOR_ADDRESS
57 #define CONFIG_RESET_VECTOR_ADDRESS 0x8ffffffc
60 #ifndef CONFIG_SYS_MONITOR_BASE
61 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
65 /* High Level Configuration Options */
66 #define CONFIG_BOOKE /* BOOKE */
67 #define CONFIG_E500 /* BOOKE e500 family */
68 #define CONFIG_MPC85xx
69 #define CONFIG_FSL_IFC /* Enable IFC Support */
70 #define CONFIG_SYS_HAS_SERDES /* common SERDES init code */
72 #define CONFIG_PCI /* Enable PCI/PCIE */
73 #if defined(CONFIG_PCI)
74 #define CONFIG_PCIE1 /* PCIE controler 1 (slot 1) */
75 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
76 #define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
77 #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */
78 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
80 #define CONFIG_CMD_NET
81 #define CONFIG_CMD_PCI
83 #define CONFIG_E1000 /* E1000 pci Ethernet card*/
87 * Memory space is mapped 1-1, but I/O space must start from 0.
89 /* controller 1, Slot 1, tgtid 1, Base address a000 */
90 #define CONFIG_SYS_PCIE1_NAME "PCIe Slot"
91 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x90000000
92 #define CONFIG_SYS_PCIE1_MEM_BUS 0x90000000
93 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x90000000
94 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */
95 #define CONFIG_SYS_PCIE1_IO_VIRT 0xC0010000
96 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
97 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
98 #define CONFIG_SYS_PCIE1_IO_PHYS 0xC0010000
100 #define CONFIG_PCI_PNP /* do pci plug-and-play */
102 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
103 #define CONFIG_DOS_PARTITION
106 #define CONFIG_FSL_LAW /* Use common FSL init code */
107 #define CONFIG_ENV_OVERWRITE
108 #define CONFIG_TSEC_ENET /* ethernet */
110 #if defined(CONFIG_SYS_CLK_100_DDR_100)
111 #define CONFIG_SYS_CLK_FREQ 100000000
112 #define CONFIG_DDR_CLK_FREQ 100000000
113 #elif defined(CONFIG_SYS_CLK_100_DDR_133)
114 #define CONFIG_SYS_CLK_FREQ 100000000
115 #define CONFIG_DDR_CLK_FREQ 133000000
120 #define CONFIG_HWCONFIG
122 * These can be toggled for performance analysis, otherwise use default.
124 #define CONFIG_L2_CACHE /* toggle L2 cache */
125 #define CONFIG_BTB /* enable branch predition */
127 #define CONFIG_SYS_MEMTEST_START 0x01000000 /* memtest works on */
128 #define CONFIG_SYS_MEMTEST_END 0x01ffffff
131 #define CONFIG_FSL_DDR3
132 #define CONFIG_SYS_SPD_BUS_NUM 0
133 #define SPD_EEPROM_ADDRESS1 0x54 /* I2C access */
134 #define SPD_EEPROM_ADDRESS2 0x56 /* I2C access */
135 #define CONFIG_FSL_DDR_INTERACTIVE
137 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef
139 #define CONFIG_SYS_SDRAM_SIZE (1024)
140 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
141 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
143 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
145 /* DDR3 Controller Settings */
146 #define CONFIG_CHIP_SELECTS_PER_CTRL 1
147 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003F
148 #define CONFIG_SYS_DDR_CS0_CONFIG_1333 0x80004302
149 #define CONFIG_SYS_DDR_CS0_CONFIG_800 0x80014302
150 #define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000
151 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
152 #define CONFIG_SYS_DDR_INIT_ADDR 0x00000000
153 #define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000
154 #define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000
155 #define CONFIG_SYS_DDR1_CS0_BNDS 0x0040007F
157 #define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600
158 #define CONFIG_SYS_DDR_SR_CNTR 0x00000000
159 #define CONFIG_SYS_DDR_RCW_1 0x00000000
160 #define CONFIG_SYS_DDR_RCW_2 0x00000000
161 #define CONFIG_SYS_DDR_CONTROL_800 0x470C0000
162 #define CONFIG_SYS_DDR_CONTROL_2_800 0x04401050
163 #define CONFIG_SYS_DDR_TIMING_4_800 0x00220001
164 #define CONFIG_SYS_DDR_TIMING_5_800 0x03402400
166 #define CONFIG_SYS_DDR_CONTROL_1333 0x470C0008
167 #define CONFIG_SYS_DDR_CONTROL_2_1333 0x24401010
168 #define CONFIG_SYS_DDR_TIMING_4_1333 0x00000001
169 #define CONFIG_SYS_DDR_TIMING_5_1333 0x03401400
171 #define CONFIG_SYS_DDR_TIMING_3_800 0x00020000
172 #define CONFIG_SYS_DDR_TIMING_0_800 0x00330004
173 #define CONFIG_SYS_DDR_TIMING_1_800 0x6f6B4846
174 #define CONFIG_SYS_DDR_TIMING_2_800 0x0FA8C8CF
175 #define CONFIG_SYS_DDR_CLK_CTRL_800 0x03000000
176 #define CONFIG_SYS_DDR_MODE_1_800 0x40461520
177 #define CONFIG_SYS_DDR_MODE_2_800 0x8000c000
178 #define CONFIG_SYS_DDR_INTERVAL_800 0x0C300000
179 #define CONFIG_SYS_DDR_WRLVL_CONTROL_800 0x8655A608
181 #define CONFIG_SYS_DDR_TIMING_3_1333 0x01061000
182 #define CONFIG_SYS_DDR_TIMING_0_1333 0x00440104
183 #define CONFIG_SYS_DDR_TIMING_1_1333 0x98913A45
184 #define CONFIG_SYS_DDR_TIMING_2_1333 0x0FB8B114
185 #define CONFIG_SYS_DDR_CLK_CTRL_1333 0x02800000
186 #define CONFIG_SYS_DDR_MODE_1_1333 0x00061A50
187 #define CONFIG_SYS_DDR_MODE_2_1333 0x00100000
188 #define CONFIG_SYS_DDR_INTERVAL_1333 0x144E0513
189 #define CONFIG_SYS_DDR_WRLVL_CONTROL_1333 0x8655F607
191 /*FIXME: the following params are constant w.r.t diff freq
192 combinations. this should be removed later
194 #if CONFIG_DDR_CLK_FREQ == 100000000
195 #define CONFIG_SYS_DDR_CS0_CONFIG CONFIG_SYS_DDR_CS0_CONFIG_800
196 #define CONFIG_SYS_DDR_CONTROL CONFIG_SYS_DDR_CONTROL_800
197 #define CONFIG_SYS_DDR_CONTROL_2 CONFIG_SYS_DDR_CONTROL_2_800
198 #define CONFIG_SYS_DDR_TIMING_4 CONFIG_SYS_DDR_TIMING_4_800
199 #define CONFIG_SYS_DDR_TIMING_5 CONFIG_SYS_DDR_TIMING_5_800
200 #elif CONFIG_DDR_CLK_FREQ == 133000000
201 #define CONFIG_SYS_DDR_CS0_CONFIG CONFIG_SYS_DDR_CS0_CONFIG_1333
202 #define CONFIG_SYS_DDR_CONTROL CONFIG_SYS_DDR_CONTROL_1333
203 #define CONFIG_SYS_DDR_CONTROL_2 CONFIG_SYS_DDR_CONTROL_2_1333
204 #define CONFIG_SYS_DDR_TIMING_4 CONFIG_SYS_DDR_TIMING_4_1333
205 #define CONFIG_SYS_DDR_TIMING_5 CONFIG_SYS_DDR_TIMING_5_1333
207 #define CONFIG_SYS_DDR_CS0_CONFIG CONFIG_SYS_DDR_CS0_CONFIG_800
208 #define CONFIG_SYS_DDR_CONTROL CONFIG_SYS_DDR_CONTROL_800
209 #define CONFIG_SYS_DDR_CONTROL_2 CONFIG_SYS_DDR_CONTROL_2_800
210 #define CONFIG_SYS_DDR_TIMING_4 CONFIG_SYS_DDR_TIMING_4_800
211 #define CONFIG_SYS_DDR_TIMING_5 CONFIG_SYS_DDR_TIMING_5_800
215 /* relocated CCSRBAR */
216 #define CONFIG_SYS_CCSRBAR CONFIG_SYS_CCSRBAR_DEFAULT
217 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR_DEFAULT
219 #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR
224 /* NOR Flash on IFC */
225 #define CONFIG_SYS_FLASH_BASE 0x88000000
226 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* Max number of sector: 32M */
228 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
230 #define CONFIG_SYS_NOR_CSPR 0x88000101
231 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
232 #define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(5)
233 /* NOR Flash Timing Params */
235 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x01) \
236 | FTIM0_NOR_TEADC(0x03) \
237 | FTIM0_NOR_TAVDS(0x00) \
238 | FTIM0_NOR_TEAHC(0x0f))
239 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x1d) \
240 | FTIM1_NOR_TRAD_NOR(0x09) \
241 | FTIM1_NOR_TSEQRAD_NOR(0x09))
242 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x1) \
243 | FTIM2_NOR_TCH(0x4) \
244 | FTIM2_NOR_TWPH(0x7) \
245 | FTIM2_NOR_TWP(0x1e))
246 #define CONFIG_SYS_NOR_FTIM3 0x0
248 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
249 #define CONFIG_SYS_FLASH_QUIET_TEST
250 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
251 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
253 #undef CONFIG_SYS_FLASH_CHECKSUM
254 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
255 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
257 /* CFI for NOR Flash */
258 #define CONFIG_FLASH_CFI_DRIVER
259 #define CONFIG_SYS_FLASH_CFI
260 #define CONFIG_SYS_FLASH_EMPTY_INFO
261 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
263 /* NAND Flash on IFC */
264 #define CONFIG_SYS_NAND_BASE 0xff800000
265 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
267 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
268 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
269 | CSPR_MSEL_NAND /* MSEL = NAND */ \
271 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
273 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
274 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
275 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
276 | CSOR_NAND_RAL_2 /* RAL = 2Byes */ \
277 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \
278 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
279 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
281 /* NAND Flash Timing Params */
282 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x03) \
283 | FTIM0_NAND_TWP(0x05) \
284 | FTIM0_NAND_TWCHT(0x02) \
285 | FTIM0_NAND_TWH(0x04))
286 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x1c) \
287 | FTIM1_NAND_TWBE(0x1e) \
288 | FTIM1_NAND_TRR(0x07) \
289 | FTIM1_NAND_TRP(0x05))
290 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x08) \
291 | FTIM2_NAND_TREH(0x04) \
292 | FTIM2_NAND_TWHRE(0x11))
293 #define CONFIG_SYS_NAND_FTIM3 FTIM3_NAND_TWW(0x04)
295 #define CONFIG_SYS_NAND_DDR_LAW 11
298 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
299 #define CONFIG_SYS_MAX_NAND_DEVICE 1
300 #define CONFIG_MTD_NAND_VERIFY_WRITE
301 #define CONFIG_CMD_NAND
303 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
305 #define CONFIG_FSL_QIXIS
306 #ifdef CONFIG_FSL_QIXIS
307 #define CONFIG_SYS_FPGA_BASE 0xffb00000
308 #define CONFIG_SYS_I2C_FPGA_ADDR 0x66
309 #define QIXIS_BASE CONFIG_SYS_FPGA_BASE
310 #define QIXIS_LBMAP_SWITCH 9
311 #define QIXIS_LBMAP_MASK 0x07
312 #define QIXIS_LBMAP_SHIFT 0
313 #define QIXIS_LBMAP_DFLTBANK 0x00
314 #define QIXIS_LBMAP_ALTBANK 0x04
315 #define QIXIS_RST_CTL_RESET 0x83
316 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
317 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21
318 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
320 #define CONFIG_SYS_FPGA_BASE_PHYS CONFIG_SYS_FPGA_BASE
322 #define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_FPGA_BASE) \
326 #define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024)
327 #define CONFIG_SYS_CSOR2 0x0
328 /* CPLD Timing parameters for IFC CS3 */
329 #define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
330 FTIM0_GPCM_TEADC(0x0e) | \
331 FTIM0_GPCM_TEAHC(0x0e))
332 #define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \
333 FTIM1_GPCM_TRAD(0x1f))
334 #define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
335 FTIM2_GPCM_TCH(0x0) | \
336 FTIM2_GPCM_TWP(0x1f))
337 #define CONFIG_SYS_CS2_FTIM3 0x0
340 /* Set up IFC registers for boot location NOR/NAND */
341 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR
342 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
343 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
344 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
345 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
346 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
347 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
348 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR
349 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK
350 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR
351 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0
352 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1
353 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2
354 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3
356 #define CONFIG_BOARD_EARLY_INIT_F /* Call board_pre_init */
357 #define CONFIG_BOARD_EARLY_INIT_R
359 #define CONFIG_SYS_INIT_RAM_LOCK
360 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */
361 #define CONFIG_SYS_INIT_RAM_END 0x00004000 /* End of used area in RAM */
363 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END \
364 - GENERATED_GBL_DATA_SIZE)
365 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
367 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon*/
368 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc*/
371 #define CONFIG_CONS_INDEX 1
372 #undef CONFIG_SERIAL_SOFTWARE_FIFO
373 #define CONFIG_SYS_NS16550
374 #define CONFIG_SYS_NS16550_SERIAL
375 #define CONFIG_SYS_NS16550_REG_SIZE 1
376 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
378 #define CONFIG_SERIAL_MULTI 1 /* Enable both serial ports */
379 #define CONFIG_SYS_CONSOLE_IS_IN_ENV /* determine from environment */
381 #define CONFIG_SYS_BAUDRATE_TABLE \
382 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
384 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR + 0x4500)
385 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR + 0x4600)
386 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR + 0x4700)
387 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR + 0x4800)
389 /* Use the HUSH parser */
390 #define CONFIG_SYS_HUSH_PARSER /* hush parser */
391 #ifdef CONFIG_SYS_HUSH_PARSER
392 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
396 * Pass open firmware flat tree
398 #define CONFIG_OF_LIBFDT
399 #define CONFIG_OF_BOARD_SETUP
400 #define CONFIG_OF_STDOUT_VIA_ALIAS
402 /* new uImage format support */
404 #define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */
406 #define CONFIG_FSL_I2C /* Use FSL common I2C driver */
407 #define CONFIG_HARD_I2C /* I2C with hardware support */
408 #undef CONFIG_SOFT_I2C /* I2C bit-banged */
409 #define CONFIG_I2C_MULTI_BUS
410 #define CONFIG_I2C_CMD_TREE
411 #define CONFIG_SYS_I2C_SPEED 400800 /* I2C speed and slave address*/
412 #define CONFIG_SYS_I2C_SLAVE 0x7F
413 #define CONFIG_SYS_I2C_OFFSET 0x3000
414 #define CONFIG_SYS_I2C2_OFFSET 0x3100
417 #define CONFIG_ID_EEPROM
418 #ifdef CONFIG_ID_EEPROM
419 #define CONFIG_SYS_I2C_EEPROM_NXID
421 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
422 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
423 #define CONFIG_SYS_EEPROM_BUS_NUM 0
425 /* enable read and write access to EEPROM */
426 #define CONFIG_CMD_EEPROM
427 #define CONFIG_SYS_I2C_MULTI_EEPROMS
428 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
429 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
430 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
433 #define CONFIG_I2C_FPGA
434 #define CONFIG_SYS_I2C_FPGA_ADDR 0x66
436 #define CONFIG_RTC_DS3231
437 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
440 * SPI interface will not be available in case of NAND boot SPI CS0 will be
443 /* eSPI - Enhanced SPI */
444 #define CONFIG_FSL_ESPI /* SPI */
445 #ifdef CONFIG_FSL_ESPI
446 #define CONFIG_SPI_FLASH
447 #define CONFIG_SPI_FLASH_SPANSION
448 #define CONFIG_CMD_SF
449 #define CONFIG_SF_DEFAULT_SPEED 10000000
450 #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
453 #if defined(CONFIG_TSEC_ENET)
455 #define CONFIG_MII /* MII PHY management */
456 #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */
457 #define CONFIG_TSEC1 1
458 #define CONFIG_TSEC1_NAME "eTSEC1"
459 #define CONFIG_TSEC2 1
460 #define CONFIG_TSEC2_NAME "eTSEC2"
462 #define TSEC1_PHY_ADDR 0
463 #define TSEC2_PHY_ADDR 1
465 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
466 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
468 #define TSEC1_PHYIDX 0
469 #define TSEC2_PHYIDX 0
471 #define CONFIG_ETHPRIME "eTSEC1"
473 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
475 /* TBI PHY configuration for SGMII mode */
476 #define CONFIG_TSEC_TBICR_SETTINGS ( \
478 | TBICR_ANEG_ENABLE \
479 | TBICR_FULL_DUPLEX \
483 #endif /* CONFIG_TSEC_ENET */
487 #define CONFIG_CMD_MMC
488 #define CONFIG_DOS_PARTITION
489 #define CONFIG_FSL_ESDHC
490 #define CONFIG_GENERIC_MMC
491 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
494 #define CONFIG_USB_EHCI /* USB */
495 #ifdef CONFIG_USB_EHCI
496 #define CONFIG_CMD_USB
497 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
498 #define CONFIG_USB_EHCI_FSL
499 #define CONFIG_USB_STORAGE
500 #define CONFIG_HAS_FSL_DR_USB
506 #if defined(CONFIG_SYS_RAMBOOT)
507 #if defined(CONFIG_RAMBOOT_SDCARD)
508 #define CONFIG_ENV_IS_IN_MMC
509 #define CONFIG_SYS_MMC_ENV_DEV 0
510 #define CONFIG_ENV_SIZE 0x2000
511 #elif defined(CONFIG_RAMBOOT_SPIFLASH)
512 #define CONFIG_ENV_IS_IN_SPI_FLASH
513 #define CONFIG_ENV_SPI_BUS 0
514 #define CONFIG_ENV_SPI_CS 0
515 #define CONFIG_ENV_SPI_MAX_HZ 10000000
516 #define CONFIG_ENV_SPI_MODE 0
517 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
518 #define CONFIG_ENV_SECT_SIZE 0x10000
519 #define CONFIG_ENV_SIZE 0x2000
521 #define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */
522 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
523 #define CONFIG_ENV_SIZE 0x2000
526 #define CONFIG_ENV_IS_IN_FLASH
527 #if CONFIG_SYS_MONITOR_BASE > 0xfff80000
528 #define CONFIG_ENV_ADDR 0xfff80000
530 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
532 #define CONFIG_ENV_SIZE 0x2000
533 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
536 #define CONFIG_LOADS_ECHO /* echo on for serial download */
537 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
540 * Command line configuration.
542 #include <config_cmd_default.h>
544 #define CONFIG_CMD_DATE
545 #define CONFIG_CMD_DHCP
546 #define CONFIG_CMD_ELF
547 #define CONFIG_CMD_ERRATA
548 #define CONFIG_CMD_I2C
549 #define CONFIG_CMD_IRQ
550 #define CONFIG_CMD_MII
551 #define CONFIG_CMD_PING
552 #define CONFIG_CMD_SETEXPR
553 #define CONFIG_CMD_REGINFO
555 #if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI)
556 #define CONFIG_CMD_EXT2
557 #define CONFIG_CMD_FAT
558 #define CONFIG_DOS_PARTITION
562 * Miscellaneous configurable options
564 #define CONFIG_SYS_LONGHELP /* undef to save memory */
565 #define CONFIG_CMDLINE_EDITING /* Command-line editing */
566 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */
567 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
568 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
570 #if defined(CONFIG_CMD_KGDB)
571 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
573 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
575 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
576 /* Print Buffer Size */
577 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
578 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
579 #define CONFIG_SYS_HZ 1000 /* decrementer freq:1ms ticks */
583 * For booting Linux, the board info and command line data
584 * have to be in the first 64 MB of memory, since this is
585 * the maximum mapped by the Linux kernel during initialization.
587 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux */
588 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
590 #if defined(CONFIG_CMD_KGDB)
591 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
592 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
596 * Environment Configuration
599 #if defined(CONFIG_TSEC_ENET)
600 #define CONFIG_HAS_ETH0
601 #define CONFIG_HAS_ETH1
604 #define CONFIG_HOSTNAME BSC9132qds
605 #define CONFIG_ROOTPATH "/opt/nfsroot"
606 #define CONFIG_BOOTFILE "uImage"
607 #define CONFIG_UBOOTPATH "u-boot.bin"
609 #define CONFIG_BAUDRATE 115200
612 #define CONFIG_DEF_HWCONFIG "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0"
614 #define CONFIG_DEF_HWCONFIG "hwconfig=sim;usb1:dr_mode=host,phy_type=ulpi\0"
617 #define CONFIG_EXTRA_ENV_SETTINGS \
619 "uboot=" CONFIG_UBOOTPATH "\0" \
620 "loadaddr=1000000\0" \
621 "bootfile=uImage\0" \
622 "consoledev=ttyS0\0" \
623 "ramdiskaddr=2000000\0" \
624 "ramdiskfile=rootfs.ext2.gz.uboot\0" \
626 "fdtfile=bsc9132qds.dtb\0" \
629 "othbootargs=mem=880M ramdisk_size=600000 " \
630 "default_hugepagesz=256m hugepagesz=256m hugepages=1 " \
632 "usbext2boot=setenv bootargs root=/dev/ram rw " \
633 "console=$consoledev,$baudrate $othbootargs; " \
635 "ext2load usb 0:4 $loadaddr $bootfile;" \
636 "ext2load usb 0:4 $fdtaddr $fdtfile;" \
637 "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \
638 "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \
639 "debug_halt_off=mw ff7e0e30 0xf0000000;"
641 #define CONFIG_NFSBOOTCOMMAND \
642 "setenv bootargs root=/dev/nfs rw " \
643 "nfsroot=$serverip:$rootpath " \
644 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
645 "console=$consoledev,$baudrate $othbootargs;" \
646 "tftp $loadaddr $bootfile;" \
647 "tftp $fdtaddr $fdtfile;" \
648 "bootm $loadaddr - $fdtaddr"
650 #define CONFIG_HDBOOT \
651 "setenv bootargs root=/dev/$bdev rw rootdelay=30 " \
652 "console=$consoledev,$baudrate $othbootargs;" \
654 "ext2load usb 0:1 $loadaddr /boot/$bootfile;" \
655 "ext2load usb 0:1 $fdtaddr /boot/$fdtfile;" \
656 "bootm $loadaddr - $fdtaddr"
658 #define CONFIG_RAMBOOTCOMMAND \
659 "setenv bootargs root=/dev/ram rw " \
660 "console=$consoledev,$baudrate $othbootargs; " \
661 "tftp $ramdiskaddr $ramdiskfile;" \
662 "tftp $loadaddr $bootfile;" \
663 "tftp $fdtaddr $fdtfile;" \
664 "bootm $loadaddr $ramdiskaddr $fdtaddr"
666 #define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND
668 #endif /* __CONFIG_H */