Merge branch 'master' of git://git.denx.de/u-boot-arm
[platform/kernel/u-boot.git] / include / configs / BSC9132QDS.h
1 /*
2  * Copyright 2013 Freescale Semiconductor, Inc.
3  *
4  * SPDX-License-Identifier:     GPL-2.0+
5  */
6
7 /*
8  * BSC9132 QDS board configuration file
9  */
10
11 #ifndef __CONFIG_H
12 #define __CONFIG_H
13
14 #ifdef CONFIG_BSC9132QDS
15 #define CONFIG_BSC9132
16 #endif
17
18 #define CONFIG_MISC_INIT_R
19
20 #ifdef CONFIG_SDCARD
21 #define CONFIG_RAMBOOT_SDCARD
22 #define CONFIG_SYS_RAMBOOT
23 #define CONFIG_SYS_EXTRA_ENV_RELOC
24 #define CONFIG_SYS_TEXT_BASE            0x11000000
25 #define CONFIG_RESET_VECTOR_ADDRESS     0x110bfffc
26 #endif
27 #define CONFIG_SYS_FSL_ERRATUM_IFC_A002769      1
28 #ifdef CONFIG_SPIFLASH
29 #define CONFIG_RAMBOOT_SPIFLASH
30 #define CONFIG_SYS_RAMBOOT
31 #define CONFIG_SYS_EXTRA_ENV_RELOC
32 #define CONFIG_SYS_TEXT_BASE            0x11000000
33 #define CONFIG_RESET_VECTOR_ADDRESS     0x110bfffc
34 #endif
35
36 #ifdef CONFIG_NAND
37 #define CONFIG_SPL
38 #define CONFIG_SPL_INIT_MINIMAL
39 #define CONFIG_SPL_SERIAL_SUPPORT
40 #define CONFIG_SPL_NAND_SUPPORT
41 #define CONFIG_SPL_NAND_BOOT
42 #define CONFIG_SPL_FLUSH_IMAGE
43 #define CONFIG_SPL_TARGET               "u-boot-with-spl.bin"
44
45 #define CONFIG_SYS_TEXT_BASE            0x00201000
46 #define CONFIG_SPL_TEXT_BASE            0xFFFFE000
47 #define CONFIG_SPL_MAX_SIZE             8192
48 #define CONFIG_SPL_RELOC_TEXT_BASE      0x00100000
49 #define CONFIG_SPL_RELOC_STACK          0x00100000
50 #define CONFIG_SYS_NAND_U_BOOT_SIZE     ((768 << 10) - 0x2000)
51 #define CONFIG_SYS_NAND_U_BOOT_DST      (0x00200000 - CONFIG_SPL_MAX_SIZE)
52 #define CONFIG_SYS_NAND_U_BOOT_START    0x00200000
53 #define CONFIG_SYS_NAND_U_BOOT_OFFS     0
54 #define CONFIG_SYS_LDSCRIPT     "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
55 #endif
56
57 #ifndef CONFIG_SYS_TEXT_BASE
58 #define CONFIG_SYS_TEXT_BASE            0x8ff40000
59 #endif
60
61 #ifndef CONFIG_RESET_VECTOR_ADDRESS
62 #define CONFIG_RESET_VECTOR_ADDRESS     0x8ffffffc
63 #endif
64
65 #ifdef CONFIG_SPL_BUILD
66 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
67 #else
68 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
69 #endif
70
71 /* High Level Configuration Options */
72 #define CONFIG_BOOKE                    /* BOOKE */
73 #define CONFIG_E500                     /* BOOKE e500 family */
74 #define CONFIG_FSL_IFC                  /* Enable IFC Support */
75 #define CONFIG_SYS_HAS_SERDES           /* common SERDES init code */
76
77 #define CONFIG_PCI                      /* Enable PCI/PCIE */
78 #if defined(CONFIG_PCI)
79 #define CONFIG_PCIE1                    /* PCIE controler 1 (slot 1) */
80 #define CONFIG_FSL_PCI_INIT             /* Use common FSL init code */
81 #define CONFIG_PCI_INDIRECT_BRIDGE      /* indirect PCI bridge support */
82 #define CONFIG_FSL_PCIE_RESET           /* need PCIe reset errata */
83 #define CONFIG_SYS_PCI_64BIT            /* enable 64-bit PCI resources */
84
85 #define CONFIG_CMD_NET
86 #define CONFIG_CMD_PCI
87
88 #define CONFIG_E1000                    /*  E1000 pci Ethernet card*/
89
90 /*
91  * PCI Windows
92  * Memory space is mapped 1-1, but I/O space must start from 0.
93  */
94 /* controller 1, Slot 1, tgtid 1, Base address a000 */
95 #define CONFIG_SYS_PCIE1_NAME           "PCIe Slot"
96 #define CONFIG_SYS_PCIE1_MEM_VIRT       0x90000000
97 #define CONFIG_SYS_PCIE1_MEM_BUS        0x90000000
98 #define CONFIG_SYS_PCIE1_MEM_PHYS       0x90000000
99 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x10000000      /* 256M */
100 #define CONFIG_SYS_PCIE1_IO_VIRT        0xC0010000
101 #define CONFIG_SYS_PCIE1_IO_BUS         0x00000000
102 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00010000      /* 64k */
103 #define CONFIG_SYS_PCIE1_IO_PHYS        0xC0010000
104
105 #define CONFIG_PCI_PNP                  /* do pci plug-and-play */
106
107 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
108 #define CONFIG_DOS_PARTITION
109 #endif
110
111 #define CONFIG_FSL_LAW                  /* Use common FSL init code */
112 #define CONFIG_ENV_OVERWRITE
113 #define CONFIG_TSEC_ENET /* ethernet */
114
115 #if defined(CONFIG_SYS_CLK_100_DDR_100)
116 #define CONFIG_SYS_CLK_FREQ     100000000
117 #define CONFIG_DDR_CLK_FREQ     100000000
118 #elif defined(CONFIG_SYS_CLK_100_DDR_133)
119 #define CONFIG_SYS_CLK_FREQ     100000000
120 #define CONFIG_DDR_CLK_FREQ     133000000
121 #endif
122
123 #define CONFIG_MP
124
125 #define CONFIG_HWCONFIG
126 /*
127  * These can be toggled for performance analysis, otherwise use default.
128  */
129 #define CONFIG_L2_CACHE                 /* toggle L2 cache */
130 #define CONFIG_BTB                      /* enable branch predition */
131
132 #define CONFIG_SYS_MEMTEST_START        0x01000000      /* memtest works on */
133 #define CONFIG_SYS_MEMTEST_END          0x01ffffff
134
135 /* DDR Setup */
136 #define CONFIG_SYS_FSL_DDR3
137 #define CONFIG_SYS_SPD_BUS_NUM          0
138 #define SPD_EEPROM_ADDRESS1             0x54 /* I2C access */
139 #define SPD_EEPROM_ADDRESS2             0x56 /* I2C access */
140 #define CONFIG_FSL_DDR_INTERACTIVE
141
142 #define CONFIG_MEM_INIT_VALUE           0xDeadBeef
143
144 #define CONFIG_SYS_SDRAM_SIZE           (1024)
145 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
146 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
147
148 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
149
150 /* DDR3 Controller Settings */
151 #define CONFIG_CHIP_SELECTS_PER_CTRL    1
152 #define CONFIG_SYS_DDR_CS0_BNDS         0x0000003F
153 #define CONFIG_SYS_DDR_CS0_CONFIG_1333  0x80004302
154 #define CONFIG_SYS_DDR_CS0_CONFIG_800   0x80014302
155 #define CONFIG_SYS_DDR_CS0_CONFIG_2     0x00000000
156 #define CONFIG_SYS_DDR_DATA_INIT        0xdeadbeef
157 #define CONFIG_SYS_DDR_INIT_ADDR        0x00000000
158 #define CONFIG_SYS_DDR_INIT_EXT_ADDR    0x00000000
159 #define CONFIG_SYS_DDR_MODE_CONTROL     0x00000000
160 #define CONFIG_SYS_DDR1_CS0_BNDS       0x0040007F
161
162 #define CONFIG_SYS_DDR_ZQ_CONTROL       0x89080600
163 #define CONFIG_SYS_DDR_SR_CNTR          0x00000000
164 #define CONFIG_SYS_DDR_RCW_1            0x00000000
165 #define CONFIG_SYS_DDR_RCW_2            0x00000000
166 #define CONFIG_SYS_DDR_CONTROL_800              0x470C0000
167 #define CONFIG_SYS_DDR_CONTROL_2_800    0x04401050
168 #define CONFIG_SYS_DDR_TIMING_4_800             0x00220001
169 #define CONFIG_SYS_DDR_TIMING_5_800             0x03402400
170
171 #define CONFIG_SYS_DDR_CONTROL_1333             0x470C0008
172 #define CONFIG_SYS_DDR_CONTROL_2_1333   0x24401010
173 #define CONFIG_SYS_DDR_TIMING_4_1333            0x00000001
174 #define CONFIG_SYS_DDR_TIMING_5_1333            0x03401400
175
176 #define CONFIG_SYS_DDR_TIMING_3_800             0x00020000
177 #define CONFIG_SYS_DDR_TIMING_0_800             0x00330004
178 #define CONFIG_SYS_DDR_TIMING_1_800             0x6f6B4846
179 #define CONFIG_SYS_DDR_TIMING_2_800             0x0FA8C8CF
180 #define CONFIG_SYS_DDR_CLK_CTRL_800             0x03000000
181 #define CONFIG_SYS_DDR_MODE_1_800               0x40461520
182 #define CONFIG_SYS_DDR_MODE_2_800               0x8000c000
183 #define CONFIG_SYS_DDR_INTERVAL_800             0x0C300000
184 #define CONFIG_SYS_DDR_WRLVL_CONTROL_800        0x8655A608
185
186 #define CONFIG_SYS_DDR_TIMING_3_1333            0x01061000
187 #define CONFIG_SYS_DDR_TIMING_0_1333            0x00440104
188 #define CONFIG_SYS_DDR_TIMING_1_1333            0x98913A45
189 #define CONFIG_SYS_DDR_TIMING_2_1333            0x0FB8B114
190 #define CONFIG_SYS_DDR_CLK_CTRL_1333            0x02800000
191 #define CONFIG_SYS_DDR_MODE_1_1333              0x00061A50
192 #define CONFIG_SYS_DDR_MODE_2_1333              0x00100000
193 #define CONFIG_SYS_DDR_INTERVAL_1333            0x144E0513
194 #define CONFIG_SYS_DDR_WRLVL_CONTROL_1333       0x8655F607
195
196 /*FIXME: the following params are constant w.r.t diff freq
197 combinations. this should be removed later
198 */
199 #if CONFIG_DDR_CLK_FREQ == 100000000
200 #define CONFIG_SYS_DDR_CS0_CONFIG CONFIG_SYS_DDR_CS0_CONFIG_800
201 #define CONFIG_SYS_DDR_CONTROL          CONFIG_SYS_DDR_CONTROL_800
202 #define CONFIG_SYS_DDR_CONTROL_2 CONFIG_SYS_DDR_CONTROL_2_800
203 #define CONFIG_SYS_DDR_TIMING_4 CONFIG_SYS_DDR_TIMING_4_800
204 #define CONFIG_SYS_DDR_TIMING_5 CONFIG_SYS_DDR_TIMING_5_800
205 #elif CONFIG_DDR_CLK_FREQ == 133000000
206 #define CONFIG_SYS_DDR_CS0_CONFIG CONFIG_SYS_DDR_CS0_CONFIG_1333
207 #define CONFIG_SYS_DDR_CONTROL          CONFIG_SYS_DDR_CONTROL_1333
208 #define CONFIG_SYS_DDR_CONTROL_2        CONFIG_SYS_DDR_CONTROL_2_1333
209 #define CONFIG_SYS_DDR_TIMING_4 CONFIG_SYS_DDR_TIMING_4_1333
210 #define CONFIG_SYS_DDR_TIMING_5 CONFIG_SYS_DDR_TIMING_5_1333
211 #else
212 #define CONFIG_SYS_DDR_CS0_CONFIG CONFIG_SYS_DDR_CS0_CONFIG_800
213 #define CONFIG_SYS_DDR_CONTROL          CONFIG_SYS_DDR_CONTROL_800
214 #define CONFIG_SYS_DDR_CONTROL_2        CONFIG_SYS_DDR_CONTROL_2_800
215 #define CONFIG_SYS_DDR_TIMING_4 CONFIG_SYS_DDR_TIMING_4_800
216 #define CONFIG_SYS_DDR_TIMING_5 CONFIG_SYS_DDR_TIMING_5_800
217 #endif
218
219
220 /* relocated CCSRBAR */
221 #define CONFIG_SYS_CCSRBAR      CONFIG_SYS_CCSRBAR_DEFAULT
222 #define CONFIG_SYS_CCSRBAR_PHYS_LOW     CONFIG_SYS_CCSRBAR_DEFAULT
223
224 #define CONFIG_SYS_IMMR         CONFIG_SYS_CCSRBAR
225
226 /* DSP CCSRBAR */
227 #define CONFIG_SYS_FSL_DSP_CCSRBAR      CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT
228 #define CONFIG_SYS_FSL_DSP_CCSRBAR_PHYS CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT
229
230 /*
231  * IFC Definitions
232  */
233 /* NOR Flash on IFC */
234
235 #ifdef CONFIG_SPL_BUILD
236 #define CONFIG_SYS_NO_FLASH
237 #endif
238 #define CONFIG_SYS_FLASH_BASE           0x88000000
239 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /* Max number of sector: 32M */
240
241 #define CONFIG_SYS_FLASH_BASE_PHYS      CONFIG_SYS_FLASH_BASE
242
243 #define CONFIG_SYS_NOR_CSPR     0x88000101
244 #define CONFIG_SYS_NOR_AMASK    IFC_AMASK(128*1024*1024)
245 #define CONFIG_SYS_NOR_CSOR     CSOR_NOR_ADM_SHIFT(5)
246 /* NOR Flash Timing Params */
247
248 #define CONFIG_SYS_NOR_FTIM0    (FTIM0_NOR_TACSE(0x01) \
249                                 | FTIM0_NOR_TEADC(0x03) \
250                                 | FTIM0_NOR_TAVDS(0x00) \
251                                 | FTIM0_NOR_TEAHC(0x0f))
252 #define CONFIG_SYS_NOR_FTIM1    (FTIM1_NOR_TACO(0x1d) \
253                                 | FTIM1_NOR_TRAD_NOR(0x09) \
254                                 | FTIM1_NOR_TSEQRAD_NOR(0x09))
255 #define CONFIG_SYS_NOR_FTIM2    (FTIM2_NOR_TCS(0x1) \
256                                 | FTIM2_NOR_TCH(0x4) \
257                                 | FTIM2_NOR_TWPH(0x7) \
258                                 | FTIM2_NOR_TWP(0x1e))
259 #define CONFIG_SYS_NOR_FTIM3    0x0
260
261 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS}
262 #define CONFIG_SYS_FLASH_QUIET_TEST
263 #define CONFIG_FLASH_SHOW_PROGRESS      45      /* count down from 45/5: 9..1 */
264 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* number of banks */
265
266 #undef CONFIG_SYS_FLASH_CHECKSUM
267 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
268 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
269
270 /* CFI for NOR Flash */
271 #define CONFIG_FLASH_CFI_DRIVER
272 #define CONFIG_SYS_FLASH_CFI
273 #define CONFIG_SYS_FLASH_EMPTY_INFO
274 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
275
276 /* NAND Flash on IFC */
277 #define CONFIG_SYS_NAND_BASE            0xff800000
278 #define CONFIG_SYS_NAND_BASE_PHYS       CONFIG_SYS_NAND_BASE
279
280 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
281                                 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
282                                 | CSPR_MSEL_NAND        /* MSEL = NAND */ \
283                                 | CSPR_V)
284 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64*1024)
285
286 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
287                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
288                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
289                                 | CSOR_NAND_RAL_2       /* RAL = 2Byes */ \
290                                 | CSOR_NAND_PGS_2K      /* Page Size = 2K */ \
291                                 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
292                                 | CSOR_NAND_PB(64))     /*Pages Per Block = 64*/
293
294 /* NAND Flash Timing Params */
295 #define CONFIG_SYS_NAND_FTIM0           (FTIM0_NAND_TCCST(0x03) \
296                                         | FTIM0_NAND_TWP(0x05) \
297                                         | FTIM0_NAND_TWCHT(0x02) \
298                                         | FTIM0_NAND_TWH(0x04))
299 #define CONFIG_SYS_NAND_FTIM1           (FTIM1_NAND_TADLE(0x1c) \
300                                         | FTIM1_NAND_TWBE(0x1e) \
301                                         | FTIM1_NAND_TRR(0x07) \
302                                         | FTIM1_NAND_TRP(0x05))
303 #define CONFIG_SYS_NAND_FTIM2           (FTIM2_NAND_TRAD(0x08) \
304                                         | FTIM2_NAND_TREH(0x04) \
305                                         | FTIM2_NAND_TWHRE(0x11))
306 #define CONFIG_SYS_NAND_FTIM3           FTIM3_NAND_TWW(0x04)
307
308 #define CONFIG_SYS_NAND_DDR_LAW         11
309
310 /* NAND */
311 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
312 #define CONFIG_SYS_MAX_NAND_DEVICE      1
313 #define CONFIG_MTD_NAND_VERIFY_WRITE
314 #define CONFIG_CMD_NAND
315
316 #define CONFIG_SYS_NAND_BLOCK_SIZE      (128 * 1024)
317
318 #ifndef CONFIG_SPL_BUILD
319 #define CONFIG_FSL_QIXIS
320 #endif
321 #ifdef CONFIG_FSL_QIXIS
322 #define CONFIG_SYS_FPGA_BASE    0xffb00000
323 #define CONFIG_SYS_I2C_FPGA_ADDR        0x66
324 #define QIXIS_BASE      CONFIG_SYS_FPGA_BASE
325 #define QIXIS_LBMAP_SWITCH      9
326 #define QIXIS_LBMAP_MASK        0x07
327 #define QIXIS_LBMAP_SHIFT       0
328 #define QIXIS_LBMAP_DFLTBANK            0x00
329 #define QIXIS_LBMAP_ALTBANK             0x04
330 #define QIXIS_RST_CTL_RESET             0x83
331 #define QIXIS_RCFG_CTL_RECONFIG_IDLE    0x20
332 #define QIXIS_RCFG_CTL_RECONFIG_START   0x21
333 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE   0x08
334
335 #define CONFIG_SYS_FPGA_BASE_PHYS       CONFIG_SYS_FPGA_BASE
336
337 #define CONFIG_SYS_CSPR2                (CSPR_PHYS_ADDR(CONFIG_SYS_FPGA_BASE) \
338                                         | CSPR_PORT_SIZE_8 \
339                                         | CSPR_MSEL_GPCM \
340                                         | CSPR_V)
341 #define CONFIG_SYS_AMASK2               IFC_AMASK(64*1024)
342 #define CONFIG_SYS_CSOR2                0x0
343 /* CPLD Timing parameters for IFC CS3 */
344 #define CONFIG_SYS_CS2_FTIM0            (FTIM0_GPCM_TACSE(0x0e) | \
345                                         FTIM0_GPCM_TEADC(0x0e) | \
346                                         FTIM0_GPCM_TEAHC(0x0e))
347 #define CONFIG_SYS_CS2_FTIM1            (FTIM1_GPCM_TACO(0x0e) | \
348                                         FTIM1_GPCM_TRAD(0x1f))
349 #define CONFIG_SYS_CS2_FTIM2            (FTIM2_GPCM_TCS(0x0e) | \
350                                         FTIM2_GPCM_TCH(0x0) | \
351                                         FTIM2_GPCM_TWP(0x1f))
352 #define CONFIG_SYS_CS2_FTIM3            0x0
353 #endif
354
355 /* Set up IFC registers for boot location NOR/NAND */
356 #if defined(CONFIG_NAND)
357 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
358 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
359 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
360 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
361 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
362 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
363 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
364 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR_CSPR
365 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
366 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
367 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
368 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
369 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
370 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
371 #else
372 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR_CSPR
373 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
374 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
375 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
376 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
377 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
378 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
379 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NAND_CSPR
380 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NAND_AMASK
381 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NAND_CSOR
382 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NAND_FTIM0
383 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NAND_FTIM1
384 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NAND_FTIM2
385 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NAND_FTIM3
386 #endif
387
388 #define CONFIG_BOARD_EARLY_INIT_F       /* Call board_pre_init */
389 #define CONFIG_BOARD_EARLY_INIT_R
390
391 #define CONFIG_SYS_INIT_RAM_LOCK
392 #define CONFIG_SYS_INIT_RAM_ADDR        0xffd00000      /* stack in RAM */
393 #define CONFIG_SYS_INIT_RAM_END         0x00004000 /* End of used area in RAM */
394
395 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_END \
396                                                 - GENERATED_GBL_DATA_SIZE)
397 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
398
399 #define CONFIG_SYS_MONITOR_LEN          (256 * 1024) /* Reserve 256 kB for Mon*/
400 #define CONFIG_SYS_MALLOC_LEN           (1024 * 1024)   /* Reserved for malloc*/
401
402 /* Serial Port */
403 #define CONFIG_CONS_INDEX       1
404 #undef  CONFIG_SERIAL_SOFTWARE_FIFO
405 #define CONFIG_SYS_NS16550
406 #define CONFIG_SYS_NS16550_SERIAL
407 #define CONFIG_SYS_NS16550_REG_SIZE     1
408 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
409 #ifdef CONFIG_SPL_BUILD
410 #define CONFIG_NS16550_MIN_FUNCTIONS
411 #endif
412
413 #define CONFIG_SERIAL_MULTI     1 /* Enable both serial ports */
414 #define CONFIG_SYS_CONSOLE_IS_IN_ENV    /* determine from environment */
415
416 #define CONFIG_SYS_BAUDRATE_TABLE       \
417         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
418
419 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR + 0x4500)
420 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR + 0x4600)
421 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR + 0x4700)
422 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR + 0x4800)
423
424 /* Use the HUSH parser */
425 #define CONFIG_SYS_HUSH_PARSER    /* hush parser */
426 #ifdef  CONFIG_SYS_HUSH_PARSER
427 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
428 #endif
429
430 /*
431  * Pass open firmware flat tree
432  */
433 #define CONFIG_OF_LIBFDT
434 #define CONFIG_OF_BOARD_SETUP
435 #define CONFIG_OF_STDOUT_VIA_ALIAS
436
437 /* new uImage format support */
438 #define CONFIG_FIT
439 #define CONFIG_FIT_VERBOSE      /* enable fit_format_{error,warning}() */
440
441 #define CONFIG_SYS_I2C
442 #define CONFIG_SYS_I2C_FSL
443 #define CONFIG_SYS_FSL_I2C_SPEED        400800 /* I2C speed and slave address*/
444 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
445 #define CONFIG_SYS_FSL_I2C2_SPEED       400800 /* I2C speed and slave address*/
446 #define CONFIG_SYS_FSL_I2C2_SLAVE       0x7F
447 #define CONFIG_SYS_FSL_I2C_OFFSET       0x3000
448 #define CONFIG_SYS_FSL_I2C2_OFFSET      0x3100
449
450 /* I2C EEPROM */
451 #define CONFIG_ID_EEPROM
452 #ifdef CONFIG_ID_EEPROM
453 #define CONFIG_SYS_I2C_EEPROM_NXID
454 #endif
455 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x57
456 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
457 #define CONFIG_SYS_EEPROM_BUS_NUM       0
458
459 /* enable read and write access to EEPROM */
460 #define CONFIG_CMD_EEPROM
461 #define CONFIG_SYS_I2C_MULTI_EEPROMS
462 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
463 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
464 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
465
466 /* I2C FPGA */
467 #define CONFIG_I2C_FPGA
468 #define CONFIG_SYS_I2C_FPGA_ADDR        0x66
469
470 #define CONFIG_RTC_DS3231
471 #define CONFIG_SYS_I2C_RTC_ADDR         0x68
472
473 /*
474  * SPI interface will not be available in case of NAND boot SPI CS0 will be
475  * used for SLIC
476  */
477 /* eSPI - Enhanced SPI */
478 #define CONFIG_FSL_ESPI  /* SPI */
479 #ifdef CONFIG_FSL_ESPI
480 #define CONFIG_SPI_FLASH
481 #define CONFIG_SPI_FLASH_SPANSION
482 #define CONFIG_CMD_SF
483 #define CONFIG_SF_DEFAULT_SPEED         10000000
484 #define CONFIG_SF_DEFAULT_MODE          SPI_MODE_0
485 #endif
486
487 #if defined(CONFIG_TSEC_ENET)
488
489 #define CONFIG_MII                      /* MII PHY management */
490 #define CONFIG_MII_DEFAULT_TSEC 1       /* Allow unregistered phys */
491 #define CONFIG_TSEC1    1
492 #define CONFIG_TSEC1_NAME       "eTSEC1"
493 #define CONFIG_TSEC2    1
494 #define CONFIG_TSEC2_NAME       "eTSEC2"
495
496 #define TSEC1_PHY_ADDR          0
497 #define TSEC2_PHY_ADDR          1
498
499 #define TSEC1_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
500 #define TSEC2_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
501
502 #define TSEC1_PHYIDX            0
503 #define TSEC2_PHYIDX            0
504
505 #define CONFIG_ETHPRIME         "eTSEC1"
506
507 #define CONFIG_PHY_GIGE         /* Include GbE speed/duplex detection */
508
509 /* TBI PHY configuration for SGMII mode */
510 #define CONFIG_TSEC_TBICR_SETTINGS ( \
511                 TBICR_PHY_RESET \
512                 | TBICR_ANEG_ENABLE \
513                 | TBICR_FULL_DUPLEX \
514                 | TBICR_SPEED1_SET \
515                 )
516
517 #endif  /* CONFIG_TSEC_ENET */
518
519 #define CONFIG_MMC
520 #ifdef CONFIG_MMC
521 #define CONFIG_CMD_MMC
522 #define CONFIG_DOS_PARTITION
523 #define CONFIG_FSL_ESDHC
524 #define CONFIG_GENERIC_MMC
525 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
526 #endif
527
528 #define CONFIG_USB_EHCI  /* USB */
529 #ifdef CONFIG_USB_EHCI
530 #define CONFIG_CMD_USB
531 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
532 #define CONFIG_USB_EHCI_FSL
533 #define CONFIG_USB_STORAGE
534 #define CONFIG_HAS_FSL_DR_USB
535 #endif
536
537 /*
538  * Environment
539  */
540 #if defined(CONFIG_RAMBOOT_SDCARD)
541 #define CONFIG_ENV_IS_IN_MMC
542 #define CONFIG_FSL_FIXED_MMC_LOCATION
543 #define CONFIG_SYS_MMC_ENV_DEV          0
544 #define CONFIG_ENV_SIZE                 0x2000
545 #elif defined(CONFIG_RAMBOOT_SPIFLASH)
546 #define CONFIG_ENV_IS_IN_SPI_FLASH
547 #define CONFIG_ENV_SPI_BUS      0
548 #define CONFIG_ENV_SPI_CS       0
549 #define CONFIG_ENV_SPI_MAX_HZ   10000000
550 #define CONFIG_ENV_SPI_MODE     0
551 #define CONFIG_ENV_OFFSET       0x100000        /* 1MB */
552 #define CONFIG_ENV_SECT_SIZE    0x10000
553 #define CONFIG_ENV_SIZE         0x2000
554 #elif defined(CONFIG_NAND)
555 #define CONFIG_ENV_IS_IN_NAND
556 #define CONFIG_ENV_SIZE         CONFIG_SYS_NAND_BLOCK_SIZE
557 #define CONFIG_ENV_OFFSET       ((768 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE)
558 #define CONFIG_ENV_RANGE        (3 * CONFIG_ENV_SIZE)
559 #elif defined(CONFIG_SYS_RAMBOOT)
560 #define CONFIG_ENV_IS_NOWHERE           /* Store ENV in memory only */
561 #define CONFIG_ENV_ADDR                 (CONFIG_SYS_MONITOR_BASE - 0x1000)
562 #define CONFIG_ENV_SIZE                 0x2000
563 #else
564 #define CONFIG_ENV_IS_IN_FLASH
565 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
566 #define CONFIG_ENV_SIZE         0x2000
567 #define CONFIG_ENV_SECT_SIZE    0x20000
568 #endif
569
570 #define CONFIG_LOADS_ECHO               /* echo on for serial download */
571 #define CONFIG_SYS_LOADS_BAUD_CHANGE    /* allow baudrate change */
572
573 /*
574  * Command line configuration.
575  */
576 #include <config_cmd_default.h>
577
578 #define CONFIG_CMD_DATE
579 #define CONFIG_CMD_DHCP
580 #define CONFIG_CMD_ELF
581 #define CONFIG_CMD_ERRATA
582 #define CONFIG_CMD_I2C
583 #define CONFIG_CMD_IRQ
584 #define CONFIG_CMD_MII
585 #define CONFIG_CMD_PING
586 #define CONFIG_CMD_SETEXPR
587 #define CONFIG_CMD_REGINFO
588
589 #if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI)
590 #define CONFIG_CMD_EXT2
591 #define CONFIG_CMD_FAT
592 #define CONFIG_DOS_PARTITION
593 #endif
594
595 /*
596  * Miscellaneous configurable options
597  */
598 #define CONFIG_SYS_LONGHELP                     /* undef to save memory */
599 #define CONFIG_CMDLINE_EDITING                  /* Command-line editing */
600 #define CONFIG_AUTO_COMPLETE                    /* add autocompletion support */
601 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
602
603 #if defined(CONFIG_CMD_KGDB)
604 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size */
605 #else
606 #define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size */
607 #endif
608 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
609                                                 /* Print Buffer Size */
610 #define CONFIG_SYS_MAXARGS      16              /* max number of command args */
611 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
612
613
614 /*
615  * For booting Linux, the board info and command line data
616  * have to be in the first 64 MB of memory, since this is
617  * the maximum mapped by the Linux kernel during initialization.
618  */
619 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20) /* Initial Memory map for Linux */
620 #define CONFIG_SYS_BOOTM_LEN    (64 << 20) /* Increase max gunzip size */
621
622 #if defined(CONFIG_CMD_KGDB)
623 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
624 #endif
625
626 /*
627  * Environment Configuration
628  */
629
630 #if defined(CONFIG_TSEC_ENET)
631 #define CONFIG_HAS_ETH0
632 #define CONFIG_HAS_ETH1
633 #endif
634
635 #define CONFIG_HOSTNAME         BSC9132qds
636 #define CONFIG_ROOTPATH         "/opt/nfsroot"
637 #define CONFIG_BOOTFILE         "uImage"
638 #define CONFIG_UBOOTPATH        "u-boot.bin"
639
640 #define CONFIG_BAUDRATE         115200
641
642 #ifdef CONFIG_SDCARD
643 #define CONFIG_DEF_HWCONFIG     "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0"
644 #else
645 #define CONFIG_DEF_HWCONFIG     "hwconfig=sim;usb1:dr_mode=host,phy_type=ulpi\0"
646 #endif
647
648 #define CONFIG_EXTRA_ENV_SETTINGS                               \
649         "netdev=eth0\0"                                         \
650         "uboot=" CONFIG_UBOOTPATH "\0"                          \
651         "loadaddr=1000000\0"                    \
652         "bootfile=uImage\0"     \
653         "consoledev=ttyS0\0"                            \
654         "ramdiskaddr=2000000\0"                 \
655         "ramdiskfile=rootfs.ext2.gz.uboot\0"            \
656         "fdtaddr=c00000\0"                              \
657         "fdtfile=bsc9132qds.dtb\0"              \
658         "bdev=sda1\0"   \
659         CONFIG_DEF_HWCONFIG\
660         "othbootargs=mem=880M ramdisk_size=600000 " \
661                 "default_hugepagesz=256m hugepagesz=256m hugepages=1 " \
662                 "isolcpus=0\0" \
663         "usbext2boot=setenv bootargs root=/dev/ram rw " \
664                 "console=$consoledev,$baudrate $othbootargs; "  \
665                 "usb start;"                    \
666                 "ext2load usb 0:4 $loadaddr $bootfile;"         \
667                 "ext2load usb 0:4 $fdtaddr $fdtfile;"   \
668                 "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;"   \
669                 "bootm $loadaddr $ramdiskaddr $fdtaddr\0"       \
670         "debug_halt_off=mw ff7e0e30 0xf0000000;"
671
672 #define CONFIG_NFSBOOTCOMMAND   \
673         "setenv bootargs root=/dev/nfs rw "     \
674         "nfsroot=$serverip:$rootpath "  \
675         "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
676         "console=$consoledev,$baudrate $othbootargs;" \
677         "tftp $loadaddr $bootfile;"     \
678         "tftp $fdtaddr $fdtfile;"       \
679         "bootm $loadaddr - $fdtaddr"
680
681 #define CONFIG_HDBOOT   \
682         "setenv bootargs root=/dev/$bdev rw rootdelay=30 "      \
683         "console=$consoledev,$baudrate $othbootargs;" \
684         "usb start;"    \
685         "ext2load usb 0:1 $loadaddr /boot/$bootfile;"   \
686         "ext2load usb 0:1 $fdtaddr /boot/$fdtfile;"     \
687         "bootm $loadaddr - $fdtaddr"
688
689 #define CONFIG_RAMBOOTCOMMAND           \
690         "setenv bootargs root=/dev/ram rw "     \
691         "console=$consoledev,$baudrate $othbootargs; "  \
692         "tftp $ramdiskaddr $ramdiskfile;"       \
693         "tftp $loadaddr $bootfile;"             \
694         "tftp $fdtaddr $fdtfile;"               \
695         "bootm $loadaddr $ramdiskaddr $fdtaddr"
696
697 #define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND
698
699 #endif  /* __CONFIG_H */