Merge branch 'master' of git://git.denx.de/u-boot-arm
[platform/kernel/u-boot.git] / include / configs / BSC9132QDS.h
1 /*
2  * Copyright 2013 Freescale Semiconductor, Inc.
3  *
4  * See file CREDITS for list of people who contributed to this
5  * project.
6  *
7  * This program is free software; you can redistribute it and/or
8  * modify it under the terms of the GNU General Public License as
9  * published by the Free Software Foundation; either version 2 of
10  * the License, or (at your option) any later version.
11  *
12  * This program is distributed in the hope that it will be useful,
13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
15  * GNU General Public License for more details.
16  *
17  * You should have received a copy of the GNU General Public License
18  * along with this program; if not, write to the Free Software
19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
20  * MA 02111-1307 USA
21  */
22
23 /*
24  * BSC9132 QDS board configuration file
25  */
26
27 #ifndef __CONFIG_H
28 #define __CONFIG_H
29
30 #ifdef CONFIG_BSC9132QDS
31 #define CONFIG_BSC9132
32 #endif
33
34 #define CONFIG_MISC_INIT_R
35
36 #ifdef CONFIG_SDCARD
37 #define CONFIG_RAMBOOT_SDCARD
38 #define CONFIG_SYS_RAMBOOT
39 #define CONFIG_SYS_EXTRA_ENV_RELOC
40 #define CONFIG_SYS_TEXT_BASE            0x11000000
41 #define CONFIG_RESET_VECTOR_ADDRESS     0x1107fffc
42 #endif
43 #define CONFIG_SYS_FSL_ERRATUM_IFC_A002769      1
44 #ifdef CONFIG_SPIFLASH
45 #define CONFIG_RAMBOOT_SPIFLASH
46 #define CONFIG_SYS_RAMBOOT
47 #define CONFIG_SYS_EXTRA_ENV_RELOC
48 #define CONFIG_SYS_TEXT_BASE            0x11000000
49 #define CONFIG_RESET_VECTOR_ADDRESS     0x1107fffc
50 #endif
51
52 #ifdef CONFIG_NAND
53 #define CONFIG_SPL
54 #define CONFIG_SPL_INIT_MINIMAL
55 #define CONFIG_SPL_SERIAL_SUPPORT
56 #define CONFIG_SPL_NAND_SUPPORT
57 #define CONFIG_SPL_NAND_MINIMAL
58 #define CONFIG_SPL_FLUSH_IMAGE
59 #define CONFIG_SPL_TARGET               "u-boot-with-spl.bin"
60
61 #define CONFIG_SYS_TEXT_BASE            0x00201000
62 #define CONFIG_SPL_TEXT_BASE            0xFFFFE000
63 #define CONFIG_SPL_MAX_SIZE             8192
64 #define CONFIG_SPL_RELOC_TEXT_BASE      0x00100000
65 #define CONFIG_SPL_RELOC_STACK          0x00100000
66 #define CONFIG_SYS_NAND_U_BOOT_SIZE     ((512 << 10) - 0x2000)
67 #define CONFIG_SYS_NAND_U_BOOT_DST      (0x00200000 - CONFIG_SPL_MAX_SIZE)
68 #define CONFIG_SYS_NAND_U_BOOT_START    0x00200000
69 #define CONFIG_SYS_NAND_U_BOOT_OFFS     0
70 #define CONFIG_SYS_LDSCRIPT     "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
71 #endif
72
73 #ifndef CONFIG_SYS_TEXT_BASE
74 #define CONFIG_SYS_TEXT_BASE            0x8ff80000
75 #endif
76
77 #ifndef CONFIG_RESET_VECTOR_ADDRESS
78 #define CONFIG_RESET_VECTOR_ADDRESS     0x8ffffffc
79 #endif
80
81 #ifdef CONFIG_SPL_BUILD
82 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
83 #else
84 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
85 #endif
86
87 /* High Level Configuration Options */
88 #define CONFIG_BOOKE                    /* BOOKE */
89 #define CONFIG_E500                     /* BOOKE e500 family */
90 #define CONFIG_MPC85xx
91 #define CONFIG_FSL_IFC                  /* Enable IFC Support */
92 #define CONFIG_SYS_HAS_SERDES           /* common SERDES init code */
93
94 #define CONFIG_PCI                      /* Enable PCI/PCIE */
95 #if defined(CONFIG_PCI)
96 #define CONFIG_PCIE1                    /* PCIE controler 1 (slot 1) */
97 #define CONFIG_FSL_PCI_INIT             /* Use common FSL init code */
98 #define CONFIG_PCI_INDIRECT_BRIDGE      /* indirect PCI bridge support */
99 #define CONFIG_FSL_PCIE_RESET           /* need PCIe reset errata */
100 #define CONFIG_SYS_PCI_64BIT            /* enable 64-bit PCI resources */
101
102 #define CONFIG_CMD_NET
103 #define CONFIG_CMD_PCI
104
105 #define CONFIG_E1000                    /*  E1000 pci Ethernet card*/
106
107 /*
108  * PCI Windows
109  * Memory space is mapped 1-1, but I/O space must start from 0.
110  */
111 /* controller 1, Slot 1, tgtid 1, Base address a000 */
112 #define CONFIG_SYS_PCIE1_NAME           "PCIe Slot"
113 #define CONFIG_SYS_PCIE1_MEM_VIRT       0x90000000
114 #define CONFIG_SYS_PCIE1_MEM_BUS        0x90000000
115 #define CONFIG_SYS_PCIE1_MEM_PHYS       0x90000000
116 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x10000000      /* 256M */
117 #define CONFIG_SYS_PCIE1_IO_VIRT        0xC0010000
118 #define CONFIG_SYS_PCIE1_IO_BUS         0x00000000
119 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00010000      /* 64k */
120 #define CONFIG_SYS_PCIE1_IO_PHYS        0xC0010000
121
122 #define CONFIG_PCI_PNP                  /* do pci plug-and-play */
123
124 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
125 #define CONFIG_DOS_PARTITION
126 #endif
127
128 #define CONFIG_FSL_LAW                  /* Use common FSL init code */
129 #define CONFIG_ENV_OVERWRITE
130 #define CONFIG_TSEC_ENET /* ethernet */
131
132 #if defined(CONFIG_SYS_CLK_100_DDR_100)
133 #define CONFIG_SYS_CLK_FREQ     100000000
134 #define CONFIG_DDR_CLK_FREQ     100000000
135 #elif defined(CONFIG_SYS_CLK_100_DDR_133)
136 #define CONFIG_SYS_CLK_FREQ     100000000
137 #define CONFIG_DDR_CLK_FREQ     133000000
138 #endif
139
140 #define CONFIG_MP
141
142 #define CONFIG_HWCONFIG
143 /*
144  * These can be toggled for performance analysis, otherwise use default.
145  */
146 #define CONFIG_L2_CACHE                 /* toggle L2 cache */
147 #define CONFIG_BTB                      /* enable branch predition */
148
149 #define CONFIG_SYS_MEMTEST_START        0x01000000      /* memtest works on */
150 #define CONFIG_SYS_MEMTEST_END          0x01ffffff
151
152 /* DDR Setup */
153 #define CONFIG_FSL_DDR3
154 #define CONFIG_SYS_SPD_BUS_NUM          0
155 #define SPD_EEPROM_ADDRESS1             0x54 /* I2C access */
156 #define SPD_EEPROM_ADDRESS2             0x56 /* I2C access */
157 #define CONFIG_FSL_DDR_INTERACTIVE
158
159 #define CONFIG_MEM_INIT_VALUE           0xDeadBeef
160
161 #define CONFIG_SYS_SDRAM_SIZE           (1024)
162 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
163 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
164
165 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
166
167 /* DDR3 Controller Settings */
168 #define CONFIG_CHIP_SELECTS_PER_CTRL    1
169 #define CONFIG_SYS_DDR_CS0_BNDS         0x0000003F
170 #define CONFIG_SYS_DDR_CS0_CONFIG_1333  0x80004302
171 #define CONFIG_SYS_DDR_CS0_CONFIG_800   0x80014302
172 #define CONFIG_SYS_DDR_CS0_CONFIG_2     0x00000000
173 #define CONFIG_SYS_DDR_DATA_INIT        0xdeadbeef
174 #define CONFIG_SYS_DDR_INIT_ADDR        0x00000000
175 #define CONFIG_SYS_DDR_INIT_EXT_ADDR    0x00000000
176 #define CONFIG_SYS_DDR_MODE_CONTROL     0x00000000
177 #define CONFIG_SYS_DDR1_CS0_BNDS       0x0040007F
178
179 #define CONFIG_SYS_DDR_ZQ_CONTROL       0x89080600
180 #define CONFIG_SYS_DDR_SR_CNTR          0x00000000
181 #define CONFIG_SYS_DDR_RCW_1            0x00000000
182 #define CONFIG_SYS_DDR_RCW_2            0x00000000
183 #define CONFIG_SYS_DDR_CONTROL_800              0x470C0000
184 #define CONFIG_SYS_DDR_CONTROL_2_800    0x04401050
185 #define CONFIG_SYS_DDR_TIMING_4_800             0x00220001
186 #define CONFIG_SYS_DDR_TIMING_5_800             0x03402400
187
188 #define CONFIG_SYS_DDR_CONTROL_1333             0x470C0008
189 #define CONFIG_SYS_DDR_CONTROL_2_1333   0x24401010
190 #define CONFIG_SYS_DDR_TIMING_4_1333            0x00000001
191 #define CONFIG_SYS_DDR_TIMING_5_1333            0x03401400
192
193 #define CONFIG_SYS_DDR_TIMING_3_800             0x00020000
194 #define CONFIG_SYS_DDR_TIMING_0_800             0x00330004
195 #define CONFIG_SYS_DDR_TIMING_1_800             0x6f6B4846
196 #define CONFIG_SYS_DDR_TIMING_2_800             0x0FA8C8CF
197 #define CONFIG_SYS_DDR_CLK_CTRL_800             0x03000000
198 #define CONFIG_SYS_DDR_MODE_1_800               0x40461520
199 #define CONFIG_SYS_DDR_MODE_2_800               0x8000c000
200 #define CONFIG_SYS_DDR_INTERVAL_800             0x0C300000
201 #define CONFIG_SYS_DDR_WRLVL_CONTROL_800        0x8655A608
202
203 #define CONFIG_SYS_DDR_TIMING_3_1333            0x01061000
204 #define CONFIG_SYS_DDR_TIMING_0_1333            0x00440104
205 #define CONFIG_SYS_DDR_TIMING_1_1333            0x98913A45
206 #define CONFIG_SYS_DDR_TIMING_2_1333            0x0FB8B114
207 #define CONFIG_SYS_DDR_CLK_CTRL_1333            0x02800000
208 #define CONFIG_SYS_DDR_MODE_1_1333              0x00061A50
209 #define CONFIG_SYS_DDR_MODE_2_1333              0x00100000
210 #define CONFIG_SYS_DDR_INTERVAL_1333            0x144E0513
211 #define CONFIG_SYS_DDR_WRLVL_CONTROL_1333       0x8655F607
212
213 /*FIXME: the following params are constant w.r.t diff freq
214 combinations. this should be removed later
215 */
216 #if CONFIG_DDR_CLK_FREQ == 100000000
217 #define CONFIG_SYS_DDR_CS0_CONFIG CONFIG_SYS_DDR_CS0_CONFIG_800
218 #define CONFIG_SYS_DDR_CONTROL          CONFIG_SYS_DDR_CONTROL_800
219 #define CONFIG_SYS_DDR_CONTROL_2 CONFIG_SYS_DDR_CONTROL_2_800
220 #define CONFIG_SYS_DDR_TIMING_4 CONFIG_SYS_DDR_TIMING_4_800
221 #define CONFIG_SYS_DDR_TIMING_5 CONFIG_SYS_DDR_TIMING_5_800
222 #elif CONFIG_DDR_CLK_FREQ == 133000000
223 #define CONFIG_SYS_DDR_CS0_CONFIG CONFIG_SYS_DDR_CS0_CONFIG_1333
224 #define CONFIG_SYS_DDR_CONTROL          CONFIG_SYS_DDR_CONTROL_1333
225 #define CONFIG_SYS_DDR_CONTROL_2        CONFIG_SYS_DDR_CONTROL_2_1333
226 #define CONFIG_SYS_DDR_TIMING_4 CONFIG_SYS_DDR_TIMING_4_1333
227 #define CONFIG_SYS_DDR_TIMING_5 CONFIG_SYS_DDR_TIMING_5_1333
228 #else
229 #define CONFIG_SYS_DDR_CS0_CONFIG CONFIG_SYS_DDR_CS0_CONFIG_800
230 #define CONFIG_SYS_DDR_CONTROL          CONFIG_SYS_DDR_CONTROL_800
231 #define CONFIG_SYS_DDR_CONTROL_2        CONFIG_SYS_DDR_CONTROL_2_800
232 #define CONFIG_SYS_DDR_TIMING_4 CONFIG_SYS_DDR_TIMING_4_800
233 #define CONFIG_SYS_DDR_TIMING_5 CONFIG_SYS_DDR_TIMING_5_800
234 #endif
235
236
237 /* relocated CCSRBAR */
238 #define CONFIG_SYS_CCSRBAR      CONFIG_SYS_CCSRBAR_DEFAULT
239 #define CONFIG_SYS_CCSRBAR_PHYS_LOW     CONFIG_SYS_CCSRBAR_DEFAULT
240
241 #define CONFIG_SYS_IMMR         CONFIG_SYS_CCSRBAR
242
243 /*
244  * IFC Definitions
245  */
246 /* NOR Flash on IFC */
247
248 #ifdef CONFIG_SPL_BUILD
249 #define CONFIG_SYS_NO_FLASH
250 #endif
251 #define CONFIG_SYS_FLASH_BASE           0x88000000
252 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /* Max number of sector: 32M */
253
254 #define CONFIG_SYS_FLASH_BASE_PHYS      CONFIG_SYS_FLASH_BASE
255
256 #define CONFIG_SYS_NOR_CSPR     0x88000101
257 #define CONFIG_SYS_NOR_AMASK    IFC_AMASK(128*1024*1024)
258 #define CONFIG_SYS_NOR_CSOR     CSOR_NOR_ADM_SHIFT(5)
259 /* NOR Flash Timing Params */
260
261 #define CONFIG_SYS_NOR_FTIM0    (FTIM0_NOR_TACSE(0x01) \
262                                 | FTIM0_NOR_TEADC(0x03) \
263                                 | FTIM0_NOR_TAVDS(0x00) \
264                                 | FTIM0_NOR_TEAHC(0x0f))
265 #define CONFIG_SYS_NOR_FTIM1    (FTIM1_NOR_TACO(0x1d) \
266                                 | FTIM1_NOR_TRAD_NOR(0x09) \
267                                 | FTIM1_NOR_TSEQRAD_NOR(0x09))
268 #define CONFIG_SYS_NOR_FTIM2    (FTIM2_NOR_TCS(0x1) \
269                                 | FTIM2_NOR_TCH(0x4) \
270                                 | FTIM2_NOR_TWPH(0x7) \
271                                 | FTIM2_NOR_TWP(0x1e))
272 #define CONFIG_SYS_NOR_FTIM3    0x0
273
274 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS}
275 #define CONFIG_SYS_FLASH_QUIET_TEST
276 #define CONFIG_FLASH_SHOW_PROGRESS      45      /* count down from 45/5: 9..1 */
277 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* number of banks */
278
279 #undef CONFIG_SYS_FLASH_CHECKSUM
280 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
281 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
282
283 /* CFI for NOR Flash */
284 #define CONFIG_FLASH_CFI_DRIVER
285 #define CONFIG_SYS_FLASH_CFI
286 #define CONFIG_SYS_FLASH_EMPTY_INFO
287 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
288
289 /* NAND Flash on IFC */
290 #define CONFIG_SYS_NAND_BASE            0xff800000
291 #define CONFIG_SYS_NAND_BASE_PHYS       CONFIG_SYS_NAND_BASE
292
293 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
294                                 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
295                                 | CSPR_MSEL_NAND        /* MSEL = NAND */ \
296                                 | CSPR_V)
297 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64*1024)
298
299 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
300                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
301                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
302                                 | CSOR_NAND_RAL_2       /* RAL = 2Byes */ \
303                                 | CSOR_NAND_PGS_2K      /* Page Size = 2K */ \
304                                 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
305                                 | CSOR_NAND_PB(64))     /*Pages Per Block = 64*/
306
307 /* NAND Flash Timing Params */
308 #define CONFIG_SYS_NAND_FTIM0           (FTIM0_NAND_TCCST(0x03) \
309                                         | FTIM0_NAND_TWP(0x05) \
310                                         | FTIM0_NAND_TWCHT(0x02) \
311                                         | FTIM0_NAND_TWH(0x04))
312 #define CONFIG_SYS_NAND_FTIM1           (FTIM1_NAND_TADLE(0x1c) \
313                                         | FTIM1_NAND_TWBE(0x1e) \
314                                         | FTIM1_NAND_TRR(0x07) \
315                                         | FTIM1_NAND_TRP(0x05))
316 #define CONFIG_SYS_NAND_FTIM2           (FTIM2_NAND_TRAD(0x08) \
317                                         | FTIM2_NAND_TREH(0x04) \
318                                         | FTIM2_NAND_TWHRE(0x11))
319 #define CONFIG_SYS_NAND_FTIM3           FTIM3_NAND_TWW(0x04)
320
321 #define CONFIG_SYS_NAND_DDR_LAW         11
322
323 /* NAND */
324 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
325 #define CONFIG_SYS_MAX_NAND_DEVICE      1
326 #define CONFIG_MTD_NAND_VERIFY_WRITE
327 #define CONFIG_CMD_NAND
328
329 #define CONFIG_SYS_NAND_BLOCK_SIZE      (128 * 1024)
330
331 #ifndef CONFIG_SPL_BUILD
332 #define CONFIG_FSL_QIXIS
333 #endif
334 #ifdef CONFIG_FSL_QIXIS
335 #define CONFIG_SYS_FPGA_BASE    0xffb00000
336 #define CONFIG_SYS_I2C_FPGA_ADDR        0x66
337 #define QIXIS_BASE      CONFIG_SYS_FPGA_BASE
338 #define QIXIS_LBMAP_SWITCH      9
339 #define QIXIS_LBMAP_MASK        0x07
340 #define QIXIS_LBMAP_SHIFT       0
341 #define QIXIS_LBMAP_DFLTBANK            0x00
342 #define QIXIS_LBMAP_ALTBANK             0x04
343 #define QIXIS_RST_CTL_RESET             0x83
344 #define QIXIS_RCFG_CTL_RECONFIG_IDLE    0x20
345 #define QIXIS_RCFG_CTL_RECONFIG_START   0x21
346 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE   0x08
347
348 #define CONFIG_SYS_FPGA_BASE_PHYS       CONFIG_SYS_FPGA_BASE
349
350 #define CONFIG_SYS_CSPR2                (CSPR_PHYS_ADDR(CONFIG_SYS_FPGA_BASE) \
351                                         | CSPR_PORT_SIZE_8 \
352                                         | CSPR_MSEL_GPCM \
353                                         | CSPR_V)
354 #define CONFIG_SYS_AMASK2               IFC_AMASK(64*1024)
355 #define CONFIG_SYS_CSOR2                0x0
356 /* CPLD Timing parameters for IFC CS3 */
357 #define CONFIG_SYS_CS2_FTIM0            (FTIM0_GPCM_TACSE(0x0e) | \
358                                         FTIM0_GPCM_TEADC(0x0e) | \
359                                         FTIM0_GPCM_TEAHC(0x0e))
360 #define CONFIG_SYS_CS2_FTIM1            (FTIM1_GPCM_TACO(0x0e) | \
361                                         FTIM1_GPCM_TRAD(0x1f))
362 #define CONFIG_SYS_CS2_FTIM2            (FTIM2_GPCM_TCS(0x0e) | \
363                                         FTIM2_GPCM_TCH(0x0) | \
364                                         FTIM2_GPCM_TWP(0x1f))
365 #define CONFIG_SYS_CS2_FTIM3            0x0
366 #endif
367
368 /* Set up IFC registers for boot location NOR/NAND */
369 #if defined(CONFIG_NAND)
370 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
371 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
372 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
373 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
374 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
375 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
376 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
377 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR_CSPR
378 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
379 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
380 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
381 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
382 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
383 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
384 #else
385 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR_CSPR
386 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
387 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
388 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
389 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
390 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
391 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
392 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NAND_CSPR
393 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NAND_AMASK
394 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NAND_CSOR
395 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NAND_FTIM0
396 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NAND_FTIM1
397 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NAND_FTIM2
398 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NAND_FTIM3
399 #endif
400
401 #define CONFIG_BOARD_EARLY_INIT_F       /* Call board_pre_init */
402 #define CONFIG_BOARD_EARLY_INIT_R
403
404 #define CONFIG_SYS_INIT_RAM_LOCK
405 #define CONFIG_SYS_INIT_RAM_ADDR        0xffd00000      /* stack in RAM */
406 #define CONFIG_SYS_INIT_RAM_END         0x00004000 /* End of used area in RAM */
407
408 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_END \
409                                                 - GENERATED_GBL_DATA_SIZE)
410 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
411
412 #define CONFIG_SYS_MONITOR_LEN          (256 * 1024) /* Reserve 256 kB for Mon*/
413 #define CONFIG_SYS_MALLOC_LEN           (1024 * 1024)   /* Reserved for malloc*/
414
415 /* Serial Port */
416 #define CONFIG_CONS_INDEX       1
417 #undef  CONFIG_SERIAL_SOFTWARE_FIFO
418 #define CONFIG_SYS_NS16550
419 #define CONFIG_SYS_NS16550_SERIAL
420 #define CONFIG_SYS_NS16550_REG_SIZE     1
421 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
422 #ifdef CONFIG_SPL_BUILD
423 #define CONFIG_NS16550_MIN_FUNCTIONS
424 #endif
425
426 #define CONFIG_SERIAL_MULTI     1 /* Enable both serial ports */
427 #define CONFIG_SYS_CONSOLE_IS_IN_ENV    /* determine from environment */
428
429 #define CONFIG_SYS_BAUDRATE_TABLE       \
430         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
431
432 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR + 0x4500)
433 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR + 0x4600)
434 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR + 0x4700)
435 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR + 0x4800)
436
437 /* Use the HUSH parser */
438 #define CONFIG_SYS_HUSH_PARSER    /* hush parser */
439 #ifdef  CONFIG_SYS_HUSH_PARSER
440 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
441 #endif
442
443 /*
444  * Pass open firmware flat tree
445  */
446 #define CONFIG_OF_LIBFDT
447 #define CONFIG_OF_BOARD_SETUP
448 #define CONFIG_OF_STDOUT_VIA_ALIAS
449
450 /* new uImage format support */
451 #define CONFIG_FIT
452 #define CONFIG_FIT_VERBOSE      /* enable fit_format_{error,warning}() */
453
454 #define CONFIG_FSL_I2C                  /* Use FSL common I2C driver */
455 #define CONFIG_HARD_I2C                 /* I2C with hardware support */
456 #undef CONFIG_SOFT_I2C                  /* I2C bit-banged */
457 #define CONFIG_I2C_MULTI_BUS
458 #define CONFIG_I2C_CMD_TREE
459 #define CONFIG_SYS_I2C_SPEED            400800 /* I2C speed and slave address*/
460 #define CONFIG_SYS_I2C_SLAVE            0x7F
461 #define CONFIG_SYS_I2C_OFFSET           0x3000
462 #define CONFIG_SYS_I2C2_OFFSET          0x3100
463
464 /* I2C EEPROM */
465 #define CONFIG_ID_EEPROM
466 #ifdef CONFIG_ID_EEPROM
467 #define CONFIG_SYS_I2C_EEPROM_NXID
468 #endif
469 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x57
470 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
471 #define CONFIG_SYS_EEPROM_BUS_NUM       0
472
473 /* enable read and write access to EEPROM */
474 #define CONFIG_CMD_EEPROM
475 #define CONFIG_SYS_I2C_MULTI_EEPROMS
476 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
477 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
478 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
479
480 /* I2C FPGA */
481 #define CONFIG_I2C_FPGA
482 #define CONFIG_SYS_I2C_FPGA_ADDR        0x66
483
484 #define CONFIG_RTC_DS3231
485 #define CONFIG_SYS_I2C_RTC_ADDR         0x68
486
487 /*
488  * SPI interface will not be available in case of NAND boot SPI CS0 will be
489  * used for SLIC
490  */
491 /* eSPI - Enhanced SPI */
492 #define CONFIG_FSL_ESPI  /* SPI */
493 #ifdef CONFIG_FSL_ESPI
494 #define CONFIG_SPI_FLASH
495 #define CONFIG_SPI_FLASH_SPANSION
496 #define CONFIG_CMD_SF
497 #define CONFIG_SF_DEFAULT_SPEED         10000000
498 #define CONFIG_SF_DEFAULT_MODE          SPI_MODE_0
499 #endif
500
501 #if defined(CONFIG_TSEC_ENET)
502
503 #define CONFIG_MII                      /* MII PHY management */
504 #define CONFIG_MII_DEFAULT_TSEC 1       /* Allow unregistered phys */
505 #define CONFIG_TSEC1    1
506 #define CONFIG_TSEC1_NAME       "eTSEC1"
507 #define CONFIG_TSEC2    1
508 #define CONFIG_TSEC2_NAME       "eTSEC2"
509
510 #define TSEC1_PHY_ADDR          0
511 #define TSEC2_PHY_ADDR          1
512
513 #define TSEC1_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
514 #define TSEC2_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
515
516 #define TSEC1_PHYIDX            0
517 #define TSEC2_PHYIDX            0
518
519 #define CONFIG_ETHPRIME         "eTSEC1"
520
521 #define CONFIG_PHY_GIGE         /* Include GbE speed/duplex detection */
522
523 /* TBI PHY configuration for SGMII mode */
524 #define CONFIG_TSEC_TBICR_SETTINGS ( \
525                 TBICR_PHY_RESET \
526                 | TBICR_ANEG_ENABLE \
527                 | TBICR_FULL_DUPLEX \
528                 | TBICR_SPEED1_SET \
529                 )
530
531 #endif  /* CONFIG_TSEC_ENET */
532
533 #define CONFIG_MMC
534 #ifdef CONFIG_MMC
535 #define CONFIG_CMD_MMC
536 #define CONFIG_DOS_PARTITION
537 #define CONFIG_FSL_ESDHC
538 #define CONFIG_GENERIC_MMC
539 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
540 #endif
541
542 #define CONFIG_USB_EHCI  /* USB */
543 #ifdef CONFIG_USB_EHCI
544 #define CONFIG_CMD_USB
545 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
546 #define CONFIG_USB_EHCI_FSL
547 #define CONFIG_USB_STORAGE
548 #define CONFIG_HAS_FSL_DR_USB
549 #endif
550
551 /*
552  * Environment
553  */
554 #if defined(CONFIG_RAMBOOT_SDCARD)
555 #define CONFIG_ENV_IS_IN_MMC
556 #define CONFIG_SYS_MMC_ENV_DEV          0
557 #define CONFIG_ENV_SIZE                 0x2000
558 #elif defined(CONFIG_RAMBOOT_SPIFLASH)
559 #define CONFIG_ENV_IS_IN_SPI_FLASH
560 #define CONFIG_ENV_SPI_BUS      0
561 #define CONFIG_ENV_SPI_CS       0
562 #define CONFIG_ENV_SPI_MAX_HZ   10000000
563 #define CONFIG_ENV_SPI_MODE     0
564 #define CONFIG_ENV_OFFSET       0x100000        /* 1MB */
565 #define CONFIG_ENV_SECT_SIZE    0x10000
566 #define CONFIG_ENV_SIZE         0x2000
567 #elif defined(CONFIG_NAND)
568 #define CONFIG_ENV_IS_IN_NAND
569 #define CONFIG_ENV_SIZE         CONFIG_SYS_NAND_BLOCK_SIZE
570 #define CONFIG_ENV_OFFSET       ((512 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE)
571 #define CONFIG_ENV_RANGE        (3 * CONFIG_ENV_SIZE)
572 #elif defined(CONFIG_SYS_RAMBOOT)
573 #define CONFIG_ENV_IS_NOWHERE           /* Store ENV in memory only */
574 #define CONFIG_ENV_ADDR                 (CONFIG_SYS_MONITOR_BASE - 0x1000)
575 #define CONFIG_ENV_SIZE                 0x2000
576 #else
577 #define CONFIG_ENV_IS_IN_FLASH
578 #if CONFIG_SYS_MONITOR_BASE > 0xfff80000
579 #define CONFIG_ENV_ADDR 0xfff80000
580 #else
581 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
582 #endif
583 #define CONFIG_ENV_SIZE         0x2000
584 #define CONFIG_ENV_SECT_SIZE    0x20000 /* 128K (one sector) */
585 #endif
586
587 #define CONFIG_LOADS_ECHO               /* echo on for serial download */
588 #define CONFIG_SYS_LOADS_BAUD_CHANGE    /* allow baudrate change */
589
590 /*
591  * Command line configuration.
592  */
593 #include <config_cmd_default.h>
594
595 #define CONFIG_CMD_DATE
596 #define CONFIG_CMD_DHCP
597 #define CONFIG_CMD_ELF
598 #define CONFIG_CMD_ERRATA
599 #define CONFIG_CMD_I2C
600 #define CONFIG_CMD_IRQ
601 #define CONFIG_CMD_MII
602 #define CONFIG_CMD_PING
603 #define CONFIG_CMD_SETEXPR
604 #define CONFIG_CMD_REGINFO
605
606 #if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI)
607 #define CONFIG_CMD_EXT2
608 #define CONFIG_CMD_FAT
609 #define CONFIG_DOS_PARTITION
610 #endif
611
612 /*
613  * Miscellaneous configurable options
614  */
615 #define CONFIG_SYS_LONGHELP                     /* undef to save memory */
616 #define CONFIG_CMDLINE_EDITING                  /* Command-line editing */
617 #define CONFIG_AUTO_COMPLETE                    /* add autocompletion support */
618 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
619 #define CONFIG_SYS_PROMPT       "=> "           /* Monitor Command Prompt */
620
621 #if defined(CONFIG_CMD_KGDB)
622 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size */
623 #else
624 #define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size */
625 #endif
626 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
627                                                 /* Print Buffer Size */
628 #define CONFIG_SYS_MAXARGS      16              /* max number of command args */
629 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
630 #define CONFIG_SYS_HZ           1000            /* decrementer freq:1ms ticks */
631
632
633 /*
634  * For booting Linux, the board info and command line data
635  * have to be in the first 64 MB of memory, since this is
636  * the maximum mapped by the Linux kernel during initialization.
637  */
638 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20) /* Initial Memory map for Linux */
639 #define CONFIG_SYS_BOOTM_LEN    (64 << 20) /* Increase max gunzip size */
640
641 #if defined(CONFIG_CMD_KGDB)
642 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
643 #define CONFIG_KGDB_SER_INDEX   2       /* which serial port to use */
644 #endif
645
646 /*
647  * Environment Configuration
648  */
649
650 #if defined(CONFIG_TSEC_ENET)
651 #define CONFIG_HAS_ETH0
652 #define CONFIG_HAS_ETH1
653 #endif
654
655 #define CONFIG_HOSTNAME         BSC9132qds
656 #define CONFIG_ROOTPATH         "/opt/nfsroot"
657 #define CONFIG_BOOTFILE         "uImage"
658 #define CONFIG_UBOOTPATH        "u-boot.bin"
659
660 #define CONFIG_BAUDRATE         115200
661
662 #ifdef CONFIG_SDCARD
663 #define CONFIG_DEF_HWCONFIG     "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0"
664 #else
665 #define CONFIG_DEF_HWCONFIG     "hwconfig=sim;usb1:dr_mode=host,phy_type=ulpi\0"
666 #endif
667
668 #define CONFIG_EXTRA_ENV_SETTINGS                               \
669         "netdev=eth0\0"                                         \
670         "uboot=" CONFIG_UBOOTPATH "\0"                          \
671         "loadaddr=1000000\0"                    \
672         "bootfile=uImage\0"     \
673         "consoledev=ttyS0\0"                            \
674         "ramdiskaddr=2000000\0"                 \
675         "ramdiskfile=rootfs.ext2.gz.uboot\0"            \
676         "fdtaddr=c00000\0"                              \
677         "fdtfile=bsc9132qds.dtb\0"              \
678         "bdev=sda1\0"   \
679         CONFIG_DEF_HWCONFIG\
680         "othbootargs=mem=880M ramdisk_size=600000 " \
681                 "default_hugepagesz=256m hugepagesz=256m hugepages=1 " \
682                 "isolcpus=0\0" \
683         "usbext2boot=setenv bootargs root=/dev/ram rw " \
684                 "console=$consoledev,$baudrate $othbootargs; "  \
685                 "usb start;"                    \
686                 "ext2load usb 0:4 $loadaddr $bootfile;"         \
687                 "ext2load usb 0:4 $fdtaddr $fdtfile;"   \
688                 "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;"   \
689                 "bootm $loadaddr $ramdiskaddr $fdtaddr\0"       \
690         "debug_halt_off=mw ff7e0e30 0xf0000000;"
691
692 #define CONFIG_NFSBOOTCOMMAND   \
693         "setenv bootargs root=/dev/nfs rw "     \
694         "nfsroot=$serverip:$rootpath "  \
695         "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
696         "console=$consoledev,$baudrate $othbootargs;" \
697         "tftp $loadaddr $bootfile;"     \
698         "tftp $fdtaddr $fdtfile;"       \
699         "bootm $loadaddr - $fdtaddr"
700
701 #define CONFIG_HDBOOT   \
702         "setenv bootargs root=/dev/$bdev rw rootdelay=30 "      \
703         "console=$consoledev,$baudrate $othbootargs;" \
704         "usb start;"    \
705         "ext2load usb 0:1 $loadaddr /boot/$bootfile;"   \
706         "ext2load usb 0:1 $fdtaddr /boot/$fdtfile;"     \
707         "bootm $loadaddr - $fdtaddr"
708
709 #define CONFIG_RAMBOOTCOMMAND           \
710         "setenv bootargs root=/dev/ram rw "     \
711         "console=$consoledev,$baudrate $othbootargs; "  \
712         "tftp $ramdiskaddr $ramdiskfile;"       \
713         "tftp $loadaddr $bootfile;"             \
714         "tftp $fdtaddr $fdtfile;"               \
715         "bootm $loadaddr $ramdiskaddr $fdtaddr"
716
717 #define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND
718
719 #endif  /* __CONFIG_H */