2 * Copyright 2013 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
8 * BSC9132 QDS board configuration file
14 #ifdef CONFIG_BSC9132QDS
15 #define CONFIG_BSC9132
18 #define CONFIG_MISC_INIT_R
21 #define CONFIG_RAMBOOT_SDCARD
22 #define CONFIG_SYS_RAMBOOT
23 #define CONFIG_SYS_EXTRA_ENV_RELOC
24 #define CONFIG_SYS_TEXT_BASE 0x11000000
25 #define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc
27 #define CONFIG_SYS_FSL_ERRATUM_IFC_A002769 1
28 #ifdef CONFIG_SPIFLASH
29 #define CONFIG_RAMBOOT_SPIFLASH
30 #define CONFIG_SYS_RAMBOOT
31 #define CONFIG_SYS_EXTRA_ENV_RELOC
32 #define CONFIG_SYS_TEXT_BASE 0x11000000
33 #define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc
38 #define CONFIG_SPL_INIT_MINIMAL
39 #define CONFIG_SPL_SERIAL_SUPPORT
40 #define CONFIG_SPL_NAND_SUPPORT
41 #define CONFIG_SPL_NAND_MINIMAL
42 #define CONFIG_SPL_FLUSH_IMAGE
43 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
45 #define CONFIG_SYS_TEXT_BASE 0x00201000
46 #define CONFIG_SPL_TEXT_BASE 0xFFFFE000
47 #define CONFIG_SPL_MAX_SIZE 8192
48 #define CONFIG_SPL_RELOC_TEXT_BASE 0x00100000
49 #define CONFIG_SPL_RELOC_STACK 0x00100000
50 #define CONFIG_SYS_NAND_U_BOOT_SIZE ((512 << 10) - 0x2000)
51 #define CONFIG_SYS_NAND_U_BOOT_DST (0x00200000 - CONFIG_SPL_MAX_SIZE)
52 #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000
53 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0
54 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
57 #ifndef CONFIG_SYS_TEXT_BASE
58 #define CONFIG_SYS_TEXT_BASE 0x8ff80000
61 #ifndef CONFIG_RESET_VECTOR_ADDRESS
62 #define CONFIG_RESET_VECTOR_ADDRESS 0x8ffffffc
65 #ifdef CONFIG_SPL_BUILD
66 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
68 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
71 /* High Level Configuration Options */
72 #define CONFIG_BOOKE /* BOOKE */
73 #define CONFIG_E500 /* BOOKE e500 family */
74 #define CONFIG_MPC85xx
75 #define CONFIG_FSL_IFC /* Enable IFC Support */
76 #define CONFIG_SYS_HAS_SERDES /* common SERDES init code */
78 #define CONFIG_PCI /* Enable PCI/PCIE */
79 #if defined(CONFIG_PCI)
80 #define CONFIG_PCIE1 /* PCIE controler 1 (slot 1) */
81 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
82 #define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
83 #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */
84 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
86 #define CONFIG_CMD_NET
87 #define CONFIG_CMD_PCI
89 #define CONFIG_E1000 /* E1000 pci Ethernet card*/
93 * Memory space is mapped 1-1, but I/O space must start from 0.
95 /* controller 1, Slot 1, tgtid 1, Base address a000 */
96 #define CONFIG_SYS_PCIE1_NAME "PCIe Slot"
97 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x90000000
98 #define CONFIG_SYS_PCIE1_MEM_BUS 0x90000000
99 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x90000000
100 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */
101 #define CONFIG_SYS_PCIE1_IO_VIRT 0xC0010000
102 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
103 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
104 #define CONFIG_SYS_PCIE1_IO_PHYS 0xC0010000
106 #define CONFIG_PCI_PNP /* do pci plug-and-play */
108 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
109 #define CONFIG_DOS_PARTITION
112 #define CONFIG_FSL_LAW /* Use common FSL init code */
113 #define CONFIG_ENV_OVERWRITE
114 #define CONFIG_TSEC_ENET /* ethernet */
116 #if defined(CONFIG_SYS_CLK_100_DDR_100)
117 #define CONFIG_SYS_CLK_FREQ 100000000
118 #define CONFIG_DDR_CLK_FREQ 100000000
119 #elif defined(CONFIG_SYS_CLK_100_DDR_133)
120 #define CONFIG_SYS_CLK_FREQ 100000000
121 #define CONFIG_DDR_CLK_FREQ 133000000
126 #define CONFIG_HWCONFIG
128 * These can be toggled for performance analysis, otherwise use default.
130 #define CONFIG_L2_CACHE /* toggle L2 cache */
131 #define CONFIG_BTB /* enable branch predition */
133 #define CONFIG_SYS_MEMTEST_START 0x01000000 /* memtest works on */
134 #define CONFIG_SYS_MEMTEST_END 0x01ffffff
137 #define CONFIG_FSL_DDR3
138 #define CONFIG_SYS_SPD_BUS_NUM 0
139 #define SPD_EEPROM_ADDRESS1 0x54 /* I2C access */
140 #define SPD_EEPROM_ADDRESS2 0x56 /* I2C access */
141 #define CONFIG_FSL_DDR_INTERACTIVE
143 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef
145 #define CONFIG_SYS_SDRAM_SIZE (1024)
146 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
147 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
149 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
151 /* DDR3 Controller Settings */
152 #define CONFIG_CHIP_SELECTS_PER_CTRL 1
153 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003F
154 #define CONFIG_SYS_DDR_CS0_CONFIG_1333 0x80004302
155 #define CONFIG_SYS_DDR_CS0_CONFIG_800 0x80014302
156 #define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000
157 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
158 #define CONFIG_SYS_DDR_INIT_ADDR 0x00000000
159 #define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000
160 #define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000
161 #define CONFIG_SYS_DDR1_CS0_BNDS 0x0040007F
163 #define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600
164 #define CONFIG_SYS_DDR_SR_CNTR 0x00000000
165 #define CONFIG_SYS_DDR_RCW_1 0x00000000
166 #define CONFIG_SYS_DDR_RCW_2 0x00000000
167 #define CONFIG_SYS_DDR_CONTROL_800 0x470C0000
168 #define CONFIG_SYS_DDR_CONTROL_2_800 0x04401050
169 #define CONFIG_SYS_DDR_TIMING_4_800 0x00220001
170 #define CONFIG_SYS_DDR_TIMING_5_800 0x03402400
172 #define CONFIG_SYS_DDR_CONTROL_1333 0x470C0008
173 #define CONFIG_SYS_DDR_CONTROL_2_1333 0x24401010
174 #define CONFIG_SYS_DDR_TIMING_4_1333 0x00000001
175 #define CONFIG_SYS_DDR_TIMING_5_1333 0x03401400
177 #define CONFIG_SYS_DDR_TIMING_3_800 0x00020000
178 #define CONFIG_SYS_DDR_TIMING_0_800 0x00330004
179 #define CONFIG_SYS_DDR_TIMING_1_800 0x6f6B4846
180 #define CONFIG_SYS_DDR_TIMING_2_800 0x0FA8C8CF
181 #define CONFIG_SYS_DDR_CLK_CTRL_800 0x03000000
182 #define CONFIG_SYS_DDR_MODE_1_800 0x40461520
183 #define CONFIG_SYS_DDR_MODE_2_800 0x8000c000
184 #define CONFIG_SYS_DDR_INTERVAL_800 0x0C300000
185 #define CONFIG_SYS_DDR_WRLVL_CONTROL_800 0x8655A608
187 #define CONFIG_SYS_DDR_TIMING_3_1333 0x01061000
188 #define CONFIG_SYS_DDR_TIMING_0_1333 0x00440104
189 #define CONFIG_SYS_DDR_TIMING_1_1333 0x98913A45
190 #define CONFIG_SYS_DDR_TIMING_2_1333 0x0FB8B114
191 #define CONFIG_SYS_DDR_CLK_CTRL_1333 0x02800000
192 #define CONFIG_SYS_DDR_MODE_1_1333 0x00061A50
193 #define CONFIG_SYS_DDR_MODE_2_1333 0x00100000
194 #define CONFIG_SYS_DDR_INTERVAL_1333 0x144E0513
195 #define CONFIG_SYS_DDR_WRLVL_CONTROL_1333 0x8655F607
197 /*FIXME: the following params are constant w.r.t diff freq
198 combinations. this should be removed later
200 #if CONFIG_DDR_CLK_FREQ == 100000000
201 #define CONFIG_SYS_DDR_CS0_CONFIG CONFIG_SYS_DDR_CS0_CONFIG_800
202 #define CONFIG_SYS_DDR_CONTROL CONFIG_SYS_DDR_CONTROL_800
203 #define CONFIG_SYS_DDR_CONTROL_2 CONFIG_SYS_DDR_CONTROL_2_800
204 #define CONFIG_SYS_DDR_TIMING_4 CONFIG_SYS_DDR_TIMING_4_800
205 #define CONFIG_SYS_DDR_TIMING_5 CONFIG_SYS_DDR_TIMING_5_800
206 #elif CONFIG_DDR_CLK_FREQ == 133000000
207 #define CONFIG_SYS_DDR_CS0_CONFIG CONFIG_SYS_DDR_CS0_CONFIG_1333
208 #define CONFIG_SYS_DDR_CONTROL CONFIG_SYS_DDR_CONTROL_1333
209 #define CONFIG_SYS_DDR_CONTROL_2 CONFIG_SYS_DDR_CONTROL_2_1333
210 #define CONFIG_SYS_DDR_TIMING_4 CONFIG_SYS_DDR_TIMING_4_1333
211 #define CONFIG_SYS_DDR_TIMING_5 CONFIG_SYS_DDR_TIMING_5_1333
213 #define CONFIG_SYS_DDR_CS0_CONFIG CONFIG_SYS_DDR_CS0_CONFIG_800
214 #define CONFIG_SYS_DDR_CONTROL CONFIG_SYS_DDR_CONTROL_800
215 #define CONFIG_SYS_DDR_CONTROL_2 CONFIG_SYS_DDR_CONTROL_2_800
216 #define CONFIG_SYS_DDR_TIMING_4 CONFIG_SYS_DDR_TIMING_4_800
217 #define CONFIG_SYS_DDR_TIMING_5 CONFIG_SYS_DDR_TIMING_5_800
221 /* relocated CCSRBAR */
222 #define CONFIG_SYS_CCSRBAR CONFIG_SYS_CCSRBAR_DEFAULT
223 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR_DEFAULT
225 #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR
230 /* NOR Flash on IFC */
232 #ifdef CONFIG_SPL_BUILD
233 #define CONFIG_SYS_NO_FLASH
235 #define CONFIG_SYS_FLASH_BASE 0x88000000
236 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* Max number of sector: 32M */
238 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
240 #define CONFIG_SYS_NOR_CSPR 0x88000101
241 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
242 #define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(5)
243 /* NOR Flash Timing Params */
245 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x01) \
246 | FTIM0_NOR_TEADC(0x03) \
247 | FTIM0_NOR_TAVDS(0x00) \
248 | FTIM0_NOR_TEAHC(0x0f))
249 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x1d) \
250 | FTIM1_NOR_TRAD_NOR(0x09) \
251 | FTIM1_NOR_TSEQRAD_NOR(0x09))
252 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x1) \
253 | FTIM2_NOR_TCH(0x4) \
254 | FTIM2_NOR_TWPH(0x7) \
255 | FTIM2_NOR_TWP(0x1e))
256 #define CONFIG_SYS_NOR_FTIM3 0x0
258 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
259 #define CONFIG_SYS_FLASH_QUIET_TEST
260 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
261 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
263 #undef CONFIG_SYS_FLASH_CHECKSUM
264 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
265 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
267 /* CFI for NOR Flash */
268 #define CONFIG_FLASH_CFI_DRIVER
269 #define CONFIG_SYS_FLASH_CFI
270 #define CONFIG_SYS_FLASH_EMPTY_INFO
271 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
273 /* NAND Flash on IFC */
274 #define CONFIG_SYS_NAND_BASE 0xff800000
275 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
277 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
278 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
279 | CSPR_MSEL_NAND /* MSEL = NAND */ \
281 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
283 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
284 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
285 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
286 | CSOR_NAND_RAL_2 /* RAL = 2Byes */ \
287 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \
288 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
289 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
291 /* NAND Flash Timing Params */
292 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x03) \
293 | FTIM0_NAND_TWP(0x05) \
294 | FTIM0_NAND_TWCHT(0x02) \
295 | FTIM0_NAND_TWH(0x04))
296 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x1c) \
297 | FTIM1_NAND_TWBE(0x1e) \
298 | FTIM1_NAND_TRR(0x07) \
299 | FTIM1_NAND_TRP(0x05))
300 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x08) \
301 | FTIM2_NAND_TREH(0x04) \
302 | FTIM2_NAND_TWHRE(0x11))
303 #define CONFIG_SYS_NAND_FTIM3 FTIM3_NAND_TWW(0x04)
305 #define CONFIG_SYS_NAND_DDR_LAW 11
308 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
309 #define CONFIG_SYS_MAX_NAND_DEVICE 1
310 #define CONFIG_MTD_NAND_VERIFY_WRITE
311 #define CONFIG_CMD_NAND
313 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
315 #ifndef CONFIG_SPL_BUILD
316 #define CONFIG_FSL_QIXIS
318 #ifdef CONFIG_FSL_QIXIS
319 #define CONFIG_SYS_FPGA_BASE 0xffb00000
320 #define CONFIG_SYS_I2C_FPGA_ADDR 0x66
321 #define QIXIS_BASE CONFIG_SYS_FPGA_BASE
322 #define QIXIS_LBMAP_SWITCH 9
323 #define QIXIS_LBMAP_MASK 0x07
324 #define QIXIS_LBMAP_SHIFT 0
325 #define QIXIS_LBMAP_DFLTBANK 0x00
326 #define QIXIS_LBMAP_ALTBANK 0x04
327 #define QIXIS_RST_CTL_RESET 0x83
328 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
329 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21
330 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
332 #define CONFIG_SYS_FPGA_BASE_PHYS CONFIG_SYS_FPGA_BASE
334 #define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_FPGA_BASE) \
338 #define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024)
339 #define CONFIG_SYS_CSOR2 0x0
340 /* CPLD Timing parameters for IFC CS3 */
341 #define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
342 FTIM0_GPCM_TEADC(0x0e) | \
343 FTIM0_GPCM_TEAHC(0x0e))
344 #define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \
345 FTIM1_GPCM_TRAD(0x1f))
346 #define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
347 FTIM2_GPCM_TCH(0x0) | \
348 FTIM2_GPCM_TWP(0x1f))
349 #define CONFIG_SYS_CS2_FTIM3 0x0
352 /* Set up IFC registers for boot location NOR/NAND */
353 #if defined(CONFIG_NAND)
354 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
355 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
356 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
357 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
358 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
359 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
360 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
361 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR_CSPR
362 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
363 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
364 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
365 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
366 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
367 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
369 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR
370 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
371 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
372 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
373 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
374 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
375 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
376 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR
377 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK
378 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR
379 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0
380 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1
381 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2
382 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3
385 #define CONFIG_BOARD_EARLY_INIT_F /* Call board_pre_init */
386 #define CONFIG_BOARD_EARLY_INIT_R
388 #define CONFIG_SYS_INIT_RAM_LOCK
389 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */
390 #define CONFIG_SYS_INIT_RAM_END 0x00004000 /* End of used area in RAM */
392 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END \
393 - GENERATED_GBL_DATA_SIZE)
394 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
396 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon*/
397 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc*/
400 #define CONFIG_CONS_INDEX 1
401 #undef CONFIG_SERIAL_SOFTWARE_FIFO
402 #define CONFIG_SYS_NS16550
403 #define CONFIG_SYS_NS16550_SERIAL
404 #define CONFIG_SYS_NS16550_REG_SIZE 1
405 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
406 #ifdef CONFIG_SPL_BUILD
407 #define CONFIG_NS16550_MIN_FUNCTIONS
410 #define CONFIG_SERIAL_MULTI 1 /* Enable both serial ports */
411 #define CONFIG_SYS_CONSOLE_IS_IN_ENV /* determine from environment */
413 #define CONFIG_SYS_BAUDRATE_TABLE \
414 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
416 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR + 0x4500)
417 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR + 0x4600)
418 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR + 0x4700)
419 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR + 0x4800)
421 /* Use the HUSH parser */
422 #define CONFIG_SYS_HUSH_PARSER /* hush parser */
423 #ifdef CONFIG_SYS_HUSH_PARSER
424 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
428 * Pass open firmware flat tree
430 #define CONFIG_OF_LIBFDT
431 #define CONFIG_OF_BOARD_SETUP
432 #define CONFIG_OF_STDOUT_VIA_ALIAS
434 /* new uImage format support */
436 #define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */
438 #define CONFIG_SYS_I2C
439 #define CONFIG_SYS_I2C_FSL
440 #define CONFIG_SYS_FSL_I2C_SPEED 400800 /* I2C speed and slave address*/
441 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
442 #define CONFIG_SYS_FSL_I2C2_SPEED 400800 /* I2C speed and slave address*/
443 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
444 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
445 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
448 #define CONFIG_ID_EEPROM
449 #ifdef CONFIG_ID_EEPROM
450 #define CONFIG_SYS_I2C_EEPROM_NXID
452 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
453 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
454 #define CONFIG_SYS_EEPROM_BUS_NUM 0
456 /* enable read and write access to EEPROM */
457 #define CONFIG_CMD_EEPROM
458 #define CONFIG_SYS_I2C_MULTI_EEPROMS
459 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
460 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
461 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
464 #define CONFIG_I2C_FPGA
465 #define CONFIG_SYS_I2C_FPGA_ADDR 0x66
467 #define CONFIG_RTC_DS3231
468 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
471 * SPI interface will not be available in case of NAND boot SPI CS0 will be
474 /* eSPI - Enhanced SPI */
475 #define CONFIG_FSL_ESPI /* SPI */
476 #ifdef CONFIG_FSL_ESPI
477 #define CONFIG_SPI_FLASH
478 #define CONFIG_SPI_FLASH_SPANSION
479 #define CONFIG_CMD_SF
480 #define CONFIG_SF_DEFAULT_SPEED 10000000
481 #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
484 #if defined(CONFIG_TSEC_ENET)
486 #define CONFIG_MII /* MII PHY management */
487 #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */
488 #define CONFIG_TSEC1 1
489 #define CONFIG_TSEC1_NAME "eTSEC1"
490 #define CONFIG_TSEC2 1
491 #define CONFIG_TSEC2_NAME "eTSEC2"
493 #define TSEC1_PHY_ADDR 0
494 #define TSEC2_PHY_ADDR 1
496 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
497 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
499 #define TSEC1_PHYIDX 0
500 #define TSEC2_PHYIDX 0
502 #define CONFIG_ETHPRIME "eTSEC1"
504 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
506 /* TBI PHY configuration for SGMII mode */
507 #define CONFIG_TSEC_TBICR_SETTINGS ( \
509 | TBICR_ANEG_ENABLE \
510 | TBICR_FULL_DUPLEX \
514 #endif /* CONFIG_TSEC_ENET */
518 #define CONFIG_CMD_MMC
519 #define CONFIG_DOS_PARTITION
520 #define CONFIG_FSL_ESDHC
521 #define CONFIG_GENERIC_MMC
522 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
525 #define CONFIG_USB_EHCI /* USB */
526 #ifdef CONFIG_USB_EHCI
527 #define CONFIG_CMD_USB
528 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
529 #define CONFIG_USB_EHCI_FSL
530 #define CONFIG_USB_STORAGE
531 #define CONFIG_HAS_FSL_DR_USB
537 #if defined(CONFIG_RAMBOOT_SDCARD)
538 #define CONFIG_ENV_IS_IN_MMC
539 #define CONFIG_SYS_MMC_ENV_DEV 0
540 #define CONFIG_ENV_SIZE 0x2000
541 #elif defined(CONFIG_RAMBOOT_SPIFLASH)
542 #define CONFIG_ENV_IS_IN_SPI_FLASH
543 #define CONFIG_ENV_SPI_BUS 0
544 #define CONFIG_ENV_SPI_CS 0
545 #define CONFIG_ENV_SPI_MAX_HZ 10000000
546 #define CONFIG_ENV_SPI_MODE 0
547 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
548 #define CONFIG_ENV_SECT_SIZE 0x10000
549 #define CONFIG_ENV_SIZE 0x2000
550 #elif defined(CONFIG_NAND)
551 #define CONFIG_ENV_IS_IN_NAND
552 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
553 #define CONFIG_ENV_OFFSET ((512 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE)
554 #define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE)
555 #elif defined(CONFIG_SYS_RAMBOOT)
556 #define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */
557 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
558 #define CONFIG_ENV_SIZE 0x2000
560 #define CONFIG_ENV_IS_IN_FLASH
561 #if CONFIG_SYS_MONITOR_BASE > 0xfff80000
562 #define CONFIG_ENV_ADDR 0xfff80000
564 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
566 #define CONFIG_ENV_SIZE 0x2000
567 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
570 #define CONFIG_LOADS_ECHO /* echo on for serial download */
571 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
574 * Command line configuration.
576 #include <config_cmd_default.h>
578 #define CONFIG_CMD_DATE
579 #define CONFIG_CMD_DHCP
580 #define CONFIG_CMD_ELF
581 #define CONFIG_CMD_ERRATA
582 #define CONFIG_CMD_I2C
583 #define CONFIG_CMD_IRQ
584 #define CONFIG_CMD_MII
585 #define CONFIG_CMD_PING
586 #define CONFIG_CMD_SETEXPR
587 #define CONFIG_CMD_REGINFO
589 #if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI)
590 #define CONFIG_CMD_EXT2
591 #define CONFIG_CMD_FAT
592 #define CONFIG_DOS_PARTITION
596 * Miscellaneous configurable options
598 #define CONFIG_SYS_LONGHELP /* undef to save memory */
599 #define CONFIG_CMDLINE_EDITING /* Command-line editing */
600 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */
601 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
602 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
604 #if defined(CONFIG_CMD_KGDB)
605 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
607 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
609 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
610 /* Print Buffer Size */
611 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
612 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
613 #define CONFIG_SYS_HZ 1000 /* decrementer freq:1ms ticks */
617 * For booting Linux, the board info and command line data
618 * have to be in the first 64 MB of memory, since this is
619 * the maximum mapped by the Linux kernel during initialization.
621 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux */
622 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
624 #if defined(CONFIG_CMD_KGDB)
625 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
626 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
630 * Environment Configuration
633 #if defined(CONFIG_TSEC_ENET)
634 #define CONFIG_HAS_ETH0
635 #define CONFIG_HAS_ETH1
638 #define CONFIG_HOSTNAME BSC9132qds
639 #define CONFIG_ROOTPATH "/opt/nfsroot"
640 #define CONFIG_BOOTFILE "uImage"
641 #define CONFIG_UBOOTPATH "u-boot.bin"
643 #define CONFIG_BAUDRATE 115200
646 #define CONFIG_DEF_HWCONFIG "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0"
648 #define CONFIG_DEF_HWCONFIG "hwconfig=sim;usb1:dr_mode=host,phy_type=ulpi\0"
651 #define CONFIG_EXTRA_ENV_SETTINGS \
653 "uboot=" CONFIG_UBOOTPATH "\0" \
654 "loadaddr=1000000\0" \
655 "bootfile=uImage\0" \
656 "consoledev=ttyS0\0" \
657 "ramdiskaddr=2000000\0" \
658 "ramdiskfile=rootfs.ext2.gz.uboot\0" \
660 "fdtfile=bsc9132qds.dtb\0" \
663 "othbootargs=mem=880M ramdisk_size=600000 " \
664 "default_hugepagesz=256m hugepagesz=256m hugepages=1 " \
666 "usbext2boot=setenv bootargs root=/dev/ram rw " \
667 "console=$consoledev,$baudrate $othbootargs; " \
669 "ext2load usb 0:4 $loadaddr $bootfile;" \
670 "ext2load usb 0:4 $fdtaddr $fdtfile;" \
671 "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \
672 "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \
673 "debug_halt_off=mw ff7e0e30 0xf0000000;"
675 #define CONFIG_NFSBOOTCOMMAND \
676 "setenv bootargs root=/dev/nfs rw " \
677 "nfsroot=$serverip:$rootpath " \
678 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
679 "console=$consoledev,$baudrate $othbootargs;" \
680 "tftp $loadaddr $bootfile;" \
681 "tftp $fdtaddr $fdtfile;" \
682 "bootm $loadaddr - $fdtaddr"
684 #define CONFIG_HDBOOT \
685 "setenv bootargs root=/dev/$bdev rw rootdelay=30 " \
686 "console=$consoledev,$baudrate $othbootargs;" \
688 "ext2load usb 0:1 $loadaddr /boot/$bootfile;" \
689 "ext2load usb 0:1 $fdtaddr /boot/$fdtfile;" \
690 "bootm $loadaddr - $fdtaddr"
692 #define CONFIG_RAMBOOTCOMMAND \
693 "setenv bootargs root=/dev/ram rw " \
694 "console=$consoledev,$baudrate $othbootargs; " \
695 "tftp $ramdiskaddr $ramdiskfile;" \
696 "tftp $loadaddr $bootfile;" \
697 "tftp $fdtaddr $fdtfile;" \
698 "bootm $loadaddr $ramdiskaddr $fdtaddr"
700 #define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND
702 #endif /* __CONFIG_H */