2 * Copyright 2011-2012 Freescale Semiconductor, Inc.
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 * BSC9131 RDB board configuration file
30 #ifdef CONFIG_BSC9131RDB
31 #define CONFIG_BSC9131
32 #define CONFIG_NAND_FSL_IFC
35 #ifdef CONFIG_SPIFLASH
36 #define CONFIG_RAMBOOT_SPIFLASH
37 #define CONFIG_SYS_RAMBOOT
38 #define CONFIG_SYS_EXTRA_ENV_RELOC
39 #define CONFIG_SYS_TEXT_BASE 0x11000000
40 #define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc
45 #define CONFIG_SPL_INIT_MINIMAL
46 #define CONFIG_SPL_SERIAL_SUPPORT
47 #define CONFIG_SPL_NAND_SUPPORT
48 #define CONFIG_SPL_NAND_MINIMAL
49 #define CONFIG_SPL_FLUSH_IMAGE
50 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
52 #define CONFIG_SYS_TEXT_BASE 0x00201000
53 #define CONFIG_SPL_TEXT_BASE 0xFFFFE000
54 #define CONFIG_SPL_MAX_SIZE 8192
55 #define CONFIG_SPL_RELOC_TEXT_BASE 0x00100000
56 #define CONFIG_SPL_RELOC_STACK 0x00100000
57 #define CONFIG_SYS_NAND_U_BOOT_SIZE ((512 << 10) - 0x2000)
58 #define CONFIG_SYS_NAND_U_BOOT_DST (0x00200000 - CONFIG_SPL_MAX_SIZE)
59 #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000
60 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0
61 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
64 #ifdef CONFIG_SPL_BUILD
65 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
67 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
71 /* High Level Configuration Options */
72 #define CONFIG_BOOKE /* BOOKE */
73 #define CONFIG_E500 /* BOOKE e500 family */
74 #define CONFIG_MPC85xx /* MPC8540/60/55/41/48/P1020/P2020/P1010,etc*/
75 #define CONFIG_FSL_IFC /* Enable IFC Support */
77 #define CONFIG_FSL_LAW /* Use common FSL init code */
78 #define CONFIG_TSEC_ENET
79 #define CONFIG_ENV_OVERWRITE
81 #define CONFIG_DDR_CLK_FREQ 66666666 /* DDRCLK on 9131 RDB */
82 #define CONFIG_SYS_CLK_FREQ 66666666 /* SYSCLK for 9131 RDB */
84 #define CONFIG_HWCONFIG
86 * These can be toggled for performance analysis, otherwise use default.
88 #define CONFIG_L2_CACHE /* toggle L2 cache */
89 #define CONFIG_BTB /* enable branch predition */
91 #define CONFIG_SYS_MEMTEST_START 0x01000000 /* memtest works on */
92 #define CONFIG_SYS_MEMTEST_END 0x01ffffff
95 #define CONFIG_FSL_DDR3
96 #undef CONFIG_SYS_DDR_RAW_TIMING
98 #define CONFIG_SYS_SPD_BUS_NUM 0
99 #define SPD_EEPROM_ADDRESS 0x52 /* I2C access */
101 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef
104 extern unsigned long get_sdram_size(void);
106 #define CONFIG_SYS_SDRAM_SIZE get_sdram_size() /* DDR size */
107 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
108 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
110 #define CONFIG_NUM_DDR_CONTROLLERS 1
111 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
112 #define CONFIG_CHIP_SELECTS_PER_CTRL 1
114 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f
115 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014302
116 #define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000
118 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
119 #define CONFIG_SYS_DDR_INIT_ADDR 0x00000000
120 #define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000
121 #define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000
123 #define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600
124 #define CONFIG_SYS_DDR_SR_CNTR 0x00000000
125 #define CONFIG_SYS_DDR_RCW_1 0x00000000
126 #define CONFIG_SYS_DDR_RCW_2 0x00000000
127 #define CONFIG_SYS_DDR_CONTROL 0xC70C0000 /* Type = DDR3 */
128 #define CONFIG_SYS_DDR_CONTROL_2 0x24401000
129 #define CONFIG_SYS_DDR_TIMING_4 0x00000001
130 #define CONFIG_SYS_DDR_TIMING_5 0x02401400
132 #define CONFIG_SYS_DDR_TIMING_3_800 0x00030000
133 #define CONFIG_SYS_DDR_TIMING_0_800 0x00110104
134 #define CONFIG_SYS_DDR_TIMING_1_800 0x6f6b8644
135 #define CONFIG_SYS_DDR_TIMING_2_800 0x0fa888cf
136 #define CONFIG_SYS_DDR_CLK_CTRL_800 0x03000000
137 #define CONFIG_SYS_DDR_MODE_1_800 0x00441420
138 #define CONFIG_SYS_DDR_MODE_2_800 0x8000c000
139 #define CONFIG_SYS_DDR_INTERVAL_800 0x0c300100
140 #define CONFIG_SYS_DDR_WRLVL_CONTROL_800 0x8675f608
143 * Base addresses -- Note these are effective addresses where the
144 * actual resources get mapped (not physical addresses)
146 /* relocated CCSRBAR */
147 #define CONFIG_SYS_CCSRBAR CONFIG_SYS_CCSRBAR_DEFAULT
148 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR_DEFAULT
150 #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses */
151 /* CONFIG_SYS_IMMR */
156 * 0x0000_0000 0x3FFF_FFFF DDR 1G cacheable
157 * 0x8800_0000 0x8810_0000 IFC internal SRAM 1M
158 * 0xC100_0000 0xC13F_FFFF MAPLE-2F 4M
159 * 0xC1F0_0000 0xC1F3_FFFF PA L2 SRAM Region 0 256K
160 * 0xC1F8_0000 0xC1F9_FFFF PA L2 SRAM Region 1 128K
161 * 0xFED0_0000 0xFED0_3FFF SEC Secured RAM 16K
162 * 0xFF70_0000 0xFF7F_FFFF PA CCSR 1M
163 * 0xFF80_0000 0xFFFF_FFFF Boot Page & NAND flash buffer 8M
170 #define CONFIG_SYS_NO_FLASH
172 /* NAND Flash on IFC */
173 #define CONFIG_SYS_NAND_BASE 0xff800000
174 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
176 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
177 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit*/ \
178 | CSPR_MSEL_NAND /* MSEL = NAND */ \
180 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
182 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
183 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
184 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
185 | CSOR_NAND_RAL_2 /* RAL = 2Byes */ \
186 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \
187 | CSOR_NAND_SPRZ_64 /* Spare size = 64 */ \
188 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
190 /* NAND Flash Timing Params */
191 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x08) \
192 | FTIM0_NAND_TWP(0x06) \
193 | FTIM0_NAND_TWCHT(0x03) \
194 | FTIM0_NAND_TWH(0x04))
195 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x18) \
196 | FTIM1_NAND_TWBE(0x23) \
197 | FTIM1_NAND_TRR(0x08) \
198 | FTIM1_NAND_TRP(0x05))
199 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x08) \
200 | FTIM2_NAND_TREH(0x04) \
201 | FTIM2_NAND_TWHRE(0x3f))
202 #define CONFIG_SYS_NAND_FTIM3 FTIM3_NAND_TWW(0x22)
204 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
205 #define CONFIG_SYS_MAX_NAND_DEVICE 1
206 #define CONFIG_MTD_NAND_VERIFY_WRITE
207 #define CONFIG_CMD_NAND
208 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
210 #define CONFIG_SYS_NAND_DDR_LAW 11
212 /* Set up IFC registers for boot location NAND */
213 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
214 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
215 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
216 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
217 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
218 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
219 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
221 #define CONFIG_BOARD_EARLY_INIT_F /* Call board_pre_init */
223 #define CONFIG_SYS_INIT_RAM_LOCK
224 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */
225 #define CONFIG_SYS_INIT_RAM_END 0x00004000/* End of used area in RAM */
227 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END \
228 - GENERATED_GBL_DATA_SIZE)
229 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
231 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon*/
232 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc*/
235 #define CONFIG_CONS_INDEX 1
236 #undef CONFIG_SERIAL_SOFTWARE_FIFO
237 #define CONFIG_SYS_NS16550
238 #define CONFIG_SYS_NS16550_SERIAL
239 #define CONFIG_SYS_NS16550_REG_SIZE 1
240 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
241 #ifdef CONFIG_SPL_BUILD
242 #define CONFIG_NS16550_MIN_FUNCTIONS
245 #define CONFIG_SYS_CONSOLE_IS_IN_ENV /* determine from environment */
247 #define CONFIG_SYS_BAUDRATE_TABLE \
248 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
250 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
252 /* Use the HUSH parser */
253 #define CONFIG_SYS_HUSH_PARSER
254 #ifdef CONFIG_SYS_HUSH_PARSER
255 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
259 * Pass open firmware flat tree
261 #define CONFIG_OF_LIBFDT
262 #define CONFIG_OF_BOARD_SETUP
263 #define CONFIG_OF_STDOUT_VIA_ALIAS
265 /* new uImage format support */
267 #define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */
269 #define CONFIG_FSL_I2C /* Use FSL common I2C driver */
270 #define CONFIG_HARD_I2C /* I2C with hardware support */
271 #undef CONFIG_SOFT_I2C /* I2C bit-banged */
272 #define CONFIG_I2C_MULTI_BUS
273 #define CONFIG_I2C_CMD_TREE
274 #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address*/
275 #define CONFIG_SYS_I2C_OFFSET 0x3000
278 #define CONFIG_CMD_EEPROM
279 #define CONFIG_SYS_I2C_MULTI_EEPROMS
280 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
281 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
282 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
284 #define CONFIG_CMD_I2C
287 #define CONFIG_FSL_ESPI
288 /* eSPI - Enhanced SPI */
289 #ifdef CONFIG_FSL_ESPI
290 #define CONFIG_SPI_FLASH
291 #define CONFIG_SPI_FLASH_SPANSION
292 #define CONFIG_CMD_SF
293 #define CONFIG_SF_DEFAULT_SPEED 10000000
294 #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
297 #if defined(CONFIG_TSEC_ENET)
299 #define CONFIG_MII /* MII PHY management */
300 #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */
301 #define CONFIG_TSEC1 1
302 #define CONFIG_TSEC1_NAME "eTSEC1"
303 #define CONFIG_TSEC2 1
304 #define CONFIG_TSEC2_NAME "eTSEC2"
306 #define TSEC1_PHY_ADDR 0
307 #define TSEC2_PHY_ADDR 3
309 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
310 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
312 #define TSEC1_PHYIDX 0
314 #define TSEC2_PHYIDX 0
316 #define CONFIG_ETHPRIME "eTSEC1"
318 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
320 #endif /* CONFIG_TSEC_ENET */
325 #if defined(CONFIG_RAMBOOT_SPIFLASH)
326 #define CONFIG_ENV_IS_IN_SPI_FLASH
327 #define CONFIG_ENV_SPI_BUS 0
328 #define CONFIG_ENV_SPI_CS 0
329 #define CONFIG_ENV_SPI_MAX_HZ 10000000
330 #define CONFIG_ENV_SPI_MODE 0
331 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
332 #define CONFIG_ENV_SECT_SIZE 0x10000
333 #define CONFIG_ENV_SIZE 0x2000
334 #elif defined(CONFIG_NAND)
335 #define CONFIG_ENV_IS_IN_NAND
336 #define CONFIG_SYS_EXTRA_ENV_RELOC
337 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
338 #define CONFIG_ENV_OFFSET ((512 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE)
339 #define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE)
340 #elif defined(CONFIG_SYS_RAMBOOT)
341 #define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */
342 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
343 #define CONFIG_ENV_SIZE 0x2000
346 #define CONFIG_LOADS_ECHO /* echo on for serial download */
347 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
350 * Command line configuration.
352 #include <config_cmd_default.h>
354 #define CONFIG_CMD_DHCP
355 #define CONFIG_CMD_ERRATA
356 #define CONFIG_CMD_ELF
357 #define CONFIG_CMD_EXT2
358 #define CONFIG_CMD_FAT
359 #define CONFIG_CMD_IRQ
360 #define CONFIG_CMD_MII
361 #define CONFIG_DOS_PARTITION
362 #define CONFIG_CMD_PING
363 #define CONFIG_CMD_REGINFO
364 #define CONFIG_CMD_SETEXPR
367 * Miscellaneous configurable options
369 #define CONFIG_SYS_LONGHELP /* undef to save memory */
370 #define CONFIG_CMDLINE_EDITING /* Command-line editing */
371 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */
372 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
373 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
375 #if defined(CONFIG_CMD_KGDB)
376 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
378 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
380 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
381 /* Print Buffer Size */
382 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
383 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
384 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
387 * For booting Linux, the board info and command line data
388 * have to be in the first 64 MB of memory, since this is
389 * the maximum mapped by the Linux kernel during initialization.
391 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux */
392 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
394 #if defined(CONFIG_CMD_KGDB)
395 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
396 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
399 #define CONFIG_USB_EHCI
401 #ifdef CONFIG_USB_EHCI
402 #define CONFIG_CMD_USB
403 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
404 #define CONFIG_USB_EHCI_FSL
405 #define CONFIG_USB_STORAGE
406 #define CONFIG_HAS_FSL_DR_USB
410 * Environment Configuration
413 #if defined(CONFIG_TSEC_ENET)
414 #define CONFIG_HAS_ETH0
417 #define CONFIG_HOSTNAME BSC9131rdb
418 #define CONFIG_ROOTPATH "/opt/nfsroot"
419 #define CONFIG_BOOTFILE "uImage"
420 #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server */
422 #define CONFIG_BAUDRATE 115200
424 #define CONFIG_EXTRA_ENV_SETTINGS \
426 "uboot=" CONFIG_UBOOTPATH "\0" \
427 "loadaddr=1000000\0" \
428 "bootfile=uImage\0" \
429 "consoledev=ttyS0\0" \
430 "ramdiskaddr=2000000\0" \
431 "ramdiskfile=rootfs.ext2.gz.uboot\0" \
433 "fdtfile=bsc9131rdb.dtb\0" \
435 "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0" \
436 "othbootargs=ramdisk_size=600000 \0" \
437 "usbext2boot=setenv bootargs root=/dev/ram rw " \
438 "console=$consoledev,$baudrate $othbootargs; " \
440 "ext2load usb 0:4 $loadaddr $bootfile;" \
441 "ext2load usb 0:4 $fdtaddr $fdtfile;" \
442 "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \
443 "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \
445 #define CONFIG_RAMBOOTCOMMAND \
446 "setenv bootargs root=/dev/ram rw " \
447 "console=$consoledev,$baudrate $othbootargs; " \
448 "tftp $ramdiskaddr $ramdiskfile;" \
449 "tftp $loadaddr $bootfile;" \
450 "tftp $fdtaddr $fdtfile;" \
451 "bootm $loadaddr $ramdiskaddr $fdtaddr"
453 #define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND
455 #endif /* __CONFIG_H */