Merge branch '2019-06-14-master-imports'
[platform/kernel/u-boot.git] / include / configs / BSC9131RDB.h
1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3  * Copyright 2011-2012 Freescale Semiconductor, Inc.
4  */
5
6 /*
7  * BSC9131 RDB board configuration file
8  */
9
10 #ifndef __CONFIG_H
11 #define __CONFIG_H
12
13 #define CONFIG_NAND_FSL_IFC
14
15 #ifdef CONFIG_SPIFLASH
16 #define CONFIG_RAMBOOT_SPIFLASH
17 #define CONFIG_SYS_RAMBOOT
18 #define CONFIG_RESET_VECTOR_ADDRESS     0x110bfffc
19 #endif
20
21 #ifdef CONFIG_NAND
22 #define CONFIG_SPL_INIT_MINIMAL
23 #define CONFIG_SPL_FLUSH_IMAGE
24 #define CONFIG_SPL_TARGET               "u-boot-with-spl.bin"
25
26 #define CONFIG_SPL_MAX_SIZE             8192
27 #define CONFIG_SPL_RELOC_TEXT_BASE      0x00100000
28 #define CONFIG_SPL_RELOC_STACK          0x00100000
29 #define CONFIG_SYS_NAND_U_BOOT_SIZE     ((768 << 10) - 0x2000)
30 #define CONFIG_SYS_NAND_U_BOOT_DST      (0x00200000 - CONFIG_SPL_MAX_SIZE)
31 #define CONFIG_SYS_NAND_U_BOOT_START    0x00200000
32 #define CONFIG_SYS_NAND_U_BOOT_OFFS     0
33 #endif
34
35 #ifdef CONFIG_SPL_BUILD
36 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
37 #else
38 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
39 #endif
40
41 /* High Level Configuration Options */
42
43 #define CONFIG_ENV_OVERWRITE
44
45 #define CONFIG_DDR_CLK_FREQ     66666666 /* DDRCLK on 9131 RDB */
46 #if defined(CONFIG_SYS_CLK_100)
47 #define CONFIG_SYS_CLK_FREQ    100000000 /* SYSCLK for 9131 RDB */
48 #else
49 #define CONFIG_SYS_CLK_FREQ     66666666 /* SYSCLK for 9131 RDB */
50 #endif
51
52 #define CONFIG_HWCONFIG
53 /*
54  * These can be toggled for performance analysis, otherwise use default.
55  */
56 #define CONFIG_L2_CACHE                 /* toggle L2 cache */
57 #define CONFIG_BTB                      /* enable branch predition */
58
59 #define CONFIG_SYS_MEMTEST_START        0x01000000      /* memtest works on */
60 #define CONFIG_SYS_MEMTEST_END          0x01ffffff
61
62 /* DDR Setup */
63 #undef CONFIG_SYS_DDR_RAW_TIMING
64 #undef CONFIG_DDR_SPD
65 #define CONFIG_SYS_SPD_BUS_NUM          0
66 #define SPD_EEPROM_ADDRESS              0x52 /* I2C access */
67
68 #define CONFIG_MEM_INIT_VALUE           0xDeadBeef
69
70 #ifndef __ASSEMBLY__
71 extern unsigned long get_sdram_size(void);
72 #endif
73 #define CONFIG_SYS_SDRAM_SIZE           get_sdram_size() /* DDR size */
74 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
75 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
76
77 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
78 #define CONFIG_CHIP_SELECTS_PER_CTRL    1
79
80 #define CONFIG_SYS_DDR_CS0_BNDS         0x0000003f
81 #define CONFIG_SYS_DDR_CS0_CONFIG       0x80014302
82 #define CONFIG_SYS_DDR_CS0_CONFIG_2     0x00000000
83
84 #define CONFIG_SYS_DDR_DATA_INIT        0xdeadbeef
85 #define CONFIG_SYS_DDR_INIT_ADDR        0x00000000
86 #define CONFIG_SYS_DDR_INIT_EXT_ADDR    0x00000000
87 #define CONFIG_SYS_DDR_MODE_CONTROL     0x00000000
88
89 #define CONFIG_SYS_DDR_ZQ_CONTROL       0x89080600
90 #define CONFIG_SYS_DDR_SR_CNTR          0x00000000
91 #define CONFIG_SYS_DDR_RCW_1            0x00000000
92 #define CONFIG_SYS_DDR_RCW_2            0x00000000
93 #define CONFIG_SYS_DDR_CONTROL          0xC70C0000      /* Type = DDR3  */
94 #define CONFIG_SYS_DDR_CONTROL_2        0x24401000
95 #define CONFIG_SYS_DDR_TIMING_4         0x00000001
96 #define CONFIG_SYS_DDR_TIMING_5         0x02401400
97
98 #define CONFIG_SYS_DDR_TIMING_3_800             0x00030000
99 #define CONFIG_SYS_DDR_TIMING_0_800             0x00110104
100 #define CONFIG_SYS_DDR_TIMING_1_800             0x6f6b8644
101 #define CONFIG_SYS_DDR_TIMING_2_800             0x0fa888cf
102 #define CONFIG_SYS_DDR_CLK_CTRL_800             0x03000000
103 #define CONFIG_SYS_DDR_MODE_1_800               0x00441420
104 #define CONFIG_SYS_DDR_MODE_2_800               0x8000c000
105 #define CONFIG_SYS_DDR_INTERVAL_800             0x0c300100
106 #define CONFIG_SYS_DDR_WRLVL_CONTROL_800        0x8675f608
107
108 /*
109  * Base addresses -- Note these are effective addresses where the
110  * actual resources get mapped (not physical addresses)
111  */
112 /* relocated CCSRBAR */
113 #define CONFIG_SYS_CCSRBAR      CONFIG_SYS_CCSRBAR_DEFAULT
114 #define CONFIG_SYS_CCSRBAR_PHYS_LOW     CONFIG_SYS_CCSRBAR_DEFAULT
115
116 #define CONFIG_SYS_IMMR         CONFIG_SYS_CCSRBAR      /* PQII uses */
117                                                         /* CONFIG_SYS_IMMR */
118 /* DSP CCSRBAR */
119 #define CONFIG_SYS_FSL_DSP_CCSRBAR      CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT
120 #define CONFIG_SYS_FSL_DSP_CCSRBAR_PHYS CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT
121
122 /*
123  * Memory map
124  *
125  * 0x0000_0000  0x3FFF_FFFF     DDR                     1G cacheable
126  * 0x8800_0000  0x8810_0000     IFC internal SRAM               1M
127  * 0xB000_0000  0xB0FF_FFFF     DSP core M2 memory      16M
128  * 0xC100_0000  0xC13F_FFFF     MAPLE-2F                4M
129  * 0xC1F0_0000  0xC1F3_FFFF     PA L2 SRAM Region 0     256K
130  * 0xC1F8_0000  0xC1F9_FFFF     PA L2 SRAM Region 1     128K
131  * 0xFED0_0000  0xFED0_3FFF     SEC Secured RAM         16K
132  * 0xFF60_0000  0xFF6F_FFFF     DSP CCSR                1M
133  * 0xFF70_0000  0xFF7F_FFFF     PA CCSR                 1M
134  * 0xFF80_0000  0xFFFF_FFFF     Boot Page & NAND flash buffer   8M
135  *
136  */
137
138 /*
139  * IFC Definitions
140  */
141
142 /* NAND Flash on IFC */
143 #define CONFIG_SYS_NAND_BASE            0xff800000
144 #define CONFIG_SYS_NAND_BASE_PHYS       CONFIG_SYS_NAND_BASE
145
146 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
147                                 | CSPR_PORT_SIZE_8      /* Port Size = 8 bit*/ \
148                                 | CSPR_MSEL_NAND        /* MSEL = NAND */ \
149                                 | CSPR_V)
150 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64*1024)
151
152 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
153                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
154                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
155                                 | CSOR_NAND_RAL_2       /* RAL = 2Byes */ \
156                                 | CSOR_NAND_PGS_2K      /* Page Size = 2K */ \
157                                 | CSOR_NAND_SPRZ_64     /* Spare size = 64 */ \
158                                 | CSOR_NAND_PB(64))     /*Pages Per Block = 64*/
159
160 /* NAND Flash Timing Params */
161 #define CONFIG_SYS_NAND_FTIM0           (FTIM0_NAND_TCCST(0x03)  \
162                                         | FTIM0_NAND_TWP(0x05)   \
163                                         | FTIM0_NAND_TWCHT(0x02) \
164                                         | FTIM0_NAND_TWH(0x04))
165 #define CONFIG_SYS_NAND_FTIM1           (FTIM1_NAND_TADLE(0x1C) \
166                                         | FTIM1_NAND_TWBE(0x1E) \
167                                         | FTIM1_NAND_TRR(0x07)  \
168                                         | FTIM1_NAND_TRP(0x05))
169 #define CONFIG_SYS_NAND_FTIM2           (FTIM2_NAND_TRAD(0x08)  \
170                                         | FTIM2_NAND_TREH(0x04) \
171                                         | FTIM2_NAND_TWHRE(0x11))
172 #define CONFIG_SYS_NAND_FTIM3           FTIM3_NAND_TWW(0x04)
173
174 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
175 #define CONFIG_SYS_MAX_NAND_DEVICE      1
176 #define CONFIG_SYS_NAND_BLOCK_SIZE      (128 * 1024)
177
178 #define CONFIG_SYS_NAND_DDR_LAW         11
179
180 /* Set up IFC registers for boot location NAND */
181 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
182 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
183 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
184 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
185 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
186 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
187 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
188
189 #define CONFIG_SYS_INIT_RAM_LOCK
190 #define CONFIG_SYS_INIT_RAM_ADDR        0xffd00000      /* stack in RAM */
191 #define CONFIG_SYS_INIT_RAM_SIZE        0x00004000/* End of used area in RAM */
192
193 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE \
194                                                 - GENERATED_GBL_DATA_SIZE)
195 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
196
197 #define CONFIG_SYS_MONITOR_LEN          (768 * 1024)
198 #define CONFIG_SYS_MALLOC_LEN           (1024 * 1024)   /* Reserved for malloc*/
199
200 /* Serial Port */
201 #undef  CONFIG_SERIAL_SOFTWARE_FIFO
202 #define CONFIG_SYS_NS16550_SERIAL
203 #define CONFIG_SYS_NS16550_REG_SIZE     1
204 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
205 #ifdef CONFIG_SPL_BUILD
206 #define CONFIG_NS16550_MIN_FUNCTIONS
207 #endif
208
209 #define CONFIG_SYS_BAUDRATE_TABLE       \
210         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
211
212 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
213
214 #define CONFIG_SYS_I2C
215 #define CONFIG_SYS_I2C_FSL
216 #define CONFIG_SYS_FSL_I2C_SPEED        400000
217 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
218 #define CONFIG_SYS_FSL_I2C_OFFSET       0x3000
219
220 /* I2C EEPROM */
221 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
222 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
223 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
224
225 /* eSPI - Enhanced SPI */
226
227 #if defined(CONFIG_TSEC_ENET)
228
229 #define CONFIG_MII_DEFAULT_TSEC 1       /* Allow unregistered phys */
230 #define CONFIG_TSEC1    1
231 #define CONFIG_TSEC1_NAME       "eTSEC1"
232 #define CONFIG_TSEC2    1
233 #define CONFIG_TSEC2_NAME       "eTSEC2"
234
235 #define TSEC1_PHY_ADDR          0
236 #define TSEC2_PHY_ADDR          3
237
238 #define TSEC1_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
239 #define TSEC2_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
240
241 #define TSEC1_PHYIDX            0
242
243 #define TSEC2_PHYIDX            0
244
245 #define CONFIG_ETHPRIME         "eTSEC1"
246
247 #endif  /* CONFIG_TSEC_ENET */
248
249 /*
250  * Environment
251  */
252 #if defined(CONFIG_RAMBOOT_SPIFLASH)
253 #define CONFIG_ENV_OFFSET       0x100000        /* 1MB */
254 #define CONFIG_ENV_SECT_SIZE    0x10000
255 #define CONFIG_ENV_SIZE         0x2000
256 #elif defined(CONFIG_NAND)
257 #define CONFIG_ENV_SIZE         CONFIG_SYS_NAND_BLOCK_SIZE
258 #define CONFIG_ENV_OFFSET       ((768 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE)
259 #define CONFIG_ENV_RANGE        (3 * CONFIG_ENV_SIZE)
260 #elif defined(CONFIG_SYS_RAMBOOT)
261 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - 0x1000)
262 #define CONFIG_ENV_SIZE         0x2000
263 #endif
264
265 #define CONFIG_LOADS_ECHO               /* echo on for serial download */
266 #define CONFIG_SYS_LOADS_BAUD_CHANGE            /* allow baudrate change */
267
268 /*
269  * Miscellaneous configurable options
270  */
271 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
272
273 #if defined(CONFIG_CMD_KGDB)
274 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size */
275 #else
276 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size */
277 #endif
278 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
279
280 /*
281  * For booting Linux, the board info and command line data
282  * have to be in the first 64 MB of memory, since this is
283  * the maximum mapped by the Linux kernel during initialization.
284  */
285 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20) /* Initial Memory map for Linux */
286 #define CONFIG_SYS_BOOTM_LEN    (64 << 20) /* Increase max gunzip size */
287
288 #if defined(CONFIG_CMD_KGDB)
289 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
290 #endif
291
292 #ifdef CONFIG_USB_EHCI_HCD
293 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
294 #define CONFIG_USB_EHCI_FSL
295 #define CONFIG_HAS_FSL_DR_USB
296 #endif
297
298 /*
299  * Dynamic MTD Partition support with mtdparts
300  */
301
302 /*
303  * Environment Configuration
304  */
305
306 #if defined(CONFIG_TSEC_ENET)
307 #define CONFIG_HAS_ETH0
308 #endif
309
310 #define CONFIG_HOSTNAME         "BSC9131rdb"
311 #define CONFIG_ROOTPATH         "/opt/nfsroot"
312 #define CONFIG_BOOTFILE         "uImage"
313 #define CONFIG_UBOOTPATH        "u-boot.bin" /* U-Boot image on TFTP server */
314
315 #define CONFIG_EXTRA_ENV_SETTINGS                               \
316         "netdev=eth0\0"                                         \
317         "uboot=" CONFIG_UBOOTPATH "\0"                          \
318         "loadaddr=1000000\0"                    \
319         "bootfile=uImage\0"     \
320         "consoledev=ttyS0\0"                            \
321         "ramdiskaddr=2000000\0"                 \
322         "ramdiskfile=rootfs.ext2.gz.uboot\0"            \
323         "fdtaddr=1e00000\0"                             \
324         "fdtfile=bsc9131rdb.dtb\0"              \
325         "bdev=sda1\0"   \
326         "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0"    \
327         "bootm_size=0x37000000\0"       \
328         "othbootargs=ramdisk_size=600000 " \
329         "default_hugepagesz=256m hugepagesz=256m hugepages=1\0" \
330         "usbext2boot=setenv bootargs root=/dev/ram rw " \
331         "console=$consoledev,$baudrate $othbootargs; "  \
332         "usb start;"                    \
333         "ext2load usb 0:4 $loadaddr $bootfile;"         \
334         "ext2load usb 0:4 $fdtaddr $fdtfile;"   \
335         "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;"   \
336         "bootm $loadaddr $ramdiskaddr $fdtaddr\0"       \
337
338 #define CONFIG_RAMBOOTCOMMAND           \
339         "setenv bootargs root=/dev/ram rw "     \
340         "console=$consoledev,$baudrate $othbootargs; "  \
341         "tftp $ramdiskaddr $ramdiskfile;"       \
342         "tftp $loadaddr $bootfile;"             \
343         "tftp $fdtaddr $fdtfile;"               \
344         "bootm $loadaddr $ramdiskaddr $fdtaddr"
345
346 #define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND
347
348 #endif  /* __CONFIG_H */