1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2011-2012 Freescale Semiconductor, Inc.
7 * BSC9131 RDB board configuration file
13 #define CONFIG_NAND_FSL_IFC
15 #ifdef CONFIG_SPIFLASH
16 #define CONFIG_RAMBOOT_SPIFLASH
17 #define CONFIG_SYS_RAMBOOT
18 #define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc
21 #ifdef CONFIG_MTD_RAW_NAND
22 #define CONFIG_SPL_INIT_MINIMAL
23 #define CONFIG_SPL_FLUSH_IMAGE
24 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
26 #define CONFIG_SPL_MAX_SIZE 8192
27 #define CONFIG_SPL_RELOC_TEXT_BASE 0x00100000
28 #define CONFIG_SPL_RELOC_STACK 0x00100000
29 #define CONFIG_SYS_NAND_U_BOOT_SIZE ((768 << 10) - 0x2000)
30 #define CONFIG_SYS_NAND_U_BOOT_DST (0x00200000 - CONFIG_SPL_MAX_SIZE)
31 #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000
32 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0
35 #ifdef CONFIG_SPL_BUILD
36 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
38 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
41 /* High Level Configuration Options */
43 #define CONFIG_ENV_OVERWRITE
45 #define CONFIG_DDR_CLK_FREQ 66666666 /* DDRCLK on 9131 RDB */
46 #if defined(CONFIG_SYS_CLK_100)
47 #define CONFIG_SYS_CLK_FREQ 100000000 /* SYSCLK for 9131 RDB */
49 #define CONFIG_SYS_CLK_FREQ 66666666 /* SYSCLK for 9131 RDB */
52 #define CONFIG_HWCONFIG
54 * These can be toggled for performance analysis, otherwise use default.
56 #define CONFIG_L2_CACHE /* toggle L2 cache */
57 #define CONFIG_BTB /* enable branch predition */
60 #undef CONFIG_SYS_DDR_RAW_TIMING
62 #define CONFIG_SYS_SPD_BUS_NUM 0
63 #define SPD_EEPROM_ADDRESS 0x52 /* I2C access */
65 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef
68 extern unsigned long get_sdram_size(void);
70 #define CONFIG_SYS_SDRAM_SIZE get_sdram_size() /* DDR size */
71 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
72 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
74 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
75 #define CONFIG_CHIP_SELECTS_PER_CTRL 1
77 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f
78 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014302
79 #define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000
81 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
82 #define CONFIG_SYS_DDR_INIT_ADDR 0x00000000
83 #define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000
84 #define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000
86 #define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600
87 #define CONFIG_SYS_DDR_SR_CNTR 0x00000000
88 #define CONFIG_SYS_DDR_RCW_1 0x00000000
89 #define CONFIG_SYS_DDR_RCW_2 0x00000000
90 #define CONFIG_SYS_DDR_CONTROL 0xC70C0000 /* Type = DDR3 */
91 #define CONFIG_SYS_DDR_CONTROL_2 0x24401000
92 #define CONFIG_SYS_DDR_TIMING_4 0x00000001
93 #define CONFIG_SYS_DDR_TIMING_5 0x02401400
95 #define CONFIG_SYS_DDR_TIMING_3_800 0x00030000
96 #define CONFIG_SYS_DDR_TIMING_0_800 0x00110104
97 #define CONFIG_SYS_DDR_TIMING_1_800 0x6f6b8644
98 #define CONFIG_SYS_DDR_TIMING_2_800 0x0fa888cf
99 #define CONFIG_SYS_DDR_CLK_CTRL_800 0x03000000
100 #define CONFIG_SYS_DDR_MODE_1_800 0x00441420
101 #define CONFIG_SYS_DDR_MODE_2_800 0x8000c000
102 #define CONFIG_SYS_DDR_INTERVAL_800 0x0c300100
103 #define CONFIG_SYS_DDR_WRLVL_CONTROL_800 0x8675f608
106 * Base addresses -- Note these are effective addresses where the
107 * actual resources get mapped (not physical addresses)
109 /* relocated CCSRBAR */
110 #define CONFIG_SYS_CCSRBAR CONFIG_SYS_CCSRBAR_DEFAULT
111 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR_DEFAULT
113 #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses */
114 /* CONFIG_SYS_IMMR */
116 #define CONFIG_SYS_FSL_DSP_CCSRBAR CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT
117 #define CONFIG_SYS_FSL_DSP_CCSRBAR_PHYS CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT
122 * 0x0000_0000 0x3FFF_FFFF DDR 1G cacheable
123 * 0x8800_0000 0x8810_0000 IFC internal SRAM 1M
124 * 0xB000_0000 0xB0FF_FFFF DSP core M2 memory 16M
125 * 0xC100_0000 0xC13F_FFFF MAPLE-2F 4M
126 * 0xC1F0_0000 0xC1F3_FFFF PA L2 SRAM Region 0 256K
127 * 0xC1F8_0000 0xC1F9_FFFF PA L2 SRAM Region 1 128K
128 * 0xFED0_0000 0xFED0_3FFF SEC Secured RAM 16K
129 * 0xFF60_0000 0xFF6F_FFFF DSP CCSR 1M
130 * 0xFF70_0000 0xFF7F_FFFF PA CCSR 1M
131 * 0xFF80_0000 0xFFFF_FFFF Boot Page & NAND flash buffer 8M
139 /* NAND Flash on IFC */
140 #define CONFIG_SYS_NAND_BASE 0xff800000
141 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
143 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
144 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit*/ \
145 | CSPR_MSEL_NAND /* MSEL = NAND */ \
147 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
149 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
150 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
151 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
152 | CSOR_NAND_RAL_2 /* RAL = 2Byes */ \
153 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \
154 | CSOR_NAND_SPRZ_64 /* Spare size = 64 */ \
155 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
157 /* NAND Flash Timing Params */
158 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x03) \
159 | FTIM0_NAND_TWP(0x05) \
160 | FTIM0_NAND_TWCHT(0x02) \
161 | FTIM0_NAND_TWH(0x04))
162 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x1C) \
163 | FTIM1_NAND_TWBE(0x1E) \
164 | FTIM1_NAND_TRR(0x07) \
165 | FTIM1_NAND_TRP(0x05))
166 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x08) \
167 | FTIM2_NAND_TREH(0x04) \
168 | FTIM2_NAND_TWHRE(0x11))
169 #define CONFIG_SYS_NAND_FTIM3 FTIM3_NAND_TWW(0x04)
171 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
172 #define CONFIG_SYS_MAX_NAND_DEVICE 1
173 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
175 #define CONFIG_SYS_NAND_DDR_LAW 11
177 /* Set up IFC registers for boot location NAND */
178 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
179 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
180 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
181 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
182 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
183 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
184 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
186 #define CONFIG_SYS_INIT_RAM_LOCK
187 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */
188 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000/* End of used area in RAM */
190 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE \
191 - GENERATED_GBL_DATA_SIZE)
192 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
194 #define CONFIG_SYS_MONITOR_LEN (768 * 1024)
195 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc*/
198 #undef CONFIG_SERIAL_SOFTWARE_FIFO
199 #define CONFIG_SYS_NS16550_SERIAL
200 #define CONFIG_SYS_NS16550_REG_SIZE 1
201 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
202 #ifdef CONFIG_SPL_BUILD
203 #define CONFIG_NS16550_MIN_FUNCTIONS
206 #define CONFIG_SYS_BAUDRATE_TABLE \
207 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
209 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
211 #define CONFIG_SYS_I2C
212 #define CONFIG_SYS_I2C_FSL
213 #define CONFIG_SYS_FSL_I2C_SPEED 400000
214 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
215 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
218 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
219 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
220 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
222 /* eSPI - Enhanced SPI */
224 #if defined(CONFIG_TSEC_ENET)
226 #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */
227 #define CONFIG_TSEC1 1
228 #define CONFIG_TSEC1_NAME "eTSEC1"
229 #define CONFIG_TSEC2 1
230 #define CONFIG_TSEC2_NAME "eTSEC2"
232 #define TSEC1_PHY_ADDR 0
233 #define TSEC2_PHY_ADDR 3
235 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
236 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
238 #define TSEC1_PHYIDX 0
240 #define TSEC2_PHYIDX 0
242 #define CONFIG_ETHPRIME "eTSEC1"
244 #endif /* CONFIG_TSEC_ENET */
249 #if defined(CONFIG_RAMBOOT_SPIFLASH)
250 #elif defined(CONFIG_MTD_RAW_NAND)
251 #define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE)
254 #define CONFIG_LOADS_ECHO /* echo on for serial download */
255 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
258 * Miscellaneous configurable options
260 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
262 #if defined(CONFIG_CMD_KGDB)
263 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
265 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
267 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
270 * For booting Linux, the board info and command line data
271 * have to be in the first 64 MB of memory, since this is
272 * the maximum mapped by the Linux kernel during initialization.
274 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux */
275 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
277 #if defined(CONFIG_CMD_KGDB)
278 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
281 #ifdef CONFIG_USB_EHCI_HCD
282 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
283 #define CONFIG_USB_EHCI_FSL
284 #define CONFIG_HAS_FSL_DR_USB
288 * Dynamic MTD Partition support with mtdparts
292 * Environment Configuration
295 #if defined(CONFIG_TSEC_ENET)
296 #define CONFIG_HAS_ETH0
299 #define CONFIG_HOSTNAME "BSC9131rdb"
300 #define CONFIG_ROOTPATH "/opt/nfsroot"
301 #define CONFIG_BOOTFILE "uImage"
302 #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server */
304 #define CONFIG_EXTRA_ENV_SETTINGS \
306 "uboot=" CONFIG_UBOOTPATH "\0" \
307 "loadaddr=1000000\0" \
308 "bootfile=uImage\0" \
309 "consoledev=ttyS0\0" \
310 "ramdiskaddr=2000000\0" \
311 "ramdiskfile=rootfs.ext2.gz.uboot\0" \
312 "fdtaddr=1e00000\0" \
313 "fdtfile=bsc9131rdb.dtb\0" \
315 "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0" \
316 "bootm_size=0x37000000\0" \
317 "othbootargs=ramdisk_size=600000 " \
318 "default_hugepagesz=256m hugepagesz=256m hugepages=1\0" \
319 "usbext2boot=setenv bootargs root=/dev/ram rw " \
320 "console=$consoledev,$baudrate $othbootargs; " \
322 "ext2load usb 0:4 $loadaddr $bootfile;" \
323 "ext2load usb 0:4 $fdtaddr $fdtfile;" \
324 "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \
325 "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \
327 #define CONFIG_RAMBOOTCOMMAND \
328 "setenv bootargs root=/dev/ram rw " \
329 "console=$consoledev,$baudrate $othbootargs; " \
330 "tftp $ramdiskaddr $ramdiskfile;" \
331 "tftp $loadaddr $bootfile;" \
332 "tftp $fdtaddr $fdtfile;" \
333 "bootm $loadaddr $ramdiskaddr $fdtaddr"
335 #define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND
337 #endif /* __CONFIG_H */