2 * Copyright 2011-2012 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
8 * BSC9131 RDB board configuration file
14 #define CONFIG_NAND_FSL_IFC
16 #ifdef CONFIG_SPIFLASH
17 #define CONFIG_RAMBOOT_SPIFLASH
18 #define CONFIG_SYS_RAMBOOT
19 #define CONFIG_SYS_EXTRA_ENV_RELOC
20 #define CONFIG_SYS_TEXT_BASE 0x11000000
21 #define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc
25 #define CONFIG_SPL_INIT_MINIMAL
26 #define CONFIG_SPL_NAND_BOOT
27 #define CONFIG_SPL_FLUSH_IMAGE
28 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
30 #define CONFIG_SYS_TEXT_BASE 0x00201000
31 #define CONFIG_SPL_TEXT_BASE 0xFFFFE000
32 #define CONFIG_SPL_MAX_SIZE 8192
33 #define CONFIG_SPL_RELOC_TEXT_BASE 0x00100000
34 #define CONFIG_SPL_RELOC_STACK 0x00100000
35 #define CONFIG_SYS_NAND_U_BOOT_SIZE ((768 << 10) - 0x2000)
36 #define CONFIG_SYS_NAND_U_BOOT_DST (0x00200000 - CONFIG_SPL_MAX_SIZE)
37 #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000
38 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0
39 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
42 #ifdef CONFIG_SPL_BUILD
43 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
45 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
48 /* High Level Configuration Options */
49 #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */
51 #define CONFIG_TSEC_ENET
52 #define CONFIG_ENV_OVERWRITE
54 #define CONFIG_DDR_CLK_FREQ 66666666 /* DDRCLK on 9131 RDB */
55 #if defined(CONFIG_SYS_CLK_100)
56 #define CONFIG_SYS_CLK_FREQ 100000000 /* SYSCLK for 9131 RDB */
58 #define CONFIG_SYS_CLK_FREQ 66666666 /* SYSCLK for 9131 RDB */
61 #define CONFIG_HWCONFIG
63 * These can be toggled for performance analysis, otherwise use default.
65 #define CONFIG_L2_CACHE /* toggle L2 cache */
66 #define CONFIG_BTB /* enable branch predition */
68 #define CONFIG_SYS_MEMTEST_START 0x01000000 /* memtest works on */
69 #define CONFIG_SYS_MEMTEST_END 0x01ffffff
72 #undef CONFIG_SYS_DDR_RAW_TIMING
74 #define CONFIG_SYS_SPD_BUS_NUM 0
75 #define SPD_EEPROM_ADDRESS 0x52 /* I2C access */
77 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef
80 extern unsigned long get_sdram_size(void);
82 #define CONFIG_SYS_SDRAM_SIZE get_sdram_size() /* DDR size */
83 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
84 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
86 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
87 #define CONFIG_CHIP_SELECTS_PER_CTRL 1
89 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f
90 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014302
91 #define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000
93 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
94 #define CONFIG_SYS_DDR_INIT_ADDR 0x00000000
95 #define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000
96 #define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000
98 #define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600
99 #define CONFIG_SYS_DDR_SR_CNTR 0x00000000
100 #define CONFIG_SYS_DDR_RCW_1 0x00000000
101 #define CONFIG_SYS_DDR_RCW_2 0x00000000
102 #define CONFIG_SYS_DDR_CONTROL 0xC70C0000 /* Type = DDR3 */
103 #define CONFIG_SYS_DDR_CONTROL_2 0x24401000
104 #define CONFIG_SYS_DDR_TIMING_4 0x00000001
105 #define CONFIG_SYS_DDR_TIMING_5 0x02401400
107 #define CONFIG_SYS_DDR_TIMING_3_800 0x00030000
108 #define CONFIG_SYS_DDR_TIMING_0_800 0x00110104
109 #define CONFIG_SYS_DDR_TIMING_1_800 0x6f6b8644
110 #define CONFIG_SYS_DDR_TIMING_2_800 0x0fa888cf
111 #define CONFIG_SYS_DDR_CLK_CTRL_800 0x03000000
112 #define CONFIG_SYS_DDR_MODE_1_800 0x00441420
113 #define CONFIG_SYS_DDR_MODE_2_800 0x8000c000
114 #define CONFIG_SYS_DDR_INTERVAL_800 0x0c300100
115 #define CONFIG_SYS_DDR_WRLVL_CONTROL_800 0x8675f608
118 * Base addresses -- Note these are effective addresses where the
119 * actual resources get mapped (not physical addresses)
121 /* relocated CCSRBAR */
122 #define CONFIG_SYS_CCSRBAR CONFIG_SYS_CCSRBAR_DEFAULT
123 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR_DEFAULT
125 #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses */
126 /* CONFIG_SYS_IMMR */
128 #define CONFIG_SYS_FSL_DSP_CCSRBAR CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT
129 #define CONFIG_SYS_FSL_DSP_CCSRBAR_PHYS CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT
134 * 0x0000_0000 0x3FFF_FFFF DDR 1G cacheable
135 * 0x8800_0000 0x8810_0000 IFC internal SRAM 1M
136 * 0xB000_0000 0xB0FF_FFFF DSP core M2 memory 16M
137 * 0xC100_0000 0xC13F_FFFF MAPLE-2F 4M
138 * 0xC1F0_0000 0xC1F3_FFFF PA L2 SRAM Region 0 256K
139 * 0xC1F8_0000 0xC1F9_FFFF PA L2 SRAM Region 1 128K
140 * 0xFED0_0000 0xFED0_3FFF SEC Secured RAM 16K
141 * 0xFF60_0000 0xFF6F_FFFF DSP CCSR 1M
142 * 0xFF70_0000 0xFF7F_FFFF PA CCSR 1M
143 * 0xFF80_0000 0xFFFF_FFFF Boot Page & NAND flash buffer 8M
150 #define CONFIG_SYS_NO_FLASH
152 /* NAND Flash on IFC */
153 #define CONFIG_SYS_NAND_BASE 0xff800000
154 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
156 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
157 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit*/ \
158 | CSPR_MSEL_NAND /* MSEL = NAND */ \
160 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
162 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
163 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
164 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
165 | CSOR_NAND_RAL_2 /* RAL = 2Byes */ \
166 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \
167 | CSOR_NAND_SPRZ_64 /* Spare size = 64 */ \
168 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
170 /* NAND Flash Timing Params */
171 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x03) \
172 | FTIM0_NAND_TWP(0x05) \
173 | FTIM0_NAND_TWCHT(0x02) \
174 | FTIM0_NAND_TWH(0x04))
175 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x1C) \
176 | FTIM1_NAND_TWBE(0x1E) \
177 | FTIM1_NAND_TRR(0x07) \
178 | FTIM1_NAND_TRP(0x05))
179 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x08) \
180 | FTIM2_NAND_TREH(0x04) \
181 | FTIM2_NAND_TWHRE(0x11))
182 #define CONFIG_SYS_NAND_FTIM3 FTIM3_NAND_TWW(0x04)
184 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
185 #define CONFIG_SYS_MAX_NAND_DEVICE 1
186 #define CONFIG_CMD_NAND
187 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
189 #define CONFIG_SYS_NAND_DDR_LAW 11
191 /* Set up IFC registers for boot location NAND */
192 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
193 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
194 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
195 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
196 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
197 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
198 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
200 #define CONFIG_SYS_INIT_RAM_LOCK
201 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */
202 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000/* End of used area in RAM */
204 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE \
205 - GENERATED_GBL_DATA_SIZE)
206 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
208 #define CONFIG_SYS_MONITOR_LEN (768 * 1024)
209 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc*/
212 #define CONFIG_CONS_INDEX 1
213 #undef CONFIG_SERIAL_SOFTWARE_FIFO
214 #define CONFIG_SYS_NS16550_SERIAL
215 #define CONFIG_SYS_NS16550_REG_SIZE 1
216 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
217 #ifdef CONFIG_SPL_BUILD
218 #define CONFIG_NS16550_MIN_FUNCTIONS
221 #define CONFIG_SYS_BAUDRATE_TABLE \
222 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
224 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
226 #define CONFIG_SYS_I2C
227 #define CONFIG_SYS_I2C_FSL
228 #define CONFIG_SYS_FSL_I2C_SPEED 400000
229 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
230 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
233 #define CONFIG_CMD_EEPROM
234 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
235 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
236 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
238 /* eSPI - Enhanced SPI */
239 #ifdef CONFIG_FSL_ESPI
240 #define CONFIG_SF_DEFAULT_SPEED 10000000
241 #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
244 #if defined(CONFIG_TSEC_ENET)
246 #define CONFIG_MII /* MII PHY management */
247 #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */
248 #define CONFIG_TSEC1 1
249 #define CONFIG_TSEC1_NAME "eTSEC1"
250 #define CONFIG_TSEC2 1
251 #define CONFIG_TSEC2_NAME "eTSEC2"
253 #define TSEC1_PHY_ADDR 0
254 #define TSEC2_PHY_ADDR 3
256 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
257 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
259 #define TSEC1_PHYIDX 0
261 #define TSEC2_PHYIDX 0
263 #define CONFIG_ETHPRIME "eTSEC1"
265 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
267 #endif /* CONFIG_TSEC_ENET */
272 #if defined(CONFIG_RAMBOOT_SPIFLASH)
273 #define CONFIG_ENV_IS_IN_SPI_FLASH
274 #define CONFIG_ENV_SPI_BUS 0
275 #define CONFIG_ENV_SPI_CS 0
276 #define CONFIG_ENV_SPI_MAX_HZ 10000000
277 #define CONFIG_ENV_SPI_MODE 0
278 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
279 #define CONFIG_ENV_SECT_SIZE 0x10000
280 #define CONFIG_ENV_SIZE 0x2000
281 #elif defined(CONFIG_NAND)
282 #define CONFIG_ENV_IS_IN_NAND
283 #define CONFIG_SYS_EXTRA_ENV_RELOC
284 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
285 #define CONFIG_ENV_OFFSET ((768 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE)
286 #define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE)
287 #elif defined(CONFIG_SYS_RAMBOOT)
288 #define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */
289 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
290 #define CONFIG_ENV_SIZE 0x2000
293 #define CONFIG_LOADS_ECHO /* echo on for serial download */
294 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
297 * Command line configuration.
299 #define CONFIG_CMD_ERRATA
300 #define CONFIG_CMD_IRQ
301 #define CONFIG_CMD_REGINFO
304 * Miscellaneous configurable options
306 #define CONFIG_SYS_LONGHELP /* undef to save memory */
307 #define CONFIG_CMDLINE_EDITING /* Command-line editing */
308 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */
309 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
311 #if defined(CONFIG_CMD_KGDB)
312 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
314 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
316 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
317 /* Print Buffer Size */
318 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
319 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
322 * For booting Linux, the board info and command line data
323 * have to be in the first 64 MB of memory, since this is
324 * the maximum mapped by the Linux kernel during initialization.
326 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux */
327 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
329 #if defined(CONFIG_CMD_KGDB)
330 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
333 /* Hash command with SHA acceleration supported in hardware */
334 #ifdef CONFIG_FSL_CAAM
335 #define CONFIG_CMD_HASH
336 #define CONFIG_SHA_HW_ACCEL
339 #define CONFIG_USB_EHCI
341 #ifdef CONFIG_USB_EHCI
342 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
343 #define CONFIG_USB_EHCI_FSL
344 #define CONFIG_HAS_FSL_DR_USB
348 * Dynamic MTD Partition support with mtdparts
350 #define CONFIG_MTD_DEVICE
351 #define CONFIG_MTD_PARTITIONS
352 #define CONFIG_CMD_MTDPARTS
353 #define MTDIDS_DEFAULT "nand0=ff800000.flash,"
354 #define MTDPARTS_DEFAULT "mtdparts=ff800000.flash:1m(uboot)," \
355 "8m(kernel),512k(dtb),-(fs)"
358 * Environment Configuration
361 #if defined(CONFIG_TSEC_ENET)
362 #define CONFIG_HAS_ETH0
365 #define CONFIG_HOSTNAME BSC9131rdb
366 #define CONFIG_ROOTPATH "/opt/nfsroot"
367 #define CONFIG_BOOTFILE "uImage"
368 #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server */
370 #define CONFIG_BAUDRATE 115200
372 #define CONFIG_EXTRA_ENV_SETTINGS \
374 "uboot=" CONFIG_UBOOTPATH "\0" \
375 "loadaddr=1000000\0" \
376 "bootfile=uImage\0" \
377 "consoledev=ttyS0\0" \
378 "ramdiskaddr=2000000\0" \
379 "ramdiskfile=rootfs.ext2.gz.uboot\0" \
380 "fdtaddr=1e00000\0" \
381 "fdtfile=bsc9131rdb.dtb\0" \
383 "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0" \
384 "bootm_size=0x37000000\0" \
385 "othbootargs=ramdisk_size=600000 " \
386 "default_hugepagesz=256m hugepagesz=256m hugepages=1\0" \
387 "usbext2boot=setenv bootargs root=/dev/ram rw " \
388 "console=$consoledev,$baudrate $othbootargs; " \
390 "ext2load usb 0:4 $loadaddr $bootfile;" \
391 "ext2load usb 0:4 $fdtaddr $fdtfile;" \
392 "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \
393 "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \
395 #define CONFIG_RAMBOOTCOMMAND \
396 "setenv bootargs root=/dev/ram rw " \
397 "console=$consoledev,$baudrate $othbootargs; " \
398 "tftp $ramdiskaddr $ramdiskfile;" \
399 "tftp $loadaddr $bootfile;" \
400 "tftp $fdtaddr $fdtfile;" \
401 "bootm $loadaddr $ramdiskaddr $fdtaddr"
403 #define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND
405 #endif /* __CONFIG_H */