3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 * Configuration settings for the CU824 board.
30 /* ------------------------------------------------------------------------- */
33 * board/config.h - configuration options, board specific
40 * High Level Configuration Options
44 #define CONFIG_MPC824X 1
45 #define CONFIG_MPC8245 1
48 #define CONFIG_BCM570x 1 /* Use Broadcom BCM570x Ethernet Driver */
49 #define CONFIG_TIGON3 1
51 #define CONFIG_CONS_INDEX 1
52 #define CONFIG_BAUDRATE 9600
53 #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
55 #define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */
57 #define CONFIG_BOOTCOMMAND "bootm FF820000" /* autoboot command */
58 #define CONFIG_BOOTDELAY 5
60 #define CFG_MAX_DOC_DEVICE 1 /* Only use Onboard TSOP-16MB device */
61 #define DOC_PASSIVE_PROBE 1
62 #define CFG_DOC_SUPPORT_2000 1
63 #define CFG_DOC_SUPPORT_MILLENNIUM 1
64 #define CFG_DOC_SHORT_TIMEOUT 1
65 #define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
71 #define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_DHCP | \
72 CFG_CMD_PCI | CFG_CMD_DOC | CFG_CMD_DATE)
75 #define CONFIG_PCI_PNP 1 /* PCI plug-and-play */
78 /* This must be included AFTER the definition of CONFIG_COMMANDS (if any)
80 #include <cmd_confdefs.h>
84 * Miscellaneous configurable options
86 #define CFG_LONGHELP /* undef to save memory */
87 #define CFG_PROMPT "=>" /* Monitor Command Prompt */
88 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
92 #define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16)
94 #define CFG_MAXARGS 8 /* Max number of command args */
95 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
96 #define CFG_LOAD_ADDR 0x00100000 /* Default load address */
98 /*-----------------------------------------------------------------------
99 * Start addresses for the final memory configuration
100 * (Set up by the startup code)
101 * Please note that CFG_SDRAM_BASE _must_ start at 0
103 #define CFG_SDRAM_BASE 0x00000000
105 #define CFG_FLASH_BASE0_PRELIM 0xFFF00000 /* FLASH bank on RCS#0 */
106 #define CFG_FLASH_BASE1_PRELIM 0xFF800000 /* FLASH bank on RCS#1 */
107 #define CFG_FLASH_BASE CFG_MONITOR_BASE
108 #define CFG_FLASH_BANKS { CFG_FLASH_BASE0_PRELIM , CFG_FLASH_BASE1_PRELIM }
110 /* even though FLASHP_BASE is FF800000, with 4MB is RCS0, the
111 * reset vector is actually located at FFB00100, but the 8245
114 #define CFG_RESET_ADDRESS 0xFFF00100
116 #define CFG_EUMB_ADDR 0xFC000000
118 #define CFG_MONITOR_BASE TEXT_BASE
120 #define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
121 #define CFG_MALLOC_LEN (2048 << 10) /* Reserve 2MB for malloc() */
123 #define CFG_MEMTEST_START 0x00004000 /* memtest works on */
124 #define CFG_MEMTEST_END 0x04000000 /* 0 ... 32 MB in DRAM */
126 /* Maximum amount of RAM.
128 #define CFG_MAX_RAM_SIZE 0x04000000 /* 0 .. 64 MB of (S)DRAM */
131 #if CFG_MONITOR_BASE >= CFG_FLASH_BASE
138 /*-----------------------------------------------------------------------
139 * Definitions for initial stack pointer and data area
141 #define CFG_INIT_RAM_ADDR CFG_SDRAM_BASE + CFG_MONITOR_LEN
142 #define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
143 #define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
144 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
145 #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
148 * Low Level Configuration Settings
149 * (address mappings, register initial values, etc.)
150 * You should know what you are doing if you make changes here.
151 * For the detail description refer to the MPC8240 user's manual.
154 #define CONFIG_SYS_CLK_FREQ 33000000 /* external frequency to pll */
157 #define CFG_ETH_DEV_FN 0x7800
158 #define CFG_ETH_IOBASE 0x00104000
160 /* Bit-field values for MCCR1.
162 #define CFG_ROMNAL 0xf
163 #define CFG_ROMFAL 0x1f
164 #define CFG_DBUS_SIZE 0x3
166 /* Bit-field values for MCCR2.
168 #define CFG_TSWAIT 0x5 /* Transaction Start Wait States timer */
169 #define CFG_REFINT 0x400 /* Refresh interval FIXME: was 0t430 */
171 /* Burst To Precharge. Bits of this value go to MCCR3 and MCCR4.
173 #define CFG_BSTOPRE 0 /* FIXME: was 192 */
175 /* Bit-field values for MCCR3.
177 #define CFG_REFREC 2 /* Refresh to activate interval */
179 /* Bit-field values for MCCR4.
181 #define CFG_PRETOACT 2 /* Precharge to activate interval FIXME: was 2 */
182 #define CFG_ACTTOPRE 5 /* Activate to Precharge interval FIXME: was 5 */
183 #define CFG_SDMODE_CAS_LAT 3 /* SDMODE CAS latancy */
184 #define CFG_SDMODE_WRAP 0 /* SDMODE wrap type */
185 #define CFG_SDMODE_BURSTLEN 3 /* SDMODE Burst length */
186 #define CFG_ACTORW 0xa /* FIXME was 2 */
187 #define CFG_REGISTERD_TYPE_BUFFER 1
189 #define CFG_PGMAX 0x0 /* how long the 8240 reatins the currently accessed page in memory FIXME: was 0x32*/
191 #define CFG_SDRAM_DSCD 0x20 /* SDRAM data in sample clock delay - note bottom 3 bits MUST be 0 */
193 /* Memory bank settings.
194 * Only bits 20-29 are actually used from these vales to set the
195 * start/end addresses. The upper two bits will always be 0, and the lower
196 * 20 bits will be 0x00000 for a start address, or 0xfffff for an end
197 * address. Refer to the MPC8240 book.
200 #define CFG_BANK0_START 0x00000000
201 #define CFG_BANK0_END (CFG_MAX_RAM_SIZE - 1)
202 #define CFG_BANK0_ENABLE 1
203 #define CFG_BANK1_START 0x3ff00000
204 #define CFG_BANK1_END 0x3fffffff
205 #define CFG_BANK1_ENABLE 0
206 #define CFG_BANK2_START 0x3ff00000
207 #define CFG_BANK2_END 0x3fffffff
208 #define CFG_BANK2_ENABLE 0
209 #define CFG_BANK3_START 0x3ff00000
210 #define CFG_BANK3_END 0x3fffffff
211 #define CFG_BANK3_ENABLE 0
212 #define CFG_BANK4_START 0x3ff00000
213 #define CFG_BANK4_END 0x3fffffff
214 #define CFG_BANK4_ENABLE 0
215 #define CFG_BANK5_START 0x3ff00000
216 #define CFG_BANK5_END 0x3fffffff
217 #define CFG_BANK5_ENABLE 0
218 #define CFG_BANK6_START 0x3ff00000
219 #define CFG_BANK6_END 0x3fffffff
220 #define CFG_BANK6_ENABLE 0
221 #define CFG_BANK7_START 0x3ff00000
222 #define CFG_BANK7_END 0x3fffffff
223 #define CFG_BANK7_ENABLE 0
225 #define CFG_ODCR 0xff
227 #define CONFIG_PCI 1 /* Include PCI support */
228 #undef CONFIG_PCI_PNP
230 /* PCI Memory space(s) */
231 #define PCI_MEM_SPACE1_START 0x80000000
232 #define PCI_MEM_SPACE2_START 0xfd000000
235 #include "../board/bmw/bmw.h"
237 /* BAT configuration */
238 #define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
239 #define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
241 #define CFG_IBAT1L (0x70000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
242 #define CFG_IBAT1U (0x70000000 | BATU_BL_256M | BATU_VS | BATU_VP)
244 #define CFG_IBAT2L (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
245 #define CFG_IBAT2U (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP)
247 #define CFG_IBAT3L (0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
248 #define CFG_IBAT3U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
250 #define CFG_DBAT0L CFG_IBAT0L
251 #define CFG_DBAT0U CFG_IBAT0U
252 #define CFG_DBAT1L CFG_IBAT1L
253 #define CFG_DBAT1U CFG_IBAT1U
254 #define CFG_DBAT2L CFG_IBAT2L
255 #define CFG_DBAT2U CFG_IBAT2U
256 #define CFG_DBAT3L CFG_IBAT3L
257 #define CFG_DBAT3U CFG_IBAT3U
260 * For booting Linux, the board info and command line data
261 * have to be in the first 8 MB of memory, since this is
262 * the maximum mapped by the Linux kernel during initialization.
264 #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
269 #define CFG_MAX_FLASH_BANKS 0 /* Max number of flash banks */
270 #define CFG_MAX_FLASH_SECT 64 /* Max number of sectors per flash */
272 #define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
273 #define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
276 * Warining: environment is not EMBEDDED in the U-Boot code.
277 * It's stored in flash separately.
279 #define CFG_ENV_IS_IN_NVRAM 1
280 #define CONFIG_ENV_OVERWRITE 1
281 #define CFG_NVRAM_ACCESS_ROUTINE 1
282 #define CFG_ENV_ADDR 0x7c004000 /* right at the start of NVRAM */
283 #define CFG_ENV_SIZE 0x1ff0 /* Size of the Environment - 8K */
284 #define CFG_ENV_OFFSET 0 /* starting right at the beginning */
287 * Cache Configuration
289 #define CFG_CACHELINE_SIZE 32
290 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
291 # define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
295 * Internal Definitions
299 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
300 #define BOOTFLAG_WARM 0x02 /* Software reboot */
303 #endif /* __CONFIG_H */