2 * (C) Copyright 2002 ELTEC Elektronik AG
3 * Frank Gottschling <fgottschling@eltec.de>
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 * board/config.h - configuration options, board specific
32 #define GTREGREAD(x) 0xffffffff /* needed for debug */
35 * High Level Configuration Options
39 /* these hardware addresses are pretty bogus, please change them to
43 #define CONFIG_ETHADDR 00:00:5b:ee:de:ad
45 #define CONFIG_IPADDR 192.168.0.105
46 #define CONFIG_SERVERIP 192.168.0.100
48 #define CONFIG_BAB7xx 1 /* this is an BAB740/BAB750 board */
50 #define CONFIG_BAUDRATE 9600 /* console baudrate */
52 #undef CONFIG_WATCHDOG
54 #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
56 #define CONFIG_ZERO_BOOTDELAY_CHECK
58 #undef CONFIG_BOOTARGS
59 #define CONFIG_BOOTCOMMAND \
61 "setenv bootargs root=ramfs console=ttyS00,9600 " \
62 "ip=${ipaddr}:${serverip}:${rootpath}:${gatewayip}:" \
63 "${netmask}:${hostname}:eth0:none; " \
66 #define CONFIG_LOADS_ECHO 0 /* echo off for serial download */
67 #define CFG_LOADS_BAUD_CHANGE /* allow baudrate changes */
69 #define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
72 * Command line configuration.
74 #include <config_cmd_default.h>
76 #define CONFIG_CMD_PCI
77 #define CONFIG_CMD_JFFS2
78 #define CONFIG_CMD_SCSI
79 #define CONFIG_CMD_IDE
80 #define CONFIG_CMD_DATE
81 #define CONFIG_CMD_FDC
82 #define CONFIG_CMD_ELF
86 * Miscellaneous configurable options
88 #define CFG_LONGHELP /* undef to save memory */
89 #define CFG_PROMPT "=> " /* Monitor Command Prompt */
92 * choose between COM1 and COM2 as serial console
94 #define CONFIG_CONS_INDEX 1
96 #if defined(CONFIG_CMD_KGDB)
97 #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
99 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
101 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
102 #define CFG_MAXARGS 16 /* max number of command args */
103 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
105 #define CFG_MEMTEST_START 0x00000000 /* memtest works on */
106 #define CFG_MEMTEST_END 0x04000000 /* 0 ... 64 MB in DRAM */
108 #define CFG_LOAD_ADDR 0x1000000 /* default load address */
110 #define CFG_HZ 1000 /* dec. freq: 1 ms ticks */
112 #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
115 * Low Level Configuration Settings
116 * (address mappings, register initial values, etc.)
117 * You should know what you are doing if you make changes here.
119 #define CFG_BOARD_ASM_INIT
120 #define CONFIG_MISC_INIT_R
123 * Choose the address mapping scheme for the MPC106 mem controller.
124 * Default is mapping B (CHRP), set this define to choose mapping A (PReP).
126 #define CFG_ADDRESS_MAP_A
127 #ifdef CFG_ADDRESS_MAP_A
129 #define CFG_PCI_MEMORY_BUS 0x80000000
130 #define CFG_PCI_MEMORY_PHYS 0x00000000
131 #define CFG_PCI_MEMORY_SIZE 0x80000000
133 #define CFG_PCI_MEM_BUS 0x00000000
134 #define CFG_PCI_MEM_PHYS 0xc0000000
135 #define CFG_PCI_MEM_SIZE 0x3f000000
137 #define CFG_ISA_MEM_BUS 0
138 #define CFG_ISA_MEM_PHYS 0
139 #define CFG_ISA_MEM_SIZE 0
141 #define CFG_PCI_IO_BUS 0x1000
142 #define CFG_PCI_IO_PHYS 0x81000000
143 #define CFG_PCI_IO_SIZE 0x01000000-CFG_PCI_IO_BUS
145 #define CFG_ISA_IO_BUS 0x00000000
146 #define CFG_ISA_IO_PHYS 0x80000000
147 #define CFG_ISA_IO_SIZE 0x00800000
151 #define CFG_PCI_MEMORY_BUS 0x00000000
152 #define CFG_PCI_MEMORY_PHYS 0x00000000
153 #define CFG_PCI_MEMORY_SIZE 0x40000000
155 #define CFG_PCI_MEM_BUS 0x80000000
156 #define CFG_PCI_MEM_PHYS 0x80000000
157 #define CFG_PCI_MEM_SIZE 0x7d000000
159 #define CFG_ISA_MEM_BUS 0x00000000
160 #define CFG_ISA_MEM_PHYS 0xfd000000
161 #define CFG_ISA_MEM_SIZE 0x01000000
163 #define CFG_PCI_IO_BUS 0x00800000
164 #define CFG_PCI_IO_PHYS 0xfe800000
165 #define CFG_PCI_IO_SIZE 0x00400000
167 #define CFG_ISA_IO_BUS 0x00000000
168 #define CFG_ISA_IO_PHYS 0xfe000000
169 #define CFG_ISA_IO_SIZE 0x00800000
171 #endif /*CFG_ADDRESS_MAP_A */
173 #define CFG_60X_PCI_MEM_OFFSET 0x00000000
175 /* driver defines FDC,IDE,... */
176 #define CFG_ISA_IO_BASE_ADDRESS CFG_ISA_IO_PHYS
177 #define CFG_ISA_IO CFG_ISA_IO_PHYS
178 #define CFG_60X_PCI_IO_OFFSET CFG_ISA_IO_PHYS
181 * Start addresses for the final memory configuration
182 * (Set up by the startup code)
183 * Please note that CFG_SDRAM_BASE _must_ start at 0
185 #define CFG_SDRAM_BASE 0x00000000
186 #define CFG_FLASH_BASE 0xfff00000
189 * Definitions for initial stack pointer and data area
191 #define CFG_INIT_RAM_ADDR 0x00fd0000 /* above the memtest region */
192 #define CFG_INIT_RAM_END 0x4000
193 #define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for init data */
194 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
195 #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
198 * Flash mapping/organization on the MPC10x.
200 #define FLASH_BASE0_PRELIM 0xff800000
201 #define FLASH_BASE1_PRELIM 0xffc00000
203 #define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
204 #define CFG_MAX_FLASH_SECT 67 /* max number of sectors on one chip */
206 #define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
207 #define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
213 /* No command line, one static partition */
214 #undef CONFIG_JFFS2_CMDLINE
215 #define CONFIG_JFFS2_DEV "nor"
216 #define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF
217 #define CONFIG_JFFS2_PART_OFFSET 0x00000000
219 /* mtdparts command line support
221 * Note: fake mtd_id used, no linux mtd map file
224 #define CONFIG_JFFS2_CMDLINE
225 #define MTDIDS_DEFAULT "nor0=bab7xx-0"
226 #define MTDPARTS_DEFAULT "mtdparts=bab7xx-0:-(jffs2)"
229 #define CFG_MONITOR_BASE CFG_FLASH_BASE
230 #define CFG_MONITOR_LEN 0x40000 /* Reserve 256 kB for Monitor */
231 #define CFG_MALLOC_LEN 0x20000 /* Reserve 128 kB for malloc() */
235 * Environment settings
237 #define CONFIG_ENV_OVERWRITE
238 #define CFG_ENV_IS_IN_NVRAM 1 /* use NVRAM for environment vars */
239 #define CFG_NVRAM_SIZE 0x1ff0 /* NVRAM size (8kB), we must protect the clock data (16 bytes) */
240 #define CFG_ENV_SIZE 0x400 /* Size of Environment vars (1kB) */
242 * We store the environment and an image of revision eeprom in the upper part of the NVRAM. Thus,
243 * user applications can use the remaining space for other purposes.
245 #define CFG_ENV_ADDR (CFG_NVRAM_SIZE +0x10 -0x800)
246 #define CFG_NV_SROM_COPY_ADDR (CFG_NVRAM_SIZE +0x10 -0x400)
247 #define CFG_NVRAM_ACCESS_ROUTINE /* This board needs a special routine to access the NVRAM */
248 #define CFG_SROM_SIZE 0x100 /* shadow of revision info is in nvram */
254 #define CFG_NS16550_SERIAL
255 #define CFG_NS16550_REG_SIZE 1
256 #define CFG_NS16550_CLK 1843200
257 #define CFG_NS16550_COM1 (CFG_ISA_IO + CFG_NS87308_UART1_BASE)
258 #define CFG_NS16550_COM2 (CFG_ISA_IO + CFG_NS87308_UART2_BASE)
263 #define CONFIG_PCI /* include pci support */
264 #define CONFIG_PCI_PNP /* pci plug-and-play */
265 #define CONFIG_PCI_HOST PCI_HOST_AUTO
266 #undef CONFIG_PCI_SCAN_SHOW
269 * Video console (graphic: SMI LynxEM, keyboard: i8042)
272 #define CONFIG_CFB_CONSOLE
273 #define CONFIG_VIDEO_SMI_LYNXEM
274 #define CONFIG_I8042_KBD
275 #define CONFIG_VIDEO_LOGO
276 #define CONFIG_CONSOLE_TIME
277 #define CONFIG_CONSOLE_EXTRA_INFO
278 #define CONFIG_CONSOLE_CURSOR
279 #define CFG_CONSOLE_BLINK_COUNT 30000 /* approx. 2 HZ */
285 extern unsigned int eltec_board;
286 extern unsigned int ata_reset_time;
287 extern unsigned int scsi_reset_time;
288 extern unsigned short scsi_dev_id;
289 extern unsigned int scsi_max_scsi_id;
290 extern unsigned char scsi_sym53c8xx_ccf;
294 * ATAPI Support (experimental)
297 #define CFG_IDE_MAXBUS 1 /* max. 2 IDE busses */
298 #define CFG_IDE_MAXDEVICE (CFG_IDE_MAXBUS*2) /* max. 2 drives per IDE bus */
300 #define CFG_ATA_BASE_ADDR CFG_60X_PCI_IO_OFFSET /* base address */
301 #define CFG_ATA_IDE0_OFFSET 0x1F0 /* default ide0 offste */
302 #define CFG_ATA_IDE1_OFFSET 0x170 /* default ide1 offset */
303 #define CFG_ATA_DATA_OFFSET 0 /* data reg offset */
304 #define CFG_ATA_REG_OFFSET 0 /* reg offset */
305 #define CFG_ATA_ALT_OFFSET 0x200 /* alternate register offset */
307 #define ATA_RESET_TIME (ata_reset_time)
309 #undef CONFIG_IDE_PCMCIA /* no pcmcia interface required */
310 #undef CONFIG_IDE_LED /* no led for ide supported */
313 * SCSI support (experimental) only SYM53C8xx supported
315 #define CONFIG_SCSI_SYM53C8XX
316 #define CONFIG_SCSI_DEV_ID (scsi_dev_id) /* 875 or 860 */
317 #define CFG_SCSI_SYM53C8XX_CCF (scsi_sym53c8xx_ccf) /* value for none 40 mhz clocks */
318 #define CFG_SCSI_MAX_LUN 8 /* number of supported LUNs */
319 #define CFG_SCSI_MAX_SCSI_ID (scsi_max_scsi_id) /* max SCSI ID (0-6) */
320 #define CFG_SCSI_MAX_DEVICE (15 * CFG_SCSI_MAX_LUN) /* max. Target devices */
321 #define CFG_SCSI_SPIN_UP_TIME (scsi_reset_time)
326 #define CONFIG_DOS_PARTITION
327 #define CONFIG_MAC_PARTITION
328 #define CONFIG_ISO_PARTITION
331 * Winbond Configuration
333 #define CFG_WINBOND_83C553 1 /* has a winbond bridge */
334 #define CFG_USE_WINBOND_IDE 0 /* use winbond 83c553 internal ide */
335 #define CFG_WINBOND_ISA_CFG_ADDR 0x80005800 /* pci-isa bridge config addr */
336 #define CFG_WINBOND_IDE_CFG_ADDR 0x80005900 /* ide config addr */
339 * NS87308 Configuration
341 #define CFG_NS87308 /* Nat Semi super-io cntr on ISA bus */
342 #define CFG_NS87308_BADDR_10 1
343 #define CFG_NS87308_DEVS (CFG_NS87308_UART1 | \
344 CFG_NS87308_UART2 | \
346 CFG_NS87308_MOUSE | \
350 CFG_NS87308_POWRMAN | \
351 CFG_NS87308_RTC_APC )
353 #define CFG_NS87308_PS2MOD
354 #define CFG_NS87308_GPIO_BASE 0x0220
355 #define CFG_NS87308_PWMAN_BASE 0x0460
356 #define CFG_NS87308_PMC2 0x00 /* SuperI/O clock source is 24MHz via X1 */
359 * set up the NVRAM access registers
360 * NVRAM's controlled by the configurable CS line from the 87308
362 #define CFG_NS87308_CS0_BASE 0x0076
363 #define CFG_NS87308_CS0_CONF 0x40
364 #define CFG_NS87308_CS1_BASE 0x0070
365 #define CFG_NS87308_CS1_CONF 0x1C
366 #define CFG_NS87308_CS2_BASE 0x0071
367 #define CFG_NS87308_CS2_CONF 0x1C
369 #define CONFIG_RTC_MK48T59
378 #define CFG_DBAT0L CFG_IBAT1L
379 #define CFG_DBAT0U CFG_IBAT1U
383 #define CFG_DBAT1L CFG_IBAT1L
384 #define CFG_DBAT1U CFG_IBAT1U
388 #define CFG_DBAT2L CFG_IBAT2L
389 #define CFG_DBAT2U CFG_IBAT2U
393 #define CFG_DBAT3L CFG_IBAT3L
394 #define CFG_DBAT3U CFG_IBAT3U
399 #define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_RW)
400 #define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
401 #define CFG_DBAT0L CFG_IBAT1L
402 #define CFG_DBAT0U CFG_IBAT1U
404 /* address range for flashes */
405 #define CFG_IBAT1L (CFG_FLASH_BASE | BATL_RW | BATL_CACHEINHIBIT)
406 #define CFG_IBAT1U (CFG_FLASH_BASE | BATU_BL_16M | BATU_VS | BATU_VP)
407 #define CFG_DBAT1L CFG_IBAT1L
408 #define CFG_DBAT1U CFG_IBAT1U
411 #define CFG_IBAT2L (CFG_ISA_IO | BATL_RW | BATL_CACHEINHIBIT)
412 #define CFG_IBAT2U (CFG_ISA_IO | BATU_BL_16M | BATU_VS | BATU_VP)
413 #define CFG_DBAT2L CFG_IBAT2L
414 #define CFG_DBAT2U CFG_IBAT2U
416 /* ISA memory space */
417 #define CFG_IBAT3L (CFG_ISA_MEM | BATL_RW | BATL_CACHEINHIBIT)
418 #define CFG_IBAT3U (CFG_ISA_MEM | BATU_BL_16M | BATU_VS | BATU_VP)
419 #define CFG_DBAT3L CFG_IBAT3L
420 #define CFG_DBAT3U CFG_IBAT3U
425 * Speed settings are board specific
428 extern unsigned long bab7xx_get_bus_freq (void);
429 extern unsigned long bab7xx_get_gclk_freq (void);
431 #define CFG_BUS_HZ bab7xx_get_bus_freq()
432 #define CFG_BUS_CLK CFG_BUS_HZ
433 #define CFG_CPU_CLK bab7xx_get_gclk_freq()
436 * For booting Linux, the board info and command line data
437 * have to be in the first 8 MB of memory, since this is
438 * the maximum mapped by the Linux kernel during initialization.
440 #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
443 * Cache Configuration
445 #define CFG_CACHELINE_SIZE 32 /* For all MPC74xx CPUs */
446 #if defined(CONFIG_CMD_KGDB)
447 #define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
451 * L2 Cache Configuration is board specific for BAB740/BAB750
452 * Init values read from revision srom.
455 #define L2_INIT (L2CR_L2SIZ_HM | L2CR_L2CLK_3 | L2CR_L2RAM_BURST | \
456 L2CR_L2OH_5 | L2CR_L2CTL | L2CR_L2WT)
457 #define L2_ENABLE (L2_INIT | L2CR_L2E)
459 #define CFG_L2_BAB7xx
462 * Internal Definitions
466 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
467 #define BOOTFLAG_WARM 0x02 /* Software reboot */
470 #define CONFIG_NET_MULTI /* Multi ethernet cards support */
472 #define CONFIG_TULIP_SELECT_MEDIA
474 #endif /* __CONFIG_H */