2 * Copyright 2011-2012 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
11 * B4860 QDS board configuration file
13 #ifdef CONFIG_RAMBOOT_PBL
14 #define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/freescale/b4860qds/b4_pbi.cfg
15 #define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/b4860qds/b4_rcw.cfg
17 #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
18 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
20 #define CONFIG_SPL_FLUSH_IMAGE
21 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
22 #define CONFIG_SYS_TEXT_BASE 0x00201000
23 #define CONFIG_SPL_TEXT_BASE 0xFFFD8000
24 #define CONFIG_SPL_PAD_TO 0x40000
25 #define CONFIG_SPL_MAX_SIZE 0x28000
26 #define RESET_VECTOR_OFFSET 0x27FFC
27 #define BOOT_PAGE_OFFSET 0x27000
28 #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10)
29 #define CONFIG_SYS_NAND_U_BOOT_DST 0x00200000
30 #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000
31 #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10)
32 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
33 #define CONFIG_SPL_NAND_BOOT
34 #ifdef CONFIG_SPL_BUILD
35 #define CONFIG_SPL_SKIP_RELOCATE
36 #define CONFIG_SPL_COMMON_INIT_DDR
37 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
42 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
43 /* Set 1M boot space */
44 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
45 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
46 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
47 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
50 /* High Level Configuration Options */
51 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
52 #define CONFIG_MP /* support multiple processors */
54 #ifndef CONFIG_SYS_TEXT_BASE
55 #define CONFIG_SYS_TEXT_BASE 0xeff40000
58 #ifndef CONFIG_RESET_VECTOR_ADDRESS
59 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
62 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
63 #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
64 #define CONFIG_PCIE1 /* PCIE controller 1 */
65 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
66 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
68 #ifndef CONFIG_ARCH_B4420
69 #define CONFIG_SYS_SRIO
70 #define CONFIG_SRIO1 /* SRIO port 1 */
71 #define CONFIG_SRIO2 /* SRIO port 2 */
72 #define CONFIG_SRIO_PCIE_BOOT_MASTER
75 /* I2C bus multiplexer */
76 #define I2C_MUX_PCA_ADDR 0x77
78 /* VSC Crossbar switches */
79 #define CONFIG_VSC_CROSSBAR
80 #define I2C_CH_DEFAULT 0x8
81 #define I2C_CH_VSC3316 0xc
82 #define I2C_CH_VSC3308 0xd
84 #define VSC3316_TX_ADDRESS 0x70
85 #define VSC3316_RX_ADDRESS 0x71
86 #define VSC3308_TX_ADDRESS 0x02
87 #define VSC3308_RX_ADDRESS 0x03
89 /* IDT clock synthesizers */
90 #define CONFIG_IDT8T49N222A
91 #define I2C_CH_IDT 0x9
93 #define IDT_SERDES1_ADDRESS 0x6E
94 #define IDT_SERDES2_ADDRESS 0x6C
96 /* Voltage monitor on channel 2*/
97 #define I2C_MUX_CH_VOL_MONITOR 0xa
98 #define I2C_VOL_MONITOR_ADDR 0x40
99 #define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2
100 #define I2C_VOL_MONITOR_BUS_V_OVF 0x1
101 #define I2C_VOL_MONITOR_BUS_V_SHIFT 3
103 #define CONFIG_ZM7300
104 #define I2C_MUX_CH_DPM 0xa
105 #define I2C_DPM_ADDR 0x28
107 #define CONFIG_ENV_OVERWRITE
109 #ifndef CONFIG_MTD_NOR_FLASH
111 #define CONFIG_FLASH_CFI_DRIVER
112 #define CONFIG_SYS_FLASH_CFI
113 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
116 #if defined(CONFIG_SPIFLASH)
117 #define CONFIG_SYS_EXTRA_ENV_RELOC
118 #define CONFIG_ENV_IS_IN_SPI_FLASH
119 #define CONFIG_ENV_SPI_BUS 0
120 #define CONFIG_ENV_SPI_CS 0
121 #define CONFIG_ENV_SPI_MAX_HZ 10000000
122 #define CONFIG_ENV_SPI_MODE 0
123 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */
124 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
125 #define CONFIG_ENV_SECT_SIZE 0x10000
126 #elif defined(CONFIG_SDCARD)
127 #define CONFIG_SYS_EXTRA_ENV_RELOC
128 #define CONFIG_SYS_MMC_ENV_DEV 0
129 #define CONFIG_ENV_SIZE 0x2000
130 #define CONFIG_ENV_OFFSET (512 * 1097)
131 #elif defined(CONFIG_NAND)
132 #define CONFIG_SYS_EXTRA_ENV_RELOC
133 #define CONFIG_ENV_SIZE 0x2000
134 #define CONFIG_ENV_OFFSET (10 * CONFIG_SYS_NAND_BLOCK_SIZE)
135 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
136 #define CONFIG_ENV_IS_IN_REMOTE
137 #define CONFIG_ENV_ADDR 0xffe20000
138 #define CONFIG_ENV_SIZE 0x2000
139 #elif defined(CONFIG_ENV_IS_NOWHERE)
140 #define CONFIG_ENV_SIZE 0x2000
142 #define CONFIG_ENV_IS_IN_FLASH
143 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
144 #define CONFIG_ENV_SIZE 0x2000
145 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
149 unsigned long get_board_sys_clk(void);
150 unsigned long get_board_ddr_clk(void);
152 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() /* sysclk for MPC85xx */
153 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk()
156 * These can be toggled for performance analysis, otherwise use default.
158 #define CONFIG_SYS_CACHE_STASHING
159 #define CONFIG_BTB /* toggle branch predition */
160 #define CONFIG_DDR_ECC
161 #ifdef CONFIG_DDR_ECC
162 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
163 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
166 #define CONFIG_ENABLE_36BIT_PHYS
168 #ifdef CONFIG_PHYS_64BIT
169 #define CONFIG_ADDR_MAP
170 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */
174 #define CONFIG_POST CONFIG_SYS_POST_MEMORY /* test POST memory test */
176 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
177 #define CONFIG_SYS_MEMTEST_END 0x00400000
178 #define CONFIG_SYS_ALT_MEMTEST
179 #define CONFIG_PANIC_HANG /* do not reset board on panic */
182 * Config the L3 Cache as L3 SRAM
184 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000
185 #define CONFIG_SYS_L3_SIZE 256 << 10
186 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
188 #define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024)
190 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024)
191 #define CONFIG_SPL_RELOC_MALLOC_SIZE (30 << 10)
192 #define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024)
193 #define CONFIG_SPL_RELOC_STACK_SIZE (22 << 10)
195 #ifdef CONFIG_PHYS_64BIT
196 #define CONFIG_SYS_DCSRBAR 0xf0000000
197 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
201 #define CONFIG_ID_EEPROM
202 #define CONFIG_SYS_I2C_EEPROM_NXID
203 #define CONFIG_SYS_EEPROM_BUS_NUM 0
204 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
205 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
206 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
207 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
212 #define CONFIG_VERY_BIG_RAM
213 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
214 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
216 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
217 #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
219 #define CONFIG_DDR_SPD
220 #define CONFIG_SYS_DDR_RAW_TIMING
221 #ifndef CONFIG_SPL_BUILD
222 #define CONFIG_FSL_DDR_INTERACTIVE
225 #define CONFIG_SYS_SPD_BUS_NUM 0
226 #define SPD_EEPROM_ADDRESS1 0x51
227 #define SPD_EEPROM_ADDRESS2 0x53
229 #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1
230 #define CONFIG_SYS_SDRAM_SIZE 2048 /* for fixed parameter use */
235 #define CONFIG_SYS_FLASH_BASE 0xe0000000
236 #ifdef CONFIG_PHYS_64BIT
237 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
239 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
242 #define CONFIG_SYS_NOR0_CSPR_EXT (0xf)
243 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
245 CSPR_PORT_SIZE_16 | \
248 #define CONFIG_SYS_NOR1_CSPR_EXT (0xf)
249 #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
250 CSPR_PORT_SIZE_16 | \
253 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024)
254 /* NOR Flash Timing Params */
255 #define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(4)
256 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x01) | \
257 FTIM0_NOR_TEADC(0x04) | \
258 FTIM0_NOR_TEAHC(0x20))
259 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
260 FTIM1_NOR_TRAD_NOR(0x1A) |\
261 FTIM1_NOR_TSEQRAD_NOR(0x13))
262 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x01) | \
263 FTIM2_NOR_TCH(0x0E) | \
264 FTIM2_NOR_TWPH(0x0E) | \
266 #define CONFIG_SYS_NOR_FTIM3 0x0
268 #define CONFIG_SYS_FLASH_QUIET_TEST
269 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
271 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
272 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
273 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
274 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
276 #define CONFIG_SYS_FLASH_EMPTY_INFO
277 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \
278 + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
280 #define CONFIG_FSL_QIXIS /* use common QIXIS code */
281 #define CONFIG_FSL_QIXIS_V2
282 #define QIXIS_BASE 0xffdf0000
283 #ifdef CONFIG_PHYS_64BIT
284 #define QIXIS_BASE_PHYS (0xf00000000ull | QIXIS_BASE)
286 #define QIXIS_BASE_PHYS QIXIS_BASE
288 #define QIXIS_LBMAP_SWITCH 0x01
289 #define QIXIS_LBMAP_MASK 0x0f
290 #define QIXIS_LBMAP_SHIFT 0
291 #define QIXIS_LBMAP_DFLTBANK 0x00
292 #define QIXIS_LBMAP_ALTBANK 0x02
293 #define QIXIS_RST_CTL_RESET 0x31
294 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
295 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21
296 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
298 #define CONFIG_SYS_CSPR3_EXT (0xf)
299 #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
303 #define CONFIG_SYS_AMASK3 IFC_AMASK(4 * 1024)
304 #define CONFIG_SYS_CSOR3 0x0
305 /* QIXIS Timing parameters for IFC CS3 */
306 #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
307 FTIM0_GPCM_TEADC(0x0e) | \
308 FTIM0_GPCM_TEAHC(0x0e))
309 #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \
310 FTIM1_GPCM_TRAD(0x1f))
311 #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
312 FTIM2_GPCM_TCH(0x8) | \
313 FTIM2_GPCM_TWP(0x1f))
314 #define CONFIG_SYS_CS3_FTIM3 0x0
316 /* NAND Flash on IFC */
317 #define CONFIG_NAND_FSL_IFC
318 #define CONFIG_SYS_NAND_MAX_ECCPOS 256
319 #define CONFIG_SYS_NAND_MAX_OOBFREE 2
320 #define CONFIG_SYS_NAND_BASE 0xff800000
321 #ifdef CONFIG_PHYS_64BIT
322 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE)
324 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
327 #define CONFIG_SYS_NAND_CSPR_EXT (0xf)
328 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
329 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
330 | CSPR_MSEL_NAND /* MSEL = NAND */ \
332 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024)
334 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
335 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
336 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
337 | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \
338 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \
339 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
340 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
342 #define CONFIG_SYS_NAND_ONFI_DETECTION
344 /* ONFI NAND Flash mode0 Timing Params */
345 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
346 FTIM0_NAND_TWP(0x18) | \
347 FTIM0_NAND_TWCHT(0x07) | \
348 FTIM0_NAND_TWH(0x0a))
349 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
350 FTIM1_NAND_TWBE(0x39) | \
351 FTIM1_NAND_TRR(0x0e) | \
352 FTIM1_NAND_TRP(0x18))
353 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
354 FTIM2_NAND_TREH(0x0a) | \
355 FTIM2_NAND_TWHRE(0x1e))
356 #define CONFIG_SYS_NAND_FTIM3 0x0
358 #define CONFIG_SYS_NAND_DDR_LAW 11
360 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
361 #define CONFIG_SYS_MAX_NAND_DEVICE 1
362 #define CONFIG_CMD_NAND
364 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
366 #if defined(CONFIG_NAND)
367 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
368 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
369 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
370 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
371 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
372 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
373 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
374 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
375 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR0_CSPR_EXT
376 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR0_CSPR
377 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK
378 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR
379 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0
380 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1
381 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2
382 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3
384 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
385 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
386 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
387 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
388 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
389 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
390 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
391 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
392 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT
393 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR
394 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK
395 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR
396 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0
397 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1
398 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
399 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
401 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT
402 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR
403 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
404 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
405 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
406 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
407 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
408 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
410 #ifdef CONFIG_SPL_BUILD
411 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
413 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
416 #if defined(CONFIG_RAMBOOT_PBL)
417 #define CONFIG_SYS_RAMBOOT
420 #define CONFIG_BOARD_EARLY_INIT_R
421 #define CONFIG_MISC_INIT_R
423 #define CONFIG_HWCONFIG
425 /* define to use L1 as initial stack */
426 #define CONFIG_L1_INIT_RAM
427 #define CONFIG_SYS_INIT_RAM_LOCK
428 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
429 #ifdef CONFIG_PHYS_64BIT
430 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
431 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000
432 /* The assembler doesn't like typecast */
433 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
434 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
435 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
437 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS 0xfe03c000 /* Initial L1 address */
438 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
439 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
441 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
443 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
444 GENERATED_GBL_DATA_SIZE)
445 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
447 #define CONFIG_SYS_MONITOR_LEN (768 * 1024)
448 #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)
450 /* Serial Port - controlled on board with jumper J8
454 #define CONFIG_CONS_INDEX 1
455 #define CONFIG_SYS_NS16550_SERIAL
456 #define CONFIG_SYS_NS16550_REG_SIZE 1
457 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
459 #define CONFIG_SYS_BAUDRATE_TABLE \
460 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
462 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
463 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
464 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
465 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
468 #define CONFIG_SYS_I2C
469 #define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */
470 #define CONFIG_SYS_FSL_I2C_SPEED 400000 /* I2C speed in Hz */
471 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
472 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 /* I2C speed in Hz */
473 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
474 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000
475 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x119000
481 #define CONFIG_RTC_DS3231 1
482 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
487 #ifdef CONFIG_SYS_SRIO
489 #define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000
490 #ifdef CONFIG_PHYS_64BIT
491 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull
493 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xa0000000
495 #define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */
499 #define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000
500 #ifdef CONFIG_PHYS_64BIT
501 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull
503 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xb0000000
505 #define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */
510 * for slave u-boot IMAGE instored in master memory space,
511 * PHYS must be aligned based on the SIZE
513 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
514 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
515 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */
516 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
518 * for slave UCODE and ENV instored in master memory space,
519 * PHYS must be aligned based on the SIZE
521 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
522 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
523 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */
525 /* slave core release by master*/
526 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
527 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
530 * SRIO_PCIE_BOOT - SLAVE
532 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
533 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
534 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
535 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
539 * eSPI - Enhanced SPI
541 #define CONFIG_SF_DEFAULT_SPEED 10000000
542 #define CONFIG_SF_DEFAULT_MODE 0
547 #ifdef CONFIG_PHYS_64BIT
548 #define CONFIG_SYS_MAPLE_MEM_PHYS 0xFA0000000ull
550 #define CONFIG_SYS_MAPLE_MEM_PHYS 0xA0000000
555 * Memory space is mapped 1-1, but I/O space must start from 0.
558 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
559 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
560 #ifdef CONFIG_PHYS_64BIT
561 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
562 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
564 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
565 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000
567 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
568 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
569 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
570 #ifdef CONFIG_PHYS_64BIT
571 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
573 #define CONFIG_SYS_PCIE1_IO_PHYS 0xf8000000
575 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
578 #ifndef CONFIG_NOBQFMAN
579 #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */
580 #define CONFIG_SYS_BMAN_NUM_PORTALS 25
581 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
582 #ifdef CONFIG_PHYS_64BIT
583 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
585 #define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE
587 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000
588 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
589 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
590 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
591 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
592 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
593 CONFIG_SYS_BMAN_CENA_SIZE)
594 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
595 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
596 #define CONFIG_SYS_QMAN_NUM_PORTALS 25
597 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000
598 #ifdef CONFIG_PHYS_64BIT
599 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull
601 #define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE
603 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000
604 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
605 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
606 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE
607 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
608 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
609 CONFIG_SYS_QMAN_CENA_SIZE)
610 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
611 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
613 #define CONFIG_SYS_DPAA_FMAN
615 #define CONFIG_SYS_DPAA_RMAN
617 /* Default address of microcode for the Linux Fman driver */
618 #if defined(CONFIG_SPIFLASH)
620 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
621 * env, so we got 0x110000.
623 #define CONFIG_SYS_QE_FW_IN_SPIFLASH
624 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000
625 #elif defined(CONFIG_SDCARD)
627 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
628 * about 545KB (1089 blocks), Env is stored after the image, and the env size is
629 * 0x2000 (16 blocks), 8 + 1089 + 16 = 1113, enlarge it to 1130.
631 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC
632 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 1130)
633 #elif defined(CONFIG_NAND)
634 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND
635 #define CONFIG_SYS_FMAN_FW_ADDR (13 * CONFIG_SYS_NAND_BLOCK_SIZE)
636 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
638 * Slave has no ucode locally, it can fetch this from remote. When implementing
639 * in two corenet boards, slave's ucode could be stored in master's memory
640 * space, the address can be mapped from slave TLB->slave LAW->
641 * slave SRIO or PCIE outbound window->master inbound window->
642 * master LAW->the ucode address in master's memory space.
644 #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE
645 #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000
647 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
648 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
650 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
651 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
652 #endif /* CONFIG_NOBQFMAN */
654 #ifdef CONFIG_SYS_DPAA_FMAN
655 #define CONFIG_FMAN_ENET
656 #define CONFIG_PHYLIB_10G
657 #define CONFIG_PHY_VITESSE
658 #define CONFIG_PHY_TERANETICS
659 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C
660 #define SGMII_CARD_PORT2_PHY_ADDR 0x10
661 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E
662 #define SGMII_CARD_PORT4_PHY_ADDR 0x11
666 #define CONFIG_PCI_INDIRECT_BRIDGE
668 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
669 #endif /* CONFIG_PCI */
671 #ifdef CONFIG_FMAN_ENET
672 #define CONFIG_SYS_FM1_ONBOARD_PHY1_ADDR 0x10
673 #define CONFIG_SYS_FM1_ONBOARD_PHY2_ADDR 0x11
675 /*B4860 QDS AMC2PEX-2S default PHY_ADDR */
676 #define CONFIG_SYS_FM1_10GEC1_PHY_ADDR 0x7 /*SLOT 1*/
677 #define CONFIG_SYS_FM1_10GEC2_PHY_ADDR 0x6 /*SLOT 2*/
679 #define CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR 0x1c
680 #define CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR 0x1d
681 #define CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR 0x1e
682 #define CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR 0x1f
684 #define CONFIG_MII /* MII PHY management */
685 #define CONFIG_ETHPRIME "FM1@DTSEC1"
686 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
689 #define CONFIG_SYS_FSL_B4860QDS_XFI_ERR
694 #define CONFIG_LOADS_ECHO /* echo on for serial download */
695 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
698 * Command line configuration.
700 #define CONFIG_CMD_REGINFO
703 #define CONFIG_CMD_PCI
709 #define CONFIG_HAS_FSL_DR_USB
711 #ifdef CONFIG_HAS_FSL_DR_USB
712 #ifdef CONFIG_USB_EHCI_HCD
713 #define CONFIG_USB_EHCI_FSL
714 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
719 * Miscellaneous configurable options
721 #define CONFIG_SYS_LONGHELP /* undef to save memory */
722 #define CONFIG_CMDLINE_EDITING /* Command-line editing */
723 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */
724 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
725 #ifdef CONFIG_CMD_KGDB
726 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
728 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
730 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
731 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
732 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
735 * For booting Linux, the board info and command line data
736 * have to be in the first 64 MB of memory, since this is
737 * the maximum mapped by the Linux kernel during initialization.
739 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/
740 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
742 #ifdef CONFIG_CMD_KGDB
743 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
747 * Environment Configuration
749 #define CONFIG_ROOTPATH "/opt/nfsroot"
750 #define CONFIG_BOOTFILE "uImage"
751 #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/
753 /* default location for tftp and bootm */
754 #define CONFIG_LOADADDR 1000000
756 #define __USB_PHY_TYPE ulpi
758 #ifdef CONFIG_ARCH_B4860
759 #define HWCONFIG "hwconfig=fsl_ddr:ctlr_intlv=null," \
760 "bank_intlv=cs0_cs1;" \
763 #define HWCONFIG "hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=cs0_cs1;"
766 #define CONFIG_EXTRA_ENV_SETTINGS \
768 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
770 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
771 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
772 "tftpflash=tftpboot $loadaddr $uboot && " \
773 "protect off $ubootaddr +$filesize && " \
774 "erase $ubootaddr +$filesize && " \
775 "cp.b $loadaddr $ubootaddr $filesize && " \
776 "protect on $ubootaddr +$filesize && " \
777 "cmp.b $loadaddr $ubootaddr $filesize\0" \
778 "consoledev=ttyS0\0" \
779 "ramdiskaddr=2000000\0" \
780 "ramdiskfile=b4860qds/ramdisk.uboot\0" \
781 "fdtaddr=1e00000\0" \
782 "fdtfile=b4860qds/b4860qds.dtb\0" \
785 /* For emulation this causes u-boot to jump to the start of the proof point
786 app code automatically */
787 #define CONFIG_PROOF_POINTS \
788 "setenv bootargs root=/dev/$bdev rw " \
789 "console=$consoledev,$baudrate $othbootargs;" \
790 "cpu 1 release 0x29000000 - - -;" \
791 "cpu 2 release 0x29000000 - - -;" \
792 "cpu 3 release 0x29000000 - - -;" \
793 "cpu 4 release 0x29000000 - - -;" \
794 "cpu 5 release 0x29000000 - - -;" \
795 "cpu 6 release 0x29000000 - - -;" \
796 "cpu 7 release 0x29000000 - - -;" \
799 #define CONFIG_HVBOOT \
800 "setenv bootargs config-addr=0x60000000; " \
801 "bootm 0x01000000 - 0x00f00000"
804 "setenv bootargs root=/dev/$bdev rw " \
805 "console=$consoledev,$baudrate $othbootargs;" \
806 "cpu 1 release 0x01000000 - - -;" \
807 "cpu 2 release 0x01000000 - - -;" \
808 "cpu 3 release 0x01000000 - - -;" \
809 "cpu 4 release 0x01000000 - - -;" \
810 "cpu 5 release 0x01000000 - - -;" \
811 "cpu 6 release 0x01000000 - - -;" \
812 "cpu 7 release 0x01000000 - - -;" \
815 #define CONFIG_LINUX \
816 "setenv bootargs root=/dev/ram rw " \
817 "console=$consoledev,$baudrate $othbootargs;" \
818 "setenv ramdiskaddr 0x02000000;" \
819 "setenv fdtaddr 0x01e00000;" \
820 "setenv loadaddr 0x1000000;" \
821 "bootm $loadaddr $ramdiskaddr $fdtaddr"
823 #define CONFIG_HDBOOT \
824 "setenv bootargs root=/dev/$bdev rw " \
825 "console=$consoledev,$baudrate $othbootargs;" \
826 "tftp $loadaddr $bootfile;" \
827 "tftp $fdtaddr $fdtfile;" \
828 "bootm $loadaddr - $fdtaddr"
830 #define CONFIG_NFSBOOTCOMMAND \
831 "setenv bootargs root=/dev/nfs rw " \
832 "nfsroot=$serverip:$rootpath " \
833 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
834 "console=$consoledev,$baudrate $othbootargs;" \
835 "tftp $loadaddr $bootfile;" \
836 "tftp $fdtaddr $fdtfile;" \
837 "bootm $loadaddr - $fdtaddr"
839 #define CONFIG_RAMBOOTCOMMAND \
840 "setenv bootargs root=/dev/ram rw " \
841 "console=$consoledev,$baudrate $othbootargs;" \
842 "tftp $ramdiskaddr $ramdiskfile;" \
843 "tftp $loadaddr $bootfile;" \
844 "tftp $fdtaddr $fdtfile;" \
845 "bootm $loadaddr $ramdiskaddr $fdtaddr"
847 #define CONFIG_BOOTCOMMAND CONFIG_LINUX
849 #include <asm/fsl_secure_boot.h>
851 #endif /* __CONFIG_H */