fe04a1f72a9aa54339c80f467ce0e748b969c244
[platform/kernel/u-boot.git] / include / configs / B4860QDS.h
1 /*
2  * Copyright 2011-2012 Freescale Semiconductor, Inc.
3  *
4  * SPDX-License-Identifier:     GPL-2.0+
5  */
6
7 #ifndef __CONFIG_H
8 #define __CONFIG_H
9
10 /*
11  * B4860 QDS board configuration file
12  */
13 #ifdef CONFIG_RAMBOOT_PBL
14 #define CONFIG_SYS_FSL_PBL_PBI  $(SRCTREE)/board/freescale/b4860qds/b4_pbi.cfg
15 #define CONFIG_SYS_FSL_PBL_RCW  $(SRCTREE)/board/freescale/b4860qds/b4_rcw.cfg
16 #ifndef CONFIG_NAND
17 #define CONFIG_RAMBOOT_TEXT_BASE        CONFIG_SYS_TEXT_BASE
18 #define CONFIG_RESET_VECTOR_ADDRESS     0xfffffffc
19 #else
20 #define CONFIG_SPL_FLUSH_IMAGE
21 #define CONFIG_SPL_TARGET               "u-boot-with-spl.bin"
22 #define CONFIG_SYS_TEXT_BASE            0x00201000
23 #define CONFIG_SPL_TEXT_BASE            0xFFFD8000
24 #define CONFIG_SPL_PAD_TO               0x40000
25 #define CONFIG_SPL_MAX_SIZE             0x28000
26 #define RESET_VECTOR_OFFSET             0x27FFC
27 #define BOOT_PAGE_OFFSET                0x27000
28 #define CONFIG_SYS_NAND_U_BOOT_SIZE     (768 << 10)
29 #define CONFIG_SYS_NAND_U_BOOT_DST      0x00200000
30 #define CONFIG_SYS_NAND_U_BOOT_START    0x00200000
31 #define CONFIG_SYS_NAND_U_BOOT_OFFS     (256 << 10)
32 #define CONFIG_SYS_LDSCRIPT     "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
33 #define CONFIG_SPL_NAND_BOOT
34 #ifdef CONFIG_SPL_BUILD
35 #define CONFIG_SPL_SKIP_RELOCATE
36 #define CONFIG_SPL_COMMON_INIT_DDR
37 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
38 #endif
39 #endif
40 #endif
41
42 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
43 /* Set 1M boot space */
44 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
45 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
46                 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
47 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
48 #endif
49
50 /* High Level Configuration Options */
51 #define CONFIG_SYS_BOOK3E_HV            /* Category E.HV supported */
52 #define CONFIG_MP                       /* support multiple processors */
53
54 #ifndef CONFIG_SYS_TEXT_BASE
55 #define CONFIG_SYS_TEXT_BASE    0xeff40000
56 #endif
57
58 #ifndef CONFIG_RESET_VECTOR_ADDRESS
59 #define CONFIG_RESET_VECTOR_ADDRESS     0xeffffffc
60 #endif
61
62 #define CONFIG_SYS_FSL_CPC              /* Corenet Platform Cache */
63 #define CONFIG_SYS_NUM_CPC              CONFIG_SYS_NUM_DDR_CTLRS
64 #define CONFIG_PCIE1                    /* PCIE controller 1 */
65 #define CONFIG_FSL_PCI_INIT             /* Use common FSL init code */
66 #define CONFIG_SYS_PCI_64BIT            /* enable 64-bit PCI resources */
67
68 #ifndef CONFIG_ARCH_B4420
69 #define CONFIG_SYS_SRIO
70 #define CONFIG_SRIO1                    /* SRIO port 1 */
71 #define CONFIG_SRIO2                    /* SRIO port 2 */
72 #define CONFIG_SRIO_PCIE_BOOT_MASTER
73 #endif
74
75 /* I2C bus multiplexer */
76 #define I2C_MUX_PCA_ADDR                0x77
77
78 /* VSC Crossbar switches */
79 #define CONFIG_VSC_CROSSBAR
80 #define I2C_CH_DEFAULT                  0x8
81 #define I2C_CH_VSC3316                  0xc
82 #define I2C_CH_VSC3308                  0xd
83
84 #define VSC3316_TX_ADDRESS              0x70
85 #define VSC3316_RX_ADDRESS              0x71
86 #define VSC3308_TX_ADDRESS              0x02
87 #define VSC3308_RX_ADDRESS              0x03
88
89 /* IDT clock synthesizers */
90 #define CONFIG_IDT8T49N222A
91 #define I2C_CH_IDT                     0x9
92
93 #define IDT_SERDES1_ADDRESS            0x6E
94 #define IDT_SERDES2_ADDRESS            0x6C
95
96 /* Voltage monitor on channel 2*/
97 #define I2C_MUX_CH_VOL_MONITOR          0xa
98 #define I2C_VOL_MONITOR_ADDR            0x40
99 #define I2C_VOL_MONITOR_BUS_V_OFFSET    0x2
100 #define I2C_VOL_MONITOR_BUS_V_OVF       0x1
101 #define I2C_VOL_MONITOR_BUS_V_SHIFT     3
102
103 #define CONFIG_ZM7300
104 #define I2C_MUX_CH_DPM                  0xa
105 #define I2C_DPM_ADDR                    0x28
106
107 #define CONFIG_ENV_OVERWRITE
108
109 #ifndef CONFIG_MTD_NOR_FLASH
110 #else
111 #define CONFIG_FLASH_CFI_DRIVER
112 #define CONFIG_SYS_FLASH_CFI
113 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
114 #endif
115
116 #if defined(CONFIG_SPIFLASH)
117 #define CONFIG_SYS_EXTRA_ENV_RELOC
118 #define CONFIG_ENV_SPI_BUS              0
119 #define CONFIG_ENV_SPI_CS               0
120 #define CONFIG_ENV_SPI_MAX_HZ           10000000
121 #define CONFIG_ENV_SPI_MODE             0
122 #define CONFIG_ENV_SIZE                 0x2000          /* 8KB */
123 #define CONFIG_ENV_OFFSET               0x100000        /* 1MB */
124 #define CONFIG_ENV_SECT_SIZE            0x10000
125 #elif defined(CONFIG_SDCARD)
126 #define CONFIG_SYS_EXTRA_ENV_RELOC
127 #define CONFIG_SYS_MMC_ENV_DEV          0
128 #define CONFIG_ENV_SIZE                 0x2000
129 #define CONFIG_ENV_OFFSET               (512 * 1097)
130 #elif defined(CONFIG_NAND)
131 #define CONFIG_SYS_EXTRA_ENV_RELOC
132 #define CONFIG_ENV_SIZE                 0x2000
133 #define CONFIG_ENV_OFFSET               (10 * CONFIG_SYS_NAND_BLOCK_SIZE)
134 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
135 #define CONFIG_ENV_ADDR         0xffe20000
136 #define CONFIG_ENV_SIZE         0x2000
137 #elif defined(CONFIG_ENV_IS_NOWHERE)
138 #define CONFIG_ENV_SIZE         0x2000
139 #else
140 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
141 #define CONFIG_ENV_SIZE         0x2000
142 #define CONFIG_ENV_SECT_SIZE    0x20000 /* 128K (one sector) */
143 #endif
144
145 #ifndef __ASSEMBLY__
146 unsigned long get_board_sys_clk(void);
147 unsigned long get_board_ddr_clk(void);
148 #endif
149 #define CONFIG_SYS_CLK_FREQ     get_board_sys_clk() /* sysclk for MPC85xx */
150 #define CONFIG_DDR_CLK_FREQ     get_board_ddr_clk()
151
152 /*
153  * These can be toggled for performance analysis, otherwise use default.
154  */
155 #define CONFIG_SYS_CACHE_STASHING
156 #define CONFIG_BTB                      /* toggle branch predition */
157 #define CONFIG_DDR_ECC
158 #ifdef CONFIG_DDR_ECC
159 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
160 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
161 #endif
162
163 #define CONFIG_ENABLE_36BIT_PHYS
164
165 #ifdef CONFIG_PHYS_64BIT
166 #define CONFIG_ADDR_MAP
167 #define CONFIG_SYS_NUM_ADDR_MAP         64      /* number of TLB1 entries */
168 #endif
169
170 #if 0
171 #define CONFIG_POST CONFIG_SYS_POST_MEMORY      /* test POST memory test */
172 #endif
173 #define CONFIG_SYS_MEMTEST_START        0x00200000      /* memtest works on */
174 #define CONFIG_SYS_MEMTEST_END          0x00400000
175 #define CONFIG_SYS_ALT_MEMTEST
176 #define CONFIG_PANIC_HANG       /* do not reset board on panic */
177
178 /*
179  *  Config the L3 Cache as L3 SRAM
180  */
181 #define CONFIG_SYS_INIT_L3_ADDR         0xFFFC0000
182 #define CONFIG_SYS_L3_SIZE              256 << 10
183 #define CONFIG_SPL_GD_ADDR              (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
184 #ifdef CONFIG_NAND
185 #define CONFIG_ENV_ADDR                 (CONFIG_SPL_GD_ADDR + 4 * 1024)
186 #endif
187 #define CONFIG_SPL_RELOC_MALLOC_ADDR    (CONFIG_SPL_GD_ADDR + 12 * 1024)
188 #define CONFIG_SPL_RELOC_MALLOC_SIZE    (30 << 10)
189 #define CONFIG_SPL_RELOC_STACK          (CONFIG_SPL_GD_ADDR + 64 * 1024)
190 #define CONFIG_SPL_RELOC_STACK_SIZE     (22 << 10)
191
192 #ifdef CONFIG_PHYS_64BIT
193 #define CONFIG_SYS_DCSRBAR              0xf0000000
194 #define CONFIG_SYS_DCSRBAR_PHYS         0xf00000000ull
195 #endif
196
197 /* EEPROM */
198 #define CONFIG_ID_EEPROM
199 #define CONFIG_SYS_I2C_EEPROM_NXID
200 #define CONFIG_SYS_EEPROM_BUS_NUM       0
201 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x57
202 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  1
203 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
204 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
205
206 /*
207  * DDR Setup
208  */
209 #define CONFIG_VERY_BIG_RAM
210 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
211 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
212
213 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
214 #define CONFIG_CHIP_SELECTS_PER_CTRL    (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
215
216 #define CONFIG_DDR_SPD
217 #define CONFIG_SYS_DDR_RAW_TIMING
218 #ifndef CONFIG_SPL_BUILD
219 #define CONFIG_FSL_DDR_INTERACTIVE
220 #endif
221
222 #define CONFIG_SYS_SPD_BUS_NUM  0
223 #define SPD_EEPROM_ADDRESS1     0x51
224 #define SPD_EEPROM_ADDRESS2     0x53
225
226 #define SPD_EEPROM_ADDRESS      SPD_EEPROM_ADDRESS1
227 #define CONFIG_SYS_SDRAM_SIZE   2048    /* for fixed parameter use */
228
229 /*
230  * IFC Definitions
231  */
232 #define CONFIG_SYS_FLASH_BASE   0xe0000000
233 #ifdef CONFIG_PHYS_64BIT
234 #define CONFIG_SYS_FLASH_BASE_PHYS      (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
235 #else
236 #define CONFIG_SYS_FLASH_BASE_PHYS      CONFIG_SYS_FLASH_BASE
237 #endif
238
239 #define CONFIG_SYS_NOR0_CSPR_EXT        (0xf)
240 #define CONFIG_SYS_NOR0_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
241                                 + 0x8000000) | \
242                                 CSPR_PORT_SIZE_16 | \
243                                 CSPR_MSEL_NOR | \
244                                 CSPR_V)
245 #define CONFIG_SYS_NOR1_CSPR_EXT        (0xf)
246 #define CONFIG_SYS_NOR1_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
247                                 CSPR_PORT_SIZE_16 | \
248                                 CSPR_MSEL_NOR | \
249                                 CSPR_V)
250 #define CONFIG_SYS_NOR_AMASK    IFC_AMASK(128 * 1024 * 1024)
251 /* NOR Flash Timing Params */
252 #define CONFIG_SYS_NOR_CSOR     CSOR_NOR_ADM_SHIFT(4)
253 #define CONFIG_SYS_NOR_FTIM0    (FTIM0_NOR_TACSE(0x01) | \
254                                 FTIM0_NOR_TEADC(0x04) | \
255                                 FTIM0_NOR_TEAHC(0x20))
256 #define CONFIG_SYS_NOR_FTIM1    (FTIM1_NOR_TACO(0x35) | \
257                                 FTIM1_NOR_TRAD_NOR(0x1A) |\
258                                 FTIM1_NOR_TSEQRAD_NOR(0x13))
259 #define CONFIG_SYS_NOR_FTIM2    (FTIM2_NOR_TCS(0x01) | \
260                                 FTIM2_NOR_TCH(0x0E) | \
261                                 FTIM2_NOR_TWPH(0x0E) | \
262                                 FTIM2_NOR_TWP(0x1c))
263 #define CONFIG_SYS_NOR_FTIM3    0x0
264
265 #define CONFIG_SYS_FLASH_QUIET_TEST
266 #define CONFIG_FLASH_SHOW_PROGRESS      45 /* count down from 45/5: 9..1 */
267
268 #define CONFIG_SYS_MAX_FLASH_BANKS      2       /* number of banks */
269 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /* sectors per device */
270 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
271 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
272
273 #define CONFIG_SYS_FLASH_EMPTY_INFO
274 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS \
275                                         + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
276
277 #define CONFIG_FSL_QIXIS        /* use common QIXIS code */
278 #define CONFIG_FSL_QIXIS_V2
279 #define QIXIS_BASE              0xffdf0000
280 #ifdef CONFIG_PHYS_64BIT
281 #define QIXIS_BASE_PHYS         (0xf00000000ull | QIXIS_BASE)
282 #else
283 #define QIXIS_BASE_PHYS         QIXIS_BASE
284 #endif
285 #define QIXIS_LBMAP_SWITCH              0x01
286 #define QIXIS_LBMAP_MASK                0x0f
287 #define QIXIS_LBMAP_SHIFT               0
288 #define QIXIS_LBMAP_DFLTBANK            0x00
289 #define QIXIS_LBMAP_ALTBANK             0x02
290 #define QIXIS_RST_CTL_RESET             0x31
291 #define QIXIS_RCFG_CTL_RECONFIG_IDLE    0x20
292 #define QIXIS_RCFG_CTL_RECONFIG_START   0x21
293 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE   0x08
294
295 #define CONFIG_SYS_CSPR3_EXT    (0xf)
296 #define CONFIG_SYS_CSPR3        (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
297                                 | CSPR_PORT_SIZE_8 \
298                                 | CSPR_MSEL_GPCM \
299                                 | CSPR_V)
300 #define CONFIG_SYS_AMASK3       IFC_AMASK(4 * 1024)
301 #define CONFIG_SYS_CSOR3        0x0
302 /* QIXIS Timing parameters for IFC CS3 */
303 #define CONFIG_SYS_CS3_FTIM0            (FTIM0_GPCM_TACSE(0x0e) | \
304                                         FTIM0_GPCM_TEADC(0x0e) | \
305                                         FTIM0_GPCM_TEAHC(0x0e))
306 #define CONFIG_SYS_CS3_FTIM1            (FTIM1_GPCM_TACO(0x0e) | \
307                                         FTIM1_GPCM_TRAD(0x1f))
308 #define CONFIG_SYS_CS3_FTIM2            (FTIM2_GPCM_TCS(0x0e) | \
309                                         FTIM2_GPCM_TCH(0x8) | \
310                                         FTIM2_GPCM_TWP(0x1f))
311 #define CONFIG_SYS_CS3_FTIM3            0x0
312
313 /* NAND Flash on IFC */
314 #define CONFIG_NAND_FSL_IFC
315 #define CONFIG_SYS_NAND_MAX_ECCPOS      256
316 #define CONFIG_SYS_NAND_MAX_OOBFREE     2
317 #define CONFIG_SYS_NAND_BASE            0xff800000
318 #ifdef CONFIG_PHYS_64BIT
319 #define CONFIG_SYS_NAND_BASE_PHYS       (0xf00000000ull | CONFIG_SYS_NAND_BASE)
320 #else
321 #define CONFIG_SYS_NAND_BASE_PHYS       CONFIG_SYS_NAND_BASE
322 #endif
323
324 #define CONFIG_SYS_NAND_CSPR_EXT        (0xf)
325 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
326                                 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
327                                 | CSPR_MSEL_NAND        /* MSEL = NAND */ \
328                                 | CSPR_V)
329 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64 * 1024)
330
331 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
332                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
333                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
334                                 | CSOR_NAND_RAL_3       /* RAL = 2Byes */ \
335                                 | CSOR_NAND_PGS_2K      /* Page Size = 2K */ \
336                                 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
337                                 | CSOR_NAND_PB(64))     /*Pages Per Block = 64*/
338
339 #define CONFIG_SYS_NAND_ONFI_DETECTION
340
341 /* ONFI NAND Flash mode0 Timing Params */
342 #define CONFIG_SYS_NAND_FTIM0           (FTIM0_NAND_TCCST(0x07) | \
343                                         FTIM0_NAND_TWP(0x18)   | \
344                                         FTIM0_NAND_TWCHT(0x07) | \
345                                         FTIM0_NAND_TWH(0x0a))
346 #define CONFIG_SYS_NAND_FTIM1           (FTIM1_NAND_TADLE(0x32) | \
347                                         FTIM1_NAND_TWBE(0x39)  | \
348                                         FTIM1_NAND_TRR(0x0e)   | \
349                                         FTIM1_NAND_TRP(0x18))
350 #define CONFIG_SYS_NAND_FTIM2           (FTIM2_NAND_TRAD(0x0f) | \
351                                         FTIM2_NAND_TREH(0x0a) | \
352                                         FTIM2_NAND_TWHRE(0x1e))
353 #define CONFIG_SYS_NAND_FTIM3           0x0
354
355 #define CONFIG_SYS_NAND_DDR_LAW         11
356
357 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
358 #define CONFIG_SYS_MAX_NAND_DEVICE      1
359
360 #define CONFIG_SYS_NAND_BLOCK_SIZE      (128 * 1024)
361
362 #if defined(CONFIG_NAND)
363 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NAND_CSPR_EXT
364 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
365 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
366 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
367 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
368 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
369 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
370 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
371 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NOR0_CSPR_EXT
372 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NOR0_CSPR
373 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NOR_AMASK
374 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NOR_CSOR
375 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NOR_FTIM0
376 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NOR_FTIM1
377 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NOR_FTIM2
378 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NOR_FTIM3
379 #else
380 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR0_CSPR_EXT
381 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR0_CSPR
382 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
383 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
384 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
385 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
386 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
387 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
388 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NAND_CSPR_EXT
389 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NAND_CSPR
390 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NAND_AMASK
391 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NAND_CSOR
392 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NAND_FTIM0
393 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NAND_FTIM1
394 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NAND_FTIM2
395 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NAND_FTIM3
396 #endif
397 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR1_CSPR_EXT
398 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR1_CSPR
399 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
400 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
401 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
402 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
403 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
404 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
405
406 #ifdef CONFIG_SPL_BUILD
407 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
408 #else
409 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
410 #endif
411
412 #if defined(CONFIG_RAMBOOT_PBL)
413 #define CONFIG_SYS_RAMBOOT
414 #endif
415
416 #define CONFIG_BOARD_EARLY_INIT_R
417 #define CONFIG_MISC_INIT_R
418
419 #define CONFIG_HWCONFIG
420
421 /* define to use L1 as initial stack */
422 #define CONFIG_L1_INIT_RAM
423 #define CONFIG_SYS_INIT_RAM_LOCK
424 #define CONFIG_SYS_INIT_RAM_ADDR        0xfdd00000      /* Initial L1 address */
425 #ifdef CONFIG_PHYS_64BIT
426 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH      0xf
427 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW       0xfe03c000
428 /* The assembler doesn't like typecast */
429 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
430         ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
431           CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
432 #else
433 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS   0xfe03c000 /* Initial L1 address */
434 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
435 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
436 #endif
437 #define CONFIG_SYS_INIT_RAM_SIZE                0x00004000
438
439 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - \
440                                         GENERATED_GBL_DATA_SIZE)
441 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
442
443 #define CONFIG_SYS_MONITOR_LEN          (768 * 1024)
444 #define CONFIG_SYS_MALLOC_LEN           (4 * 1024 * 1024)
445
446 /* Serial Port - controlled on board with jumper J8
447  * open - index 2
448  * shorted - index 1
449  */
450 #define CONFIG_CONS_INDEX       1
451 #define CONFIG_SYS_NS16550_SERIAL
452 #define CONFIG_SYS_NS16550_REG_SIZE     1
453 #define CONFIG_SYS_NS16550_CLK          (get_bus_freq(0)/2)
454
455 #define CONFIG_SYS_BAUDRATE_TABLE       \
456         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
457
458 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
459 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
460 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
461 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
462
463 /* I2C */
464 #define CONFIG_SYS_I2C
465 #define CONFIG_SYS_I2C_FSL              /* Use FSL common I2C driver */
466 #define CONFIG_SYS_FSL_I2C_SPEED        400000  /* I2C speed in Hz */
467 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
468 #define CONFIG_SYS_FSL_I2C2_SPEED       400000  /* I2C speed in Hz */
469 #define CONFIG_SYS_FSL_I2C2_SLAVE       0x7F
470 #define CONFIG_SYS_FSL_I2C_OFFSET       0x118000
471 #define CONFIG_SYS_FSL_I2C2_OFFSET      0x119000
472
473 /*
474  * RTC configuration
475  */
476 #define RTC
477 #define CONFIG_RTC_DS3231               1
478 #define CONFIG_SYS_I2C_RTC_ADDR         0x68
479
480 /*
481  * RapidIO
482  */
483 #ifdef CONFIG_SYS_SRIO
484 #ifdef CONFIG_SRIO1
485 #define CONFIG_SYS_SRIO1_MEM_VIRT       0xa0000000
486 #ifdef CONFIG_PHYS_64BIT
487 #define CONFIG_SYS_SRIO1_MEM_PHYS       0xc20000000ull
488 #else
489 #define CONFIG_SYS_SRIO1_MEM_PHYS       0xa0000000
490 #endif
491 #define CONFIG_SYS_SRIO1_MEM_SIZE       0x10000000      /* 256M */
492 #endif
493
494 #ifdef CONFIG_SRIO2
495 #define CONFIG_SYS_SRIO2_MEM_VIRT       0xb0000000
496 #ifdef CONFIG_PHYS_64BIT
497 #define CONFIG_SYS_SRIO2_MEM_PHYS       0xc30000000ull
498 #else
499 #define CONFIG_SYS_SRIO2_MEM_PHYS       0xb0000000
500 #endif
501 #define CONFIG_SYS_SRIO2_MEM_SIZE       0x10000000      /* 256M */
502 #endif
503 #endif
504
505 /*
506  * for slave u-boot IMAGE instored in master memory space,
507  * PHYS must be aligned based on the SIZE
508  */
509 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
510 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
511 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000       /* 1M */
512 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
513 /*
514  * for slave UCODE and ENV instored in master memory space,
515  * PHYS must be aligned based on the SIZE
516  */
517 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
518 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
519 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000    /* 256K */
520
521 /* slave core release by master*/
522 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
523 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
524
525 /*
526  * SRIO_PCIE_BOOT - SLAVE
527  */
528 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
529 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
530 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
531                 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
532 #endif
533
534 /*
535  * eSPI - Enhanced SPI
536  */
537 #define CONFIG_SF_DEFAULT_SPEED         10000000
538 #define CONFIG_SF_DEFAULT_MODE          0
539
540 /*
541  * MAPLE
542  */
543 #ifdef CONFIG_PHYS_64BIT
544 #define CONFIG_SYS_MAPLE_MEM_PHYS      0xFA0000000ull
545 #else
546 #define CONFIG_SYS_MAPLE_MEM_PHYS      0xA0000000
547 #endif
548
549 /*
550  * General PCI
551  * Memory space is mapped 1-1, but I/O space must start from 0.
552  */
553
554 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
555 #define CONFIG_SYS_PCIE1_MEM_VIRT       0x80000000
556 #ifdef CONFIG_PHYS_64BIT
557 #define CONFIG_SYS_PCIE1_MEM_BUS        0xe0000000
558 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc00000000ull
559 #else
560 #define CONFIG_SYS_PCIE1_MEM_BUS        0x80000000
561 #define CONFIG_SYS_PCIE1_MEM_PHYS       0x80000000
562 #endif
563 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x20000000      /* 512M */
564 #define CONFIG_SYS_PCIE1_IO_VIRT        0xf8000000
565 #define CONFIG_SYS_PCIE1_IO_BUS         0x00000000
566 #ifdef CONFIG_PHYS_64BIT
567 #define CONFIG_SYS_PCIE1_IO_PHYS        0xff8000000ull
568 #else
569 #define CONFIG_SYS_PCIE1_IO_PHYS        0xf8000000
570 #endif
571 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00010000      /* 64k */
572
573 /* Qman/Bman */
574 #ifndef CONFIG_NOBQFMAN
575 #define CONFIG_SYS_DPAA_QBMAN           /* Support Q/Bman */
576 #define CONFIG_SYS_BMAN_NUM_PORTALS     25
577 #define CONFIG_SYS_BMAN_MEM_BASE        0xf4000000
578 #ifdef CONFIG_PHYS_64BIT
579 #define CONFIG_SYS_BMAN_MEM_PHYS        0xff4000000ull
580 #else
581 #define CONFIG_SYS_BMAN_MEM_PHYS        CONFIG_SYS_BMAN_MEM_BASE
582 #endif
583 #define CONFIG_SYS_BMAN_MEM_SIZE        0x02000000
584 #define CONFIG_SYS_BMAN_SP_CENA_SIZE    0x4000
585 #define CONFIG_SYS_BMAN_SP_CINH_SIZE    0x1000
586 #define CONFIG_SYS_BMAN_CENA_BASE       CONFIG_SYS_BMAN_MEM_BASE
587 #define CONFIG_SYS_BMAN_CENA_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
588 #define CONFIG_SYS_BMAN_CINH_BASE       (CONFIG_SYS_BMAN_MEM_BASE + \
589                                         CONFIG_SYS_BMAN_CENA_SIZE)
590 #define CONFIG_SYS_BMAN_CINH_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
591 #define CONFIG_SYS_BMAN_SWP_ISDR_REG    0xE08
592 #define CONFIG_SYS_QMAN_NUM_PORTALS     25
593 #define CONFIG_SYS_QMAN_MEM_BASE        0xf6000000
594 #ifdef CONFIG_PHYS_64BIT
595 #define CONFIG_SYS_QMAN_MEM_PHYS        0xff6000000ull
596 #else
597 #define CONFIG_SYS_QMAN_MEM_PHYS        CONFIG_SYS_QMAN_MEM_BASE
598 #endif
599 #define CONFIG_SYS_QMAN_MEM_SIZE        0x02000000
600 #define CONFIG_SYS_QMAN_SP_CENA_SIZE    0x4000
601 #define CONFIG_SYS_QMAN_SP_CINH_SIZE    0x1000
602 #define CONFIG_SYS_QMAN_CENA_BASE       CONFIG_SYS_QMAN_MEM_BASE
603 #define CONFIG_SYS_QMAN_CENA_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
604 #define CONFIG_SYS_QMAN_CINH_BASE       (CONFIG_SYS_QMAN_MEM_BASE + \
605                                         CONFIG_SYS_QMAN_CENA_SIZE)
606 #define CONFIG_SYS_QMAN_CINH_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
607 #define CONFIG_SYS_QMAN_SWP_ISDR_REG    0xE08
608
609 #define CONFIG_SYS_DPAA_FMAN
610
611 #define CONFIG_SYS_DPAA_RMAN
612
613 /* Default address of microcode for the Linux Fman driver */
614 #if defined(CONFIG_SPIFLASH)
615 /*
616  * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
617  * env, so we got 0x110000.
618  */
619 #define CONFIG_SYS_QE_FW_IN_SPIFLASH
620 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000
621 #elif defined(CONFIG_SDCARD)
622 /*
623  * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
624  * about 545KB (1089 blocks), Env is stored after the image, and the env size is
625  * 0x2000 (16 blocks), 8 + 1089 + 16 = 1113, enlarge it to 1130.
626  */
627 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC
628 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 1130)
629 #elif defined(CONFIG_NAND)
630 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND
631 #define CONFIG_SYS_FMAN_FW_ADDR (13 * CONFIG_SYS_NAND_BLOCK_SIZE)
632 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
633 /*
634  * Slave has no ucode locally, it can fetch this from remote. When implementing
635  * in two corenet boards, slave's ucode could be stored in master's memory
636  * space, the address can be mapped from slave TLB->slave LAW->
637  * slave SRIO or PCIE outbound window->master inbound window->
638  * master LAW->the ucode address in master's memory space.
639  */
640 #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE
641 #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000
642 #else
643 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
644 #define CONFIG_SYS_FMAN_FW_ADDR         0xEFF00000
645 #endif
646 #define CONFIG_SYS_QE_FMAN_FW_LENGTH    0x10000
647 #define CONFIG_SYS_FDT_PAD              (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
648 #endif /* CONFIG_NOBQFMAN */
649
650 #ifdef CONFIG_SYS_DPAA_FMAN
651 #define CONFIG_FMAN_ENET
652 #define CONFIG_PHYLIB_10G
653 #define CONFIG_PHY_VITESSE
654 #define CONFIG_PHY_TERANETICS
655 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C
656 #define SGMII_CARD_PORT2_PHY_ADDR 0x10
657 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E
658 #define SGMII_CARD_PORT4_PHY_ADDR 0x11
659 #endif
660
661 #ifdef CONFIG_PCI
662 #define CONFIG_PCI_INDIRECT_BRIDGE
663
664 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
665 #endif  /* CONFIG_PCI */
666
667 #ifdef CONFIG_FMAN_ENET
668 #define CONFIG_SYS_FM1_ONBOARD_PHY1_ADDR 0x10
669 #define CONFIG_SYS_FM1_ONBOARD_PHY2_ADDR 0x11
670
671 /*B4860 QDS AMC2PEX-2S default PHY_ADDR */
672 #define CONFIG_SYS_FM1_10GEC1_PHY_ADDR 0x7       /*SLOT 1*/
673 #define CONFIG_SYS_FM1_10GEC2_PHY_ADDR 0x6       /*SLOT 2*/
674
675 #define CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR    0x1c
676 #define CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR    0x1d
677 #define CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR    0x1e
678 #define CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR    0x1f
679
680 #define CONFIG_MII              /* MII PHY management */
681 #define CONFIG_ETHPRIME         "FM1@DTSEC1"
682 #endif
683
684 #define CONFIG_SYS_FSL_B4860QDS_XFI_ERR
685
686 /*
687  * Environment
688  */
689 #define CONFIG_LOADS_ECHO               /* echo on for serial download */
690 #define CONFIG_SYS_LOADS_BAUD_CHANGE    /* allow baudrate change */
691
692 /*
693  * Command line configuration.
694  */
695 #define CONFIG_CMD_REGINFO
696
697 /*
698 * USB
699 */
700 #define CONFIG_HAS_FSL_DR_USB
701
702 #ifdef CONFIG_HAS_FSL_DR_USB
703 #ifdef CONFIG_USB_EHCI_HCD
704 #define CONFIG_USB_EHCI_FSL
705 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
706 #endif
707 #endif
708
709 /*
710  * Miscellaneous configurable options
711  */
712 #define CONFIG_SYS_LONGHELP                     /* undef to save memory */
713 #define CONFIG_CMDLINE_EDITING                  /* Command-line editing */
714 #define CONFIG_AUTO_COMPLETE                    /* add autocompletion support */
715 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
716 #ifdef CONFIG_CMD_KGDB
717 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size */
718 #else
719 #define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size */
720 #endif
721 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
722 #define CONFIG_SYS_MAXARGS      16              /* max number of command args */
723 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
724
725 /*
726  * For booting Linux, the board info and command line data
727  * have to be in the first 64 MB of memory, since this is
728  * the maximum mapped by the Linux kernel during initialization.
729  */
730 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20)      /* Initial map for Linux*/
731 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
732
733 #ifdef CONFIG_CMD_KGDB
734 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
735 #endif
736
737 /*
738  * Environment Configuration
739  */
740 #define CONFIG_ROOTPATH         "/opt/nfsroot"
741 #define CONFIG_BOOTFILE         "uImage"
742 #define CONFIG_UBOOTPATH        "u-boot.bin"    /* U-Boot image on TFTP server*/
743
744 /* default location for tftp and bootm */
745 #define CONFIG_LOADADDR         1000000
746
747 #define __USB_PHY_TYPE  ulpi
748
749 #ifdef CONFIG_ARCH_B4860
750 #define HWCONFIG        "hwconfig=fsl_ddr:ctlr_intlv=null,"     \
751                         "bank_intlv=cs0_cs1;"   \
752                         "en_cpc:cpc2;"
753 #else
754 #define HWCONFIG        "hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=cs0_cs1;"
755 #endif
756
757 #define CONFIG_EXTRA_ENV_SETTINGS                               \
758         HWCONFIG                                                \
759         "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
760         "netdev=eth0\0"                                         \
761         "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"                     \
762         "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"                     \
763         "tftpflash=tftpboot $loadaddr $uboot && "               \
764         "protect off $ubootaddr +$filesize && "                 \
765         "erase $ubootaddr +$filesize && "                       \
766         "cp.b $loadaddr $ubootaddr $filesize && "               \
767         "protect on $ubootaddr +$filesize && "                  \
768         "cmp.b $loadaddr $ubootaddr $filesize\0"                \
769         "consoledev=ttyS0\0"                                    \
770         "ramdiskaddr=2000000\0"                                 \
771         "ramdiskfile=b4860qds/ramdisk.uboot\0"                  \
772         "fdtaddr=1e00000\0"                                     \
773         "fdtfile=b4860qds/b4860qds.dtb\0"                               \
774         "bdev=sda3\0"
775
776 /* For emulation this causes u-boot to jump to the start of the proof point
777    app code automatically */
778 #define CONFIG_PROOF_POINTS                     \
779  "setenv bootargs root=/dev/$bdev rw "          \
780  "console=$consoledev,$baudrate $othbootargs;"  \
781  "cpu 1 release 0x29000000 - - -;"              \
782  "cpu 2 release 0x29000000 - - -;"              \
783  "cpu 3 release 0x29000000 - - -;"              \
784  "cpu 4 release 0x29000000 - - -;"              \
785  "cpu 5 release 0x29000000 - - -;"              \
786  "cpu 6 release 0x29000000 - - -;"              \
787  "cpu 7 release 0x29000000 - - -;"              \
788  "go 0x29000000"
789
790 #define CONFIG_HVBOOT   \
791  "setenv bootargs config-addr=0x60000000; "     \
792  "bootm 0x01000000 - 0x00f00000"
793
794 #define CONFIG_ALU                              \
795  "setenv bootargs root=/dev/$bdev rw "          \
796  "console=$consoledev,$baudrate $othbootargs;"  \
797  "cpu 1 release 0x01000000 - - -;"              \
798  "cpu 2 release 0x01000000 - - -;"              \
799  "cpu 3 release 0x01000000 - - -;"              \
800  "cpu 4 release 0x01000000 - - -;"              \
801  "cpu 5 release 0x01000000 - - -;"              \
802  "cpu 6 release 0x01000000 - - -;"              \
803  "cpu 7 release 0x01000000 - - -;"              \
804  "go 0x01000000"
805
806 #define CONFIG_LINUX                            \
807  "setenv bootargs root=/dev/ram rw "            \
808  "console=$consoledev,$baudrate $othbootargs;"  \
809  "setenv ramdiskaddr 0x02000000;"               \
810  "setenv fdtaddr 0x01e00000;"                   \
811  "setenv loadaddr 0x1000000;"                   \
812  "bootm $loadaddr $ramdiskaddr $fdtaddr"
813
814 #define CONFIG_HDBOOT                                   \
815         "setenv bootargs root=/dev/$bdev rw "           \
816         "console=$consoledev,$baudrate $othbootargs;"   \
817         "tftp $loadaddr $bootfile;"                     \
818         "tftp $fdtaddr $fdtfile;"                       \
819         "bootm $loadaddr - $fdtaddr"
820
821 #define CONFIG_NFSBOOTCOMMAND                   \
822         "setenv bootargs root=/dev/nfs rw "     \
823         "nfsroot=$serverip:$rootpath "          \
824         "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
825         "console=$consoledev,$baudrate $othbootargs;"   \
826         "tftp $loadaddr $bootfile;"             \
827         "tftp $fdtaddr $fdtfile;"               \
828         "bootm $loadaddr - $fdtaddr"
829
830 #define CONFIG_RAMBOOTCOMMAND                           \
831         "setenv bootargs root=/dev/ram rw "             \
832         "console=$consoledev,$baudrate $othbootargs;"   \
833         "tftp $ramdiskaddr $ramdiskfile;"               \
834         "tftp $loadaddr $bootfile;"                     \
835         "tftp $fdtaddr $fdtfile;"                       \
836         "bootm $loadaddr $ramdiskaddr $fdtaddr"
837
838 #define CONFIG_BOOTCOMMAND              CONFIG_LINUX
839
840 #include <asm/fsl_secure_boot.h>
841
842 #endif  /* __CONFIG_H */